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ADS61B23EVM
User Manual
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Texas Instruments ADS61B23EVM, ADS61xx User Manual

ADS61xx and ADS61B23EVM
User's Guide
Literature Number: SLAU206B
September 2007 – Revised April 2008
2 SLAU206B – September 2007 – Revised April 2008
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Contents
1 Overview ............................................................................................................................. 5
2 Circuit Description ............................................................................................................... 6
3 TI ADC SPI Control Interface ................................................................................................ 10
3.1 Installing the ADC SPI Control Software ............................................................................. 10
3.2 Setting Up the EVM for ADC SPI Control ............................................................................ 11
3.3 Using the TI ADC SPI Interface Software ............................................................................ 11
4 Connecting to FPGA Platforms ............................................................................................ 13
4.1 TSW1100 ................................................................................................................. 13
4.2 TSW1200 ................................................................................................................. 13
5 ADC Evaluation .................................................................................................................. 14
5.1 Hardware Selection ..................................................................................................... 14
5.2 Coherent Input Frequency Selection .................................................................................. 15
6 Physical Description ........................................................................................................... 16
6.1 PCB Layout ............................................................................................................... 16
6.2 Bill of Materials ........................................................................................................... 21
6.3 EVM Schematics ........................................................................................................ 23
Important Notices ............................................................................................................... 29
SLAU206B – September 2007 – Revised April 2008 Table of Contents 3
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List of Figures
1 TI ADC SPC Interface Screen ........................................................................................... 10
2 Top Silkscreen .............................................................................................................. 16
3 Component Side ............................................................................................................ 17
4 Ground Plane 1 ............................................................................................................. 18
5 Power Plane 1 .............................................................................................................. 19
6 Bottom Side ................................................................................................................. 20
7 EVM Schematic, Sheet 1 .................................................................................................. 23
8 EVM Schematic, Sheet 2 .................................................................................................. 24
9 EVM Schematic, Sheet 3 .................................................................................................. 25
10 EVM Schematic, Sheet 4 .................................................................................................. 26
11 EVM Schematic, Sheet 5 .................................................................................................. 27
12 Breakout Board Schematic, Sheet 6 ..................................................................................... 28
List of Tables
1 Breakout Board Pin Assignments.......................................................................................... 8
2 Jumpers ....................................................................................................................... 9
3 Surface-Mount Jumpers .................................................................................................... 9
4 ADS61xx Frequently Used Registers .................................................................................... 12
5 Bill of Materials ............................................................................................................. 21
4 List of Figures SLAU206B – September 2007 – Revised April 2008
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1 Overview

This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, ADS6145, and ADS61B23, which collectively are referred to as ADS61xx and ADS61B23. The ADS61xx/ADS61B23 EVM provides a platform for evaluating the low-power, single-channel ADS61xx/ADS61B23 12- and 14-bit analog-to-digital converters (ADC), and the ADS61B23 12-bit ADC with buffered analog input under various signal, reference, and supply conditions.
This document should be used in combination with the respective ADC data sheet.

1.1 ADS61xx/ADS61B23 EVM Quick-Start Procedure

Using the quick-start procedure, many users can begin evaluating the ADC in a short time. The quick-start procedure uses the default conditions of the EVM as shipped from the factory. In addition, the quick-start guide configures the ADC in a CMOS offset binary data format. Users who have modified the board may find the quick-start procedure to be ineffective.
1. Supply 3.3 V to J11 while connecting the return to a shorted J11 and J14. Power on the device.
2. Confirm jumper J6 is shorted 1–2 and jumpers J2, J3, and J7 have positions 2–3 shorted.
3. Use the silkscreen to confirm jumper J1 is set to Offset Binary, CMOS output.
4. Use the silkscreen to confirm jumper J4 is set to 0dB Gain, Int Ref.
5. Supply a –1-dBFS filtered, low-phase-noise, 10-MHz CW tone into J8.
6. Supply a filtered, low-phase-noise clock to J9.
7. Use the accompanying breakout board and monitor the digital output (see Table 1 ).
User's Guide
SLAU206B – September 2007 – Revised April 2008
Windows is a registered trademark of Microsoft Corporation. Samtec is a trademark of Samtec, Inc. Xilinx, Virtex are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
SLAU206B – September 2007 – Revised April 2008 5
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Circuit Description

2 Circuit Description

2.1 Schematic Diagram

The schematic diagram for the EVM is in Section 6.3 .

2.2 ADC Circuit Function

The following sections describe the function of individual circuits. See the relevant data sheet for device operating characteristics.

2.2.1 ADC Operational Mode

By default, the ADC is configured to operate in parallel-mode operation, because jumper (J3) asserts a
3.3-V state to the ADC reset pin. Consequently, the SW1 reset pushbutton must be pressed only when the device is configured in serial operation mode. Because the ADC is in parallel operation mode, voltages are used to set the ADC configuration modes. Users can use the EVM silkscreen to set the operation modes.

2.2.2 EVM Power Connections

Power is supplied to the EVM by banana jack sockets. Separate connections are provided for a 3.3-V digital buffer supply (J11) and 3.3-V analog supply (J13); however, by default these are shorted together using R65, a 0- Ω resistor. Consequently, users can supply power to either J11 or J13 to power the ADC. The separate connections allow users to separate analog and digital supplies by removing R65. When using the amplifier evaluation path, connect the positive rail to J20 and the negative rail to J16. The voltages depend on the coupling method and connection to the ADC. If the ADC VCM is not supplied to the amplifier and the amplifier is connected to the ADC in a dc-coupled fashion, set J20 to 4 V and J16 to –1 V. In ac-coupled configurations where the ADC VCM biases the ADC inputs, connect J20 to 5 V and J16 to GND. The ADC SPI interface and CDCP1803 also are powered through J20, which should be set to 5 V for operation of those circuits.
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2.2.3 ADC Analog Inputs

The EVM is configured to accept a single-ended input source and convert it to an ac-coupled differential signal using a transformer. The inputs to the ADC must be dc-biased, which is accomplished by using the ADC VCM output. The input is provided by the SMA connector J8.
Using SMA input J10, users can evaluate the ADC using a THS4509 amplifier, which converts a single-ended input into a differential signal while providing 10 dB of signal gain. Users should enable the amplifier path by connecting JP7 1–2 and by shorting positions 2–3 on both surface-mount jumpers JP5 and JP6. At low input frequencies, the ADC represents a high-input impedance and R38, R46, and C76 form a low-pass filter with a 3-db cutoff frequency of 70 MHz. Users can change these component values depending on the bandwidth of the signal they are digitizing to band-limit the input noise into the ADC. Using an excessively high cutoff frequency degrades the SNR of the system. Before beginning evaluation of the amplifier path, a user must choose whether to dc-couple or ac-couple the amplifier path.
In a dc-coupled system, replace C75 and C77 with 0- Ω resistors and remove R37 and R45. Use the ADC VCM to set the CM input of the amplifier by ensuring that R21 is populated with a 0- Ω resistor. Because the ADC has a common-mode voltage of 1.5 V and because the THS4509 is not a rail-to-rail amplifier, adjust VCC to 4 V and –VCC to –1 V, which can be done by applying the respective voltages to J20 and J16.
For an ac-coupled system, use the voltage divider R37 and R45 to set the common-mode input of the amplifier, which should be set to the midpoint of the amplifier supply. Alternatively, users can leave R37 and R45 unpopulated and the amplifier sets its own common voltage to (VCC – VEE)/2. Capacitors C75 and C77 provide ac-coupling of the system, and the ADC inputs then can be biased by the R41 and R42 combination. Another ac-coupled approach, not supported on this EVM, is to use a transformer at the outputs of the THS4509. In this case, the transformer provides for ac-coupling, and the inputs of the ADC can be biased by feeding the ADC VCM to the transformer center tap on the secondary.
6 SLAU206B – September 2007 – Revised April 2008
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Note that the THS4509 used on this EVM is pinout compatible with the THS4508 , THS4511 , THS4513 , and THS4520 . Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common-mode range, power supplies, and frequency of operation. Contact your local Texas Instruments (TI) sales representative for assistance in selection of these amplifiers.

2.2.4 ADC Clock Input

Connect a filtered, low-phase-noise clock input to J9. A transformer, T3, provides the conversion from a single-ended clock signal into a differential clock signal.
The EVM also provides a clock distribution path using the CDCP1803. The CDCP1803 provides for a 1:3 LVDS fanout helpful when clocking multiple ADCs from the same clocking source. Users selecting this input path should use a low-jitter square-wave input. In addition, the CDCP1803 jitter performance makes this a valid clocking solution only for input frequencies in the first Nyquist zone, as jitter degrades SNR for frequencies much above the first Nyquist zone. To use this path, change jumper JP8 to short 1–2, and JP2, JP3, and JP4 to short pins 2–3.

2.2.5 ADC Digital Outputs

The ADS61xx/ADS61B23 ADC parallel digital outputs are brought to J10, a high-density Samtec™ connector. Several options are available in processing the ADC data.
1. The mating logic analyzer breakout board can capture the ADC data using a logic analyzer. Users who choose this option should use the companion breakout board and Table 1 for the connection details. Users lacking access to a logic analyzer can use the TSW1100 to capture the digital data. See the connection guidelines in Section 4.1 .
2. Users can create their own digital interface board which directly interfaces to the ADC. In this case, they design their mating digital interface board with the Samtec part number QSO-060-01-F-D-A, which is the companion part number to the EVM connector.
Circuit Description
SLAU206B – September 2007 – Revised April 2008 7
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Circuit Description
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Table 1. Breakout Board Pin Assignments
J4 PIN ADS6142/43/44/45 DESCRIPTION
1 GND GND 2 CLK CLK 3 GND GND 4 NC NC 5 GND GND 6 NC Data bit 0 (LSB) 7 GND GND 8 NC Data bit 1
9 GND GND 10 Data bit 0 (LSB) Data bit 2 11 GND GND 12 Data bit 1 Data bit 3 13 GND GND 14 Data bit 2 Data bit 4 15 GND GND 16 Data bit 3 Data bit 5 17 GND GND 18 Data bit 4 Data bit 6 19 GND GND 20 Data bit 5 Data bit 7 21 GND GND 22 Data bit 6 Data bit 8 23 GND GND 24 Data bit 7 Data bit 9 25 GND GND 26 Data bit 8 Data bit 10 27 GND GND 28 Data bit 9 Data bit 11 29 GND GND 30 Data bit 10 Data bit 12 31 GND GND 32 Data bit 11 (MSB) Data bit 13 (MSB) 33 GND GND 34 NC NC 35 GND GND 36 NC NC 37 GND GND 38 NC NC 39 GND GND 40 NC NC
ADS6122/23/B23/24/25
DESCRIPTION

2.2.6 Jumper Selections

The EVM features several jumpers whose functions are described in Table 2 . The EVM also features surface-mount jumpers in cases where either the signal integrity is important or the functions are rarely used. Table 3 summarizes these options.
8 SLAU206B – September 2007 – Revised April 2008
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Circuit Description
Table 2. Jumpers
Description Reference Designator Default Selection Optional Selection
Parallel mode: SEN pin J1 5–6, Offset binary, CMOS output Multiple choices voltage bias
SEN control J2 2–3, EVM controlled 1–2, USB or FPGA
ADC control mode J3 2–3, Parallel mode 1–2, serial mode Parallel mode: SCLK pin J4 1–2, 0-dB Gain, Int Ref Multiple choices
voltage bias ADS61xx/ADS61B23 J5 1–2, ADS61xx/ADS61B23 powered on 2–3, ADS61xx/ADS61B23
power down powered off SDATA control J6 1–2, USB or FPGA controlled 2–3, EVM controlled SCLK control J7 2–3, EVM controlled 2–3, USB or FPGA
controlled
controlled
Table 3. Surface-Mount Jumpers
Description Reference Designator Default Selection Optional Selection
JP1 Probe point for CDCP1803 output Clock input path selection JP2 1–2, transformer coupled path 2–3, CDCP1803 path Clock input path selection JP3 1–2, transformer coupled path 2–3, CDCP1803 path Clock input path selection JP4 1–2, transformer coupled path 2–3, CDCP1803 path Analog input path JP5 1–2, transformer coupled input path 2–3, THS4509 path Analog input path JP6 1–2, transformer coupled input path 2–3, THS4509 path THS4509 power down JP7 2–3, THS4509 powered down 1–2, THS4509 powered
CDCP1803 power down JP8 2–3, CDCP1803 powered down 1–2, CDCP1803 powered
on
on
SLAU206B – September 2007 – Revised April 2008 9
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