Texas Instruments ADS58J63 Datasheet

CLKINP/M

DAP/MINAP/M

PLL

x10/x20

DCP/M

DDP/M

14bit ADC

INBP/M

INCP/M

14bit ADC

INDP/M

DBP/M

JESD204B

SYNCbCD

SYSREFP/M

RESET

SCLK

SEN

SDIN

SDOUT

Configuration

Registers

Digital Block

Interleaving

Correction

14bit ADC

Digital Block

Interleaving

Correction

Digital Block

Interleaving

Correction

Digital Block

Interleaving

Correction

SYNCbAB

TRIGAB

TRIGCD

TRDYCD

JESD204B

TRDYAB

Burst Mode

4x

K*FS/16

FS/8

2x

FS/4

2x

4x

K*FS/16

FS/8

2x

FS/4

2x

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Tools & Software

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ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device

1 Features 3 Description

1

• Quad Channel

• 14-Bit Resolution

• Maximum Clock Rate: 500 MSPS

• Input Bandwidth (3 dB): 900 MHz

• On-Chip Dither

• Analog Input Buffer with High-Impedance Input

• Output Options: – Rx: Decimate-by-2 and -4 Options with Low-

Pass Filter

– 200-MHz Complex Bandwidth or 100-MHz

Real Bandwidth Support

– DPD FB: Burst Mode with 14-Bit Output

• 1.9-VPPDifferential Full-Scale Input

• JESD204B Interface: – Subclass 1 Support – 1 Lane per ADC Up to 10 Gbps – Dedicated SYNC pin for pair of channels

• Support for Multi-Chip Synchronization

• 72-Pin VQFN Package (10 mm × 10 mm)

• Key Specifications: – Power Dissipation: 675 mW/ch – Spectral Performance (Un-decimated)

– fIN= 190 MHz IF at –1 dBFS:

– SNR: 70.4 dBFS – NSD: –154.4 dBFS/Hz – SFDR: 86 dBc (HD2, HD3),

95 dBFS (non HD2, HD3)

– fIN= 370 MHz IF at –3 dBFS:

– SNR: 68.5 dBFS – NSD: –152.5 dBFS/Hz – SFDR: 81 dBc (HD2, HD3),

86 dBFS (non HD2, HD3)

The ADS58J63 is a low-power, wide-bandwidth, 14bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

ADS58J63 VQFN (72) 10.00 mm x 10.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Block Diagram

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

(1)

2 Applications

• Multi-Carrier GSM Cellular Infrastructure Base

• Multi-Carrier Multi-Mode Cellular Infrastructure

Stations

Base Stations

• Telecommunications Receiver

• Telecom DPD Observation Receiver

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS58J63

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4 Revision History

Changes from Original (June 2015) to Revision A Page

• Changed From Product Preview To Production datasheet ................................................................................................... 1

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

DDP

DGND

DDM

SYNCbCDM

NC

AVDD

AVDD3V

INCP

TRDYCD

DGND

DBP

DAM

AVDD

SEN

SDIN

SCLK

AVDD

DVDD

AVDD3V

AVDD

SDOUT

ADS58J63

GND PAD (backside)

DGND

RES

RESET

IOVDD

DAP

DBM

DGND

IOVDD

PDN

IOVDD

DVDD

AVDD

AVDD3V

AVDD

INAP

INAM

AVDD3V

AVDD

INBM

SYSREFP

AGND

AVDD3V

AGND

CLKINM

CLKINP

AGND

AVDD

NC

DCM

DCP

IOVDD

SYNCbCDP

TRIGCD

DGND

IOVDD

AVDD3V

INDM

INDP

17

18

AVDD

INCM

36

INBP

AVDD

54

53

TRDYAB

TRIGAB

56 55

SYNCbABP

SYNCbABM

35

AGND

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5 Pin Configuration and Functions

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

RMP Package

VQFN-72

Top View

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Pin Functions

NAME NUMBER

INPUT/REFERENCE

INAP/M 42, 41 I Differential analog input for channel A INBP/M 36, 37 I Differential analog input for channel B INCP/M 19, 18 I Differential analog input for channel C INDP/M 13, 14 I Differential analog input for channel D

CLOCK/SYNC

CLKINP/M 27, 28 I Differential clock input for ADC SYSREFP/M 33, 34 I External sync input

CONTROL/SERIAL

RESET 48 I Hardware reset. Active high. This pin has an internal 150-kΩ pull-down resistor. SCLK 6 I Serial interface clock input SDIN 5 I Serial interface data input. SEN 7 I Serial interface enable SDOUT 11 O Serial interface data output. PDN 50 I/O Power down. Can be configured via SPI register setting. RES 49 – Reserve Pin. Connect to GND NC 22, 23 – No connect

TRDYAB 54 O

TRIGAB 53 I

TRDYCD 1 O

TRIGCD 2 I

DATA INTERFACE

DAP/M 58, 59 O JESD204B Serial data output for channel A DBP/M 61, 62 O JESD204B Serial data output for channel B DCP/M 66, 65 O JESD204B Serial data output for channel C DDP/M 69, 68 O JESD204B Serial data output for channel D

SYNCbABP/M 55, 56 I

SYNCbCDP/M 72, 71 I

POWER SUPPLY

AVDD3V I Analog 3 V for analog buffer

AVDD I Analog 1.9-V power supply

DVDD 8, 47 I Digital 1.9-V power supply IOVDD I Digital 1.15-V power supply for the JESD204B transmitter AGND 21, 26, 29, 32 I Analog ground DGND I Digital ground

10, 16, 24, 31,

39, 45

9, 12, 15, 17, 20, 25, 30, 35, 38, 40, 43, 44,

46

4, 51, 57, 64,

70

3, 52, 60, 63,

67

I/O DESCRIPTION

Trigger ready output for burst mode for channel A,B. Can be configured via SPI to TRDY signal for all four channels in burst mode. Can be left open if not used.

Manual burst mode trigger input channel A,B. Can be configured via SPI to manual trigger input signal for all four channels in burst mode. Can be connected to GND if not used.

Trigger ready output for burst mode for channel C,D. Can be configured via SPI to TRDY signal for all four channels in burst mode. Can be left open if not used.

Manual burst mode trigger input channel C,D. Can be configured via SPI to manual trigger input signal for all four channels in burst mode. Can be connected to GND if not used.

Synchronization input for JESD204B port channel A,B. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination.

Synchronization input for JESD204B port channel C,D. Can be configured via SPI to SYNCb signal for all four channels. Needs external termination.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

AVDD3V –0.3 3.6 V

Supply voltage range:

AVDD –0.3 2.1 V DVDD –0.3 2.1 V IOVDD –0.2 1.4 V

Voltage between AGND and DGND –0.3 0.3 V

INA/BP, INA/BM, INC/DP, INC/DM –0.3 3 V CLKINP, CLKINM –0.3 AVDD + 0.3 V

Voltage applied to input pins

SYSREFP, SYSREFM, TRIGAB, TRIGCD –0.3 AVDD + 0.3 V SCLK, SEN, SDIN, RESET, SPI_MODE,

SYNCbABP/M, SYNCbCDP/M, PDN

Storage temperature, T

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

MIN MAX UNIT

–0.2 2 V

–65 150 °C

VALUE UNIT

(1)

±1 kV

6.3 Recommended Operating Conditions

(1)

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

AVDD3V 2.85 3 3.6 V

Supply voltage range:

Analog inputs:

Differential input voltage range 1.9 V Input common-mode voltage VCM ± 0.025 V Input clock frequency, device clock frequency 250 500 MHz

Clock inputs: LVPECL, ac-coupled 1.6 V

Input clock amplitude differential (V

– V

CLKM

)

CLKP

Input device clock duty cycle, default after reset 45% 50% 55%

Temperature:

(1) SYSREF needs to be applied for the device bring up. (2) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.

AVDD 1.8 1.9 2 V DVDD 1.8 1.9 2 V IOVDD 1.1 1.15 1.2 V

Sine wave, ac-coupled 1.5 V

LVDS, ac-coupled 0.7 V

Operating free-air, T Operating junction, T

A

J

–40 85 ºC

(2)

105

125 ºC

PP

PP PP PP

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6.4 Thermal Information

ADS58J63

THERMAL METRIC

(1)

RMP (VQFNP) UNIT

72 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 22.3 Junction-to-case (top) thermal resistance 5.1 Junction-to-board thermal resistance 2.4 Junction-to-top characterization parameter 0.1 Junction-to-board characterization parameter 2.3 Junction-to-case (bottom) thermal resistance 0.4

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Typical values are at TA= 25°C, full temperature range is from T Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC Sampling Rate 500 MSPS Resolution 14 Bits POWER SUPPLY

AVDD3V 2.85 3 3.6 V AVDD 1.8 1.9 2 V DVDD 1.8 1.9 2 V IOVDD 1.1 1.15 1.2 V I

AVDD3V

I

AVDD

I

DVDD

I

IOVDD

Pdis Total power dissipation

ANALOG INPUTS

3-V analog supply current 340 mA

1.9-V analog supply current 365 mA

1.9-V digital supply current

1.15-V SERDES supply

2x Decimation (4 ch) 190 mA

Burst Mode (4 ch)

current

2x Decimation (4 ch) 2.68 W Burst Mode (4 ch) 2.67 W

Global power-down power dissipation

Differential input full-scale voltage

Input common-mode voltage V Diffrential input resistance at fIN=370MHz 0.5 kΩ

Differential input capacitance at fIN=370MHz 2.5 pF Analog input bandwidth (3 dB) 900 MHz

= –40°C to T

MIN

370-MHz, full-scale input on all four channels

= 85°C, ADC Sampling Frequency = 500

MAX

184 mA 533 mA

250 mW

1.9 V

VCM ±

0.025

PP

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Electrical Characteristics (continued)

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISOLATION

fIN= 10 MHz 105 dBFS

Isolation between near channels (CHA and CHB are near to each other. CHC and CHD are near to each other)

Crosstalk

(1)

Isolation between far channels (for CHA and CHB, CHC and CHD are far channels)

CLOCK INPUT

Internal clock biasing 1.15 V

(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.

fIN= 100 MHz 104 dBFS fIN= 170 MHz 96 dBFS fIN= 270 MHz 97 dBFS fIN= 370 MHz 93 dBFS fIN= 470 MHz 85 dBFS fIN= 10 MHz 110 dBFS fIN= 100 MHz 107 dBFS fIN= 170 MHz 96 dBFS fIN= 270 MHz 97 dBFS fIN= 370 MHz 95 dBFS fIN= 470 MHz 94 dBFS

CLKINP and CLKINM pins are connected to internal biasing voltage through 400 Ω

6.6 AC Performance

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

14-Bit Burst Mode Decimate-by-2 Filter

(DDC Mode 8) (DDC Mode 2) fIN= 10 MHz 70.8 74.1 fIN= 70 MHz 70.5 74

fIN= 190 MHz

SNR Signal-to-noise ratio dBFS

NSD Noise spectral density

fIN= 300 MHz 69 72.6 fIN= 350 MHz 68.7 72 fIN= 370 MHz 64.6 68.4 fIN= 470 MHz 67.5 70.7 fIN= 10 MHz 154.8 154.8 fIN= 70 MHz 154.5 154.5

fIN= 190 MHz

fIN= 300 MHz 153 153.0 fIN= 350 MHz 152.7 152.7 fIN= 370 MHz 148.5 152.4 152.4 fIN= 470 MHz 151.5 151.5

AIN= – 1 dBFS 69.5 73.2 AIN= – 3 dBFS 65.6 70.3 73.6

AIN= – 1 dBFS 153.5 153.5 AIN= – 3 dBFS 149.5 154.3 154.3

dBFS/

Hz

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AC Performance (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

fIN= 10 MHz 70.7 73.9 fIN= 70 MHz 70.4 73.9

SINAD dBFS

SFDR dBc

HD2 dBc

HD3 Third harmonic distortion dBc

Non Spurious-free dynamic HD2, range (excluding HD2, dBc HD3 HD3)

Signal-to-noise and distortion ratio

Spurious-free dynamic range

Second harmonic distortion

fIN= 190 MHz

fIN= 300 MHz 68.9 72.5 fIN= 350 MHz 68.6 71.7 fIN= 370 MHz 68.2 fIN= 470 MHz 66.9 69.7 fIN= 10 MHz 89 88 fIN= 70 MHz 87 95

fIN= 190 MHz

fIN= 300 MHz 82 94 fIN= 350 MHz 82 82 fIN= 370 MHz 75 81 fIN= 470 MHz 73 74 fIN= 10 MHz 89 91 fIN= 70 MHz 94 103

fIN= 190 MHz

fIN= 300 MHz 82 97 fIN= 350 MHz 82 82 fIN= 370 MHz 75 81 fIN= 470 MHz 73 74 fIN= 10 MHz 93 88 fIN= 70 MHz 87 99

fIN= 190 MHz

fIN= 300 MHz 95 100 fIN= 350 MHz 90 96 fIN= 370 MHz 75 85 fIN= 470 MHz 83 83 fIN= 10 MHz 94 98 fIN= 70 MHz 94 95

fIN= 190 MHz

fIN= 300 MHz 92 94 fIN= 350 MHz 91 94 fIN= 370 MHz 80 90 fIN= 470 MHz 87 93

AIN= – 1 dBFS 69.4 73.1 AIN= – 3 dBFS 70.2 73.5

AIN= – 1 dBFS 86 97 AIN= – 3 dBFS 78 88 96

AIN= – 1 dBFS 86 101 AIN= – 3 dBFS 78 88 101

AIN= – 1 dBFS 98 100 AIN= – 3 dBFS 78 97 98

AIN= – 1 dBFS 93 97 AIN= – 3 dBFS 87 93 96

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AC Performance (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

fIN= 10 MHz 88 86 fIN= 70 MHz 85 92

fIN= 190 MHz

THD Total harmonic distortion dBc

IMD3 AIN= – 7 dBFS 82 dBFS

Third-tone intermodulation fIN= 365 MHz, fIN= distortion 370 MHz

fIN= 300 MHz 81 89 fIN= 350 MHz 79 82 fIN= 370 MHz 78 fIN= 470 MHz 72 73 fIN= 185 MHz, fIN=

190 MHz

fIN= 465 MHz, fIN= 470 MHz

AIN= – 1 dBFS 85 92 AIN= – 3 dBFS 86 91

AIN= – 7 dBFS 89

AIN= – 7 dBFS 77

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6.7 Digital Characteristics

Typical values are at TA= 25°C, full temperature range is from T MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)

V

IH

V

IL

I

IH

I

IL

High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.8 V Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.4 V

High-level input current

Low-level input current

DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)

V

D

V

(CM_DIG)

Differential Input Voltage 0.35 0.45 1.4 V Common-mode voltage for SYSREF 1.3 V

DIGITAL OUTPUTS (SDOUT, PDN)

V

OH

V

OL

High-level output voltage DVDD V Low-level output voltage 0.1 V

DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)

V

OD

V

OC

Output differential voltage With default swing setting. 700 mV Output common-mode voltage 450 mV

Transmitter short-circuit current –100 100 mA

z

os

Single-ended output impedance 50 Ω Output capacitance 2 pF

(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ

(typical) pull up resistor to IOVDD.

(2) 50-Ω, single-ended external termination to IOVDD.

(1)

SEN 0 µA RESET, SCLK, SDIN, PDN 100 µA SEN 50 µA RESET, SCLK, SDIN, PDN 0 µA

(2)

Transmitter pins shorted to any voltage between –0.25 V and 1.45 V

Output capacitance inside the device, from either output to ground

= –40°C to T

MIN

= 85°C, ADC sampling rate = 500

MAX

DVDD –

0.1

PP

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CLKINM

Data Latency: 77 Clock Cycles

N

T

PD

CLKINP

DAP/M

DBP/M DCP/M DDP/M

SAMPLE N SAMPLE N+1SAMPLE N-1

D

20

D1D

20

SAMPLE

N+1

N+2

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6.8 Timing Characteristics

Typical values are at TA= 25°C, full temperature range is from T MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted.

SAMPLE TIMING CHARACTERISTICS

Aperture delay 0.75 1.6 ns Aperture delay matching between two channels on the same device ±70 ps Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps Aperture jitter 135 fSrms Wake-up time to valid data after coming out of global power-down 150 µs

Data Latency

OVR Latency ADC sample to OVR bit 44 Clock

t

PDI

t

SU_SYSREF

t

H_SYSREF

JESD OUTPUT INTERFACE TIMING CHARACTERISTICS

tR, t

Clock propagation delay 4 ns Setup time for SYSREF, referenced to input clock rising edge 300 900 ps

Hold time for SYSREF, referenced to input clock rising edge 100 ps

Unit interval 100 400 ps Serial output data rate 2.5 10 Gbps Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output

F

waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps

(1) Overall ADC Latency = Data Latency + t

(1)

ADC sample to digital output 77 Clock

Input clock rising edge cross-over to output clock rising edge cross-over

PDI

= –40°C to T

MIN

= 85°C, ADC sampling rate = 500

MAX

MIN TYP MAX UNITS

35 ps

Input

Cycles

Input

Cycles

Figure 1. Latency Timing Diagram

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Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D005

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D006

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D003

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D004

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D001

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D002

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6.9 Typical Characteristics: 14-Bit Burst Mode

Typical values are at TA= 25°C, full temperature range is from T Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (Non23) SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (Non23)

FIN= 10 MHz , AIN= –1 dBFS FIN= 140 MHz , AIN= –1 dBFS

Figure 2. FFT for 10-MHz Input Signal Figure 3. FFT for 140-MHz Input Signal

FIN= 190 MHz , AIN= –1 dBFS FIN= 230 MHz , AIN= –1 dBFS

SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (Non23) SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (Non23)

Figure 4. FFT for 190-MHz Input Signal Figure 5. FFT for 230-MHz Input Signal

SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (Non23) SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (Non23)

FIN= 300 MHz , AIN= - 3 dBFS FIN= 370 MHz , AIN= - 3 dBFS

Figure 6. FFT for 300-MHz Input Signal Figure 7. FFT for 370-MHz Input Signal

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Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D011

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D012

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D009

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D010

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D007

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D008

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Typical Characteristics: 14-Bit Burst Mode (continued)

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (Non23) Each tone at -7 dBFS

FIN= 470 MHz , AIN= - 3 dBFS F

Figure 8. FFT for 470-MHz Input Signal Figure 9. FFT for Two-Tone Input Signal

= 185 MHz, F

IN1

= 190 MHz, IMD = 89 dBFS

IN2

F

= 185 MHz, F

IN1

IN2

Each tone at -36 dBFS Each tone at -7 dBFS

Figure 10. FFT for Two-Tone Input Signal Figure 11. FFT for Two-Tone Input Signal

F

= 370 MHz, F

IN1

Figure 12. FFT for Two-Tone Input Signal Figure 13. FFT for Two-Tone Input Signal

IN2

Each tone at -36 dBFS Each tone at -7 dBFS

= 190 MHz, IMD = 103 dBFS F

= 365 MHz, IMD = 102 dBFS F

Product Folder Links: ADS58J63

= 370 MHz, F

IN1

= 470 MHz, F

IN1

= 365 MHz, IMD = 81.7 dBFS

IN2

= 465 MHz, IMD = 76.7 dBFS

IN2

Input Frequency (MHz)

SFDR (dBc)

0 40 80 120 160 200 240 280 320 360 400 440 480

72

76

80

84

88

92

96

D017

Ain = -1 dBFS Ain = -3 dBFS

Input Frequency (MHz)

Interleaving Spur (dBc)

0 40 80 120 160 200 240 280 320 360 400 440 480

78

81

84

87

90

93

96

D018

Each Tone Amplitude (dBFS)

IMD (dBFS)

-35 -31 -27 -23 -19 -15 -11 -7

-104

-100

-96

-92

-88

-84

-80

D015

Each Tone Amplitude (dBFS)

IMD (dBFS)

-35 -31 -27 -23 -19 -15 -11 -7

-104

-98

-92

-86

-80

-74

D016

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D013

Each Tone Amplitude (dBFS)

IMD (dBFS)

-35 -31 -27 -23 -19 -15 -11 -7

-104

-102

-100

-98

-96

-94

-92

-90

-88

D014

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical Characteristics: 14-Bit Burst Mode (continued)

www.ti.com

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

F

= 470 MHz, F

IN1

Figure 14. FFT for Two-Tone Input Signal

= 465 MHz, IMD = 98.8 dBFS F

IN2

Each tone at -36 dBFS

= 185 MHz, F

IN1

= 190 MHz

IN2

Figure 15. Intermodulation Distortion Vs Input Amplitude

F

= 365 MHz, F

IN1

Figure 16. Intermodulation Distortion Vs Input Amplitude Figure 17. Intermodulation Distortion Vs Input Amplitude

Figure 18. Spurious-Free Dynamic Range vs Input Figure 19. IL Spur Vs Input Frequency

= 370 MHz F

IN2

Frequency

Product Folder Links: ADS58J63

= 465 MHz, F

IN1

= 470 MHz

IN2

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

80

81

82

83

84

D023

AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V

AVDD = 1.95 V AVDD = 2 V

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

69.4

69.8

70.2

70.6

71

71.4

D024

DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V

DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

85

87

89

91

93

D021

AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V

AVDD = 1.95 V AVDD = 2 V

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

66

67

68

69

70

71

72

D022

AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V

AVDD = 1.95 V AVDD = 2 V

Input Frequency (MHz)

SNR (dBFS)

0 40 80 120 160 200 240 280 320 360 400 440 480

66.5

67.5

68.5

69.5

70.5

71.5

D019

AIN = -1 dBFS AIN = -3 dBFS

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

68

68.8

69.6

70.4

71.2

72

D020

AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V

AVDD = 1.95 V AVDD = 2 V

www.ti.com

Typical Characteristics: 14-Bit Burst Mode (continued)

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

FIN= 190 MHz, AIN= – 1 dBFS

Figure 20. Signal-to-Noise Ratio vs Input Frequency Figure 21. Signal-to-Noise Ratio vs AVDD Supply and

Temperature

FIN= 190 MHz, AIN= – 1 dBFS FIN= 370 MHz, AIN= – 3 dBFS

Figure 22. Spurious-Free Dynamic Range vs AVDD Supply Figure 23. Signal-to-Noise Ratio vs AVDD Supply and

and Temperature Temperature

Figure 24. Spurious-Free Dynamic Range vs AVDD Supply Figure 25. Signal-to-Noise Ratio vs DVDD Supply and

FIN= 370 MHz, AIN= – 3 dBFS FIN= 190 MHz, AIN= – 1 dBFS

and Temperature Temperature

Product Folder Links: ADS58J63

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

86

87

88

89

90

91

92

D029

AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V

AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

67

68

69

70

71

72

73

D030

AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V

AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

80

81

82

83

84

D027

DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V

DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

69.2

69.7

70.2

70.7

71.2

71.7

72.2

D028

AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V

AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

86

87

88

89

90

91

92

D025

DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V

DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V

Temperature (°C)

SNR (dBFS)

-40 -15 10 35 60 85

67

68

69

70

71

D026

DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V

DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical Characteristics: 14-Bit Burst Mode (continued)

www.ti.com

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

FIN= 190 MHz, AIN= – 1 dBFS FIN= 370 MHz, AIN= – 3 dBFS

Figure 26. Spurious-Free Dynamic Range vs DVDD Supply Figure 27. Signal-to-Noise Ratio vs DVDD Supply and

and Temperature Temperature

FIN= 370 MHz, AIN= – 3 dBFS FIN= 190 MHz, AIN= – 1 dBFS

Figure 28. Spurious-Free Dynamic Range vs DVDD Supply Figure 29. Signal-to-Noise Ratio vs AVDD3V Supply and

and Temperature Temperature

Figure 30. Spurious-Free Dynamic Range vs AVDD3V Figure 31. Signal-to-Noise Ratio vs AVDD3V Supply and

FIN= 190 MHz, AIN= – 1 dBFS FIN= 370 MHz, AIN= – 3 dBFS

Supply and Temperature Temperature

Product Folder Links: ADS58J63

Differential Clock Amplitude (Vpp)

SNR (dBFS)

SFDR (dBc)

0.2 0.6 1 1.4 1.8 2.2

60 0

63 25

66 50

69 75

72 100

75 125

D035

SNR SFDR

Input Clock Duty Cycle (%)

SNR (dBFS)

SFDR (dBc)

30 35 40 45 50 55 60 65 70

68 70

69 75

70 80

71 85

72 90

73 95

D036

SNR SFDR

Amplitude (dBFS)

SNR (dBFS)

SFDR (dBc,dBFS)

-70 -60 -50 -40 -30 -20 -10 0

65 0

66.5 30

68 60

69.5 90

71 120

72.5 150

74 180

D033

SNR (dBFS) SFDR (dBc) SFDR (dBFS)

Differential Clock Amplitude (Vpp)

SNR (dBFS)

SFDR (dBc)

0.2 0.6 1 1.4 1.8 2.2

65 60

67 70

69 80

71 90

73 100

75 110

D034

SNR SFDR

Temperature (°C)

SFDR (dBc)

-40 -15 10 35 60 85

80

81

82

83

84

D031

AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V

AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V

Amplitude (dBFS)

SNR (dBFS)

SFDR (dBc,dBFS)

-70 -60 -50 -40 -30 -20 -10 0

64 25

66 50

68 75

70 100

72 125

74 150

D032

SNR (dBFS) SFDR (dBc) SFDR (dBFS)

www.ti.com

Typical Characteristics: 14-Bit Burst Mode (continued)

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

FIN= 370 MHz, AIN= – 3 dBFS FIN= 190 MHz

Figure 32. Spurious-Free Dynamic Range vs AVDD3V Figure 33. Performance vs Amplitude

Supply and Temperature

FIN= 370 MHz FIN= 190 MHz, AIN= – 1 dBFS

Figure 34. Performance vs Amplitude Figure 35. Performance vs Clock Amplitude

FIN= 370 MHz, AIN= – 3 dBFS FIN= 190 MHz, AIN= – 1 dBFS

Figure 36. Performance vs Clock Amplitude Figure 37. Performance vs Clock Duty Cycle

Product Folder Links: ADS58J63

Frequency of Input Common-Mode Signal (MHz)

CMRR (dB)

0 50 100 150 200 250 300

-60

-55

-50

-45

-40

-35

-30

-25

-20

D041

Sampling Speed (MSPS)

Power Consumption (W)

250 300 350 400 450 500

0

0.8

1.6

2.4

3.2

4

D042

AVDD_Power (W) DVDD_Power (W) AVDD3V_Power (W)

IOVDD_Power (W) TotalPower (W)

Frequency of Signal on Supply (MHz)

PSRR (dB)

0 50 100 150 200 250 300

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

D039

PSRR with 50-mVPP Signal on AVDD PSRR with 50-mVPP Signal on AVDD3V

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D040

Input Clock Duty Cycle (%)

SNR (dBFS)

SFDR (dBc)

30 35 40 45 50 55 60 65 70

65 69

66 72

67 75

68 78

69 81

70 84

71 87

72 90

D037

SNR SFDR

Input Frequency (MHz)

Amplitude (dBFS)

0 50 100 150 200 250

-120

-100

-80

-60

-40

-20

0

D038

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

Typical Characteristics: 14-Bit Burst Mode (continued)

www.ti.com

Typical values are at TA= 25°C, full temperature range is from T

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500

MAX

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

FIN= 370 MHz, AIN= – 3 dBFS FIN= 190 MHz , AIN= –1 dBFS

Figure 38. Performance vs Clock Duty Cycle

SFDR = 49 dBc, f

PSRR

= 5 MHz, A

PSRR

= 50 mVPP

Figure 39. Power-Supply Rejection Ratio FFT for test signal

on AVDD Supply

FIN= 190 MHz, AIN= – 1 dBFS FIN= 190 MHz , AIN= – 1 dBFS

Figure 40. Power-Supply Rejection Ratio vs Supplies

50-mVPP test-Signal on input common mode

FIN= 190 MHz, AIN= – 1dBFS

Figure 42. Common-Mode Rejection Ratio

SFDR = 81 , f

CMRR

= 5 MHz, A

CMRR

= 50 mVPP

Figure 41. Common-Mode Rejection Ratio FFT

Figure 43. Power vs Chip Clock

Product Folder Links: ADS58J63

Input Frequency (MHz)

Amplitude (dBFS)

0 25 50 75 100 125

-120

-100

-80

-60

-40

-20

0

D045

Input Frequency (MHz)

Amplitude (dBFS)

0 25 50 75 100 125

-120

-100

-80

-60

-40

-20

0

D045

Input Frequency (MHz)

Amplitude (dBFS)

0 25 50 75 100 125

-120

-100

-80

-60

-40

-20

0

D043

Input Frequency (MHz)

Amplitude (dBFS)

0 25 50 75 100 125

-120

-100

-80

-60

-40

-20

0

D044

ADS58J63

www.ti.com

SBAS717A –JUNE 2015–REVISED JUNE 2015

6.10 Typical Characteristics: Mode 2

Low pass or high pass decimation-by-2 filter selected as per input frequency. Typical values are at TA= 25°C, full temperature range is from T Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No

MAX

SNR = 74.1 dBFS, SFDR = 98 dBc, SFDR = 100 dBc (Non23) SNR = 73.8 dBFS, SFDR = 99 dBc, SFDR = 99 dBc (Non23)

FIN= 100 MHz , AIN= – 1 dBFS FIN= 150 MHz , AIN= – 1 dBFS

Figure 44. FFT for 100-MHz Input Signal Figure 45. FFT for 150-MHz Input Signal

FIN= 185 MHz , AIN= – 1 dBFS FIN= 230 MHz , AIN= – 1 dBFS

SNR = 73.2 dBFS, SFDR = 98 dBc, SFDR = 98 dBc (Non23) SNR = 72.4 dBFS, SFDR = 91 dBc, SFDR = 98 dBc (Non23)

Figure 46. FFT for 185-MHz Input Signal Figure 47. FFT for 230-MHz Input Signal

Product Folder Links: ADS58J63

Input Frequency (MHz)

Amplitude (dBFS)

-125 -75 -25 25 75 125

-120

-100

-80

-60

-40

-20

0

D049

Input Frequency (MHz)

Amplitude (dBFS)

-125 -75 -25 25 75 125

-120

-100

-80

-60

-40

-20

0

D047

Input Frequency (MHz)

Amplitude (dBFS)

-125 -75 -25 25 75 125

-120

-100

-80

-60

-40

-20

0

D048

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

www.ti.com

6.11 Typical Characteristics: Mode 0

Low-pass decimation-by-2 filter selected, Complex FFT plotted,mixer frequency 125 MHz. Typical values are at TA= 25°C, full temperature range is from T Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

= –40°C to T

MIN

= 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No

MAX

SNR = 69.5 dBFS, SFDR = 83 dBc, SFDR = 87 dBc (Non23) SNR = 68.1 dBFS, SFDR = 82 dBc, SFDR = 82 dBc (Non23)

FIN= 270 MHz , AIN= – 3 dBFS FIN= 370 MHz , AIN= – 3 dBFS

Figure 48. FFT for 270-MHz Input Signal Figure 49. FFT for 370-MHz Input Signal

FIN= 470 MHz , AIN= – 3 dBFS

SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (Non23)

Figure 50. FFT for 470-MHz Input Signal

Product Folder Links: ADS58J63

CLKINP/M

DAP/MINAP/M

PLL

x10/x20

DCP/M

DDP/M

14bit

ADC

INBP/M

INCP/M

14bit

ADC

INDP/M

DBP/M

JESD204B

SYNCbCD

SYSREFP/M

RESET

SCLK

SEN

SDIN

SDOUT

Configuration

Registers

Digital Block

Interleaving

Correction

14bit

ADC

14bit

ADC

Digital Block

Interleaving

Correction

Digital Block

Interleaving

Correction

Digital Block

Interleaving

Correction

SYNCbAB

TRIGAB

TRIGCD

TRDYCD

JESD204B

TRDYAB

Burst Mode

4x

K*FS/16

FS/8

2x

FS/4

2x

4x

K*FS/16

FS/8

2x

FS/4

2x

ADS58J63

www.ti.com

SBAS717A –JUNE 2015–REVISED JUNE 2015

7 Detailed Description

7.1 Overview

The ADS58J63 is a low power, wide bandwidth 14-bit 500 MSPS quad channel telecom receiver IC. It supports the JESD204B serial interface with data rates up to 10 Gbps supporting 1 lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Its digital block includes a 2x and 4x decimation low pass filter with FS/4 and k×FS/16 mixers to support a receive bandwidth up to 200 MHz and a output burst mode for use as DPD observation receiver.

The JESD204B interface reduces the number of interface lines allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used to serialize the 14bit data from each channel.

7.2 Functional Block Diagram

Product Folder Links: ADS58J63

INxP

INxM

1:1

0.1uF

1:1

25 

0.1uF

Device

Rin Cin

T2T1

25 

10 

25 

3.3 pF

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

www.ti.com

7.3 Feature Description

7.3.1 Analog Inputs

The ADS58J63 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50 Ω matching for RF applications. The buffer also helps to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +

0.475 V) and (VCM – 0.475 V), resulting in a 1.9-Vpp (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.

7.3.2 Recommended Input Circuitry

In order to achieve optimum AC performance the following circuitry is recommended at the analog inputs.

Figure 51. Analog Input Driving Circuit

Product Folder Links: ADS58J63

Filter

N

Filter

14-bit

Burst Mode

Mode

Selection

cos(2nf

mix1/fS

)

sin(2nf

mix1/fS

)

cos(2nf

mix2/fS

)

sin(2nf

mix2/fS

)

I data

Q data

CH x

IL E n g

i n e

N

2

Real data

Upscaled

Zero-

padded

data

14/9-bit Burst Mode data

0 2 4 5 6 7 8

To JESD

Encoder

500MSPS data, x(n)

ADS58J63

www.ti.com

SBAS717A –JUNE 2015–REVISED JUNE 2015

7.4 Device Functional Modes

7.4.1 Digital Features

The ADS58J63 supports decimation by 2 and 4 and burst mode output. The 4 channels can be configured as pairs (A and B and C and D) to either burst or decimation mode (must be same decimation mode for all 4 channels).

Table 1. Overview of Operating Modes

OPERATING DIGITAL BANDWIDTH BANDWIDTH OUTPUT

MODE MIXER AT 491Msps AT 368Msps FORMAT

DESCRIPTION DECIMATION OUTPUT

0 ±FS/4 2 200 MHz 150 MHz Complex 250 Msps

2 – 2 100 MHz 75 MHz Real 250 Msps

4 N×Fs/16 2 100 MHz 75 MHz Real 250 Msps

5 N×Fs/16 2 200 MHz 150 MHz Complex 250 Msps

Decimation

6 N×Fs/16 4 100 MHz 75 MHz Complex 125 Msps

7 N×Fs/16 2 100 MHz 75 MHz Real 500 Msps

8 Burst Mode – – 245.76 MHz 184.32 MHz Real 500 Msps

Figure 52 shows signal processing in Digital Down-Conversion (DDC) Block in ADS58J63.

MAX

RATE

Figure 52. Digital Down-Conversion (DDC) Block

Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.

Table 2. Features of DDC Block in Different Modes

Mode fmix1 Filter and Decimation fmix 2 Output

0 fS/4 LPF cut off freq at fS/4, decimation by 2 not used I, Q data at 250 MSPS each is given out 2 not used LPF or HPF cut off at fS/4, decimation by 2 not used Straight 250 MSPS data is given out 4 k fS/16 LPF cutoff at fS/8, decimation by 2 fS/8 Real data at 250 MSPS is given out 5 k fS/16 LPF cutoff at fS/8, decimation by 2 not used I, Q data at 250 MSPS each is given out 6 k fS/16 LPF cutoff at fS/8, decimation by 4 not used I, Q data at 125 MSPS each is given out

7 k fS/16 LPF cutoff at fS8, decimation by 2 fS/8 8 not used not used not used Straight 500 MSPS Burst mode data is given out

Real data is up-scaled, zero-padded and given out

at 500 MSPS

Product Folder Links: ADS58J63

Frequency Response

Magnitude (dB)

0 0.1 0.2 0.3 0.4 0.5

-120

-100

-80

-60

-40

-20

0

20

D052

Frequency Response

Magnitude (dB)

0 0.05 0.1 0.15 0.2 0.25

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

D053

14-bit

ADC

2x

IQ: 250 Msps

FS/2

FS/4

± Fs/4

500 Msps IQ: 500 Msps

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

www.ti.com

7.4.2 Mode 0 – Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±Fs/4 complex digital mixer preceding the digital filter – so the IQ passband is ± ~110 MHz (3 dB) centered at Fs/4. Mixing with +FS/4 inverts the spectrum. The stop band attenuation is approximately 90 dB and the passband flatness is ±0.1 dB. Figure 53 shows mixing operation in DDC Mode 0.

Figure 53. Mixing in Mode 0

Table 3. Filter Specification Details – Mode 0

CORNERS LOW PASS

–0.1 dB 0.204 × Fs –0.5 dB 0.211 × Fs –1 dB 0.216 × Fs –3 dB 0.226 × Fs

Figure 54. Frequency Response of Filter in Mode 0 Figure 55. Zoomed view of Frequency Response

Product Folder Links: ADS58J63

Frequency Response

Magnitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-120

-100

-80

-60

-40

-20

0

20

D056

Frequency Response

Magnitude (dB)

0 0.05 0.1 0.15 0.2 0.25

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

D057

14-bit

ADC

2x

250 Msps

FS/2

FS/4

500 Msps

ADS58J63

www.ti.com

SBAS717A –JUNE 2015–REVISED JUNE 2015

7.4.3 Mode 2 – Decimation by 2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs. The passband is ~110 MHz (3 dB). Figure 56 shows filtering operation in DDC Mode 2.

Figure 56. Filtering in Mode 2

Table 4. Filter Specification Details – Mode 2

CORNERS LOW PASS HIGH PASS

–0.1 dB 0.204 × Fs 0.296 × Fs –0.5 dB 0.211 × Fs 0.290 × Fs –1 dB 0.216 × Fs 0.284 × Fs –3 dB 0.226 × Fs 0.274 × Fs

Figure 57. Frequency Response for Decimate-by-2 Low Figure 58. Zoomed View of Frequency Response

Pass and High Pass Filter (in Mode 2)

Product Folder Links: ADS58J63

Frequency Response

Magnitude (dB)

0 0.05 0.1 0.15 0.2 0.25

-120

-100

-80

-60

-40

-20

0

20

D050

Frequency Response

Magnitude (dB)

0 0.05 0.1 0.15 0.2 0.25

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

D051

14-bit

ADC

2x

IQ: 250 Msps

FS/2 FS/4

N*Fs/16

500 Msps IQ: 500 Msps

FS/4 FS/8

Fs/8

Real: 250 Msps

FS/4

FS/8

Example:

N= -4

0 Pad

Real: 500 Msps

FS/4

FS/8

FS/2

2nd Image

0

ADS58J63

SBAS717A –JUNE 2015–REVISED JUNE 2015

www.ti.com

7.4.4 Mode 4/7 – Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7) preceding the decimation by 2 digital filter also with an IQ passband of ± ~55 MHz (3 dB) centered at N×Fs/16. A positive value for N inverts the spectrum. In addition a Fs/8 complex digital mixer is added after the decimation filter transforming the output back to real format while centering the output spectrum within the Nyquist zone.

In addition the ADS58J63 supports a 0-pad feature where a sample with value = 0 gets added after each sample. In that way the output data rate gets interpolated to 500 Msps (real) with a 2ndimage inverted at Fs/2Fin.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for out of band aliases. The passband flatness is ±0.1 dB.

Figure 60. Frequency Response for Decimate-by-2 Low- Figure 61. Zoomed View of Frequency Response

Pass Filter (in Mode 4 and Mode 7)

Figure 59. Mixing and Filtering in Mode 4/7

Table 5. Filter Specification Details – Mode 4/7

CORNERS LOW PASS

–0.1 dB 0.102 × Fs –0.5 dB 0.105 × Fs –1 dB 0.108 × Fs –3 dB 0.113 × Fs

Product Folder Links: ADS58J63

Texas Instruments ADS58J63 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features 3 Description

2 Applications

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 AC Performance

6.7 Digital Characteristics

6.8 Timing Characteristics

6.9 Typical Characteristics: 14-Bit Burst Mode

6.10 Typical Characteristics: Mode 2

6.11 Typical Characteristics: Mode 0

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Analog Inputs

7.3.2 Recommended Input Circuitry

7.4 Device Functional Modes

7.4.1 Digital Features

7.4.2 Mode 0 – Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

7.4.3 Mode 2 – Decimation by 2 for up to 110 MHz of Real Bandwidth

7.4.4 Mode 4/7 – Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth