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ADS5525
User Manual
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Texas Instruments ADS5525, ADS5527, ADS5545, ADS5546, ADS5547 User Manual

ADS5525/27/45/46/47 EVM User Guide
User's Guide
November 2006
SLWU028B
2 SLWU028B – January 2006 – Revised November 2006
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Contents
1.1 EVM Basic Functions ............................................................................................ 5
2 EVM Quick Start Guide ................................................................................................ 6
2.1 EVM LVDS Output Mode Quick Start (Default) .............................................................. 6
2.2 EVM CMOS Output Mode Quick Start ........................................................................ 6
3.1 Schematic Diagram .............................................................................................. 7
3.2 Circuit Function ................................................................................................... 7
4 Expansion Options .................................................................................................... 13
4.1 Custom FPGA Code ........................................................................................... 13
4.2 Expansion Slot .................................................................................................. 13
4.3 Optional USB SPI Interface ................................................................................... 13
5 Physical Description .................................................................................................. 14
5.1 PCB Layout ...................................................................................................... 14
5.2 Bill of Materials .................................................................................................. 20
5.3 PCB Schematics ................................................................................................ 25
SLWU028B – January 2006 – Revised November 2006 Table of Contents 3
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List of Figures
1 ADS5547 SNR Performance vs Decoupling ............................................................................. 8
2 THS4509 + ADS5545 EVM Performance ................................................................................ 9
3 Eye Diagram of Data on Header J4. ..................................................................................... 11
4 Top Layer .................................................................................................................... 14
5 Layer 2, Ground Plane .................................................................................................... 15
6 Layer 3, Power Plane #1 .................................................................................................. 16
7 Layer 4, Power Plane #2 .................................................................................................. 17
8 Layer 5, Ground Plane .................................................................................................... 18
9 Layer 6, Bottom Layer ..................................................................................................... 19
List of Tables
1 DIP Switch SW1 ............................................................................................................. 7
2 EVM Power Options ......................................................................................................... 8
3 Output Connector J4 ....................................................................................................... 10
4 Test Points .................................................................................................................. 12
5 Bill of Materials ............................................................................................................. 21
4 List of Figures SLWU028B – January 2006 – Revised November 2006
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1 Overview

1.1 EVM Basic Functions

User's Guide
SLWU028B – January 2006 – Revised November 2006
This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device der many conditions.
Analog input to the ADC is provided via external SMA connectors. The user supplies a single-ended input, which is converted into a differential signal. One input path uses a differential amplifier, while the other input is transformer-coupled.
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input is converted into a differential signal at the input of the device.
Digital output from the EVM is via a 40-pin connector. Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC
analog and digital supplies, the FPGA supply, and the differential amplifier supply.
CAUTION
Exceeding the maximum input voltages can damage EVM components. Undervoltage may cause improper operation of some or all of the EVM components.
Xilinx, Spartan, WebPACK are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
SLWU028B – January 2006 – Revised November 2006 5
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EVM Quick Start Guide

2 EVM Quick Start Guide

The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode.
Note: Follow the steps in the listed order; not doing so could result in improper operation.

2.1 EVM LVDS Output Mode Quick Start (Default)

1. Ensure a jumper is installed between pins 1 and 2 on JP2.
2. Ensure DIP switch SW1, switch 2 is set to LVDS.
3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.
4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding returns connected to J9 and J16.
5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.
6. Provide a filtered, low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.
7. Provide a filtered, sinusoidal analog input to J3.
8. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.

2.2 EVM CMOS Output Mode Quick Start

1. Ensure a jumper is installed between pins 2 and 3 on JP2.
2. Ensure DIP switch SW1, switch 2 is set to CMOS.
3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.
4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding returns connected to J9 and J16.
5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.
6. Provide a low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.
7. Provide a filtered sinusoidal analog input to J3.
8. Briefly depress S1, which resets the EVM.
9. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.
6 SLWU028B – January 2006 – Revised November 2006
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3 Circuit Description

3.1 Schematic Diagram

The schematic diagram for the EVM is in Section 5.3 of this document.

3.2 Circuit Function

The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics.

3.2.1 Configuration Options

The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is configured for parallel-mode operation. Table 1 describes the functionality of the DIP switches.
Note: When the device is configured for serial-mode operation (SW1, switch 8), the DIP settings
SW1 SWITCH
NUMBER
Circuit Description
on SW1, switch 1 through SW1, switch 7 are ignored.
Table 1. DIP Switch SW1
OFF ON DESCRIPTION
1 2s complement Offset binary Determines device output format 2 LVDS CMOS Determines device output mode 3 Reserved Reserved Reserved 4 Internal reference External reference When set to External Reference, ADC uses common-mode
voltage on TP1. 5 Edge = 1 Edge = 2 Allows for output edge programmability 6 Edge = 3 Edge = 4 Allows for output edge programmability 7 Normal Power down Allows for power down 8 Serial Parallel Determines mode for register interface
By switching SW1, switch 8 to OFF, the ADC operates in serial mode, using its programmed register contents. A complete register map can be found in the device datasheet. Three pins on header J6 have been reserved for programming the device while it operates in serial mode. To program the device registers using header J6, place SCLK on pin 21, SDATA on pin 23, and SEN on pin 25. A pattern generator can be used to generate the patterns needed for programming. Alternatively, TI provides an optional USB daughtercard that plugs into the expansion slot of the EVM. The USB daughtercard allows ADC register control via a software package loaded onto the PC.

3.2.2 Power

Power is supplied to the EVM via banana jack sockets. The EVM offers the capability to supply analog and digital 3.3 V independently to the ADC. Table 2 offers a snapshot of the power-supply options. All supply connections are required for default operation, except J12, J10, J13, and J20.
The EVM provides local decoupling for the ADC; however, the ADC features internal decoupling, and in many cases minimal external decoupling can be used without loss in performance. Users are encouraged to experiment to find the optimal amount of external decoupling required for their application. Figure 1 shows the ADS5547 LVDS-mode performance with all of the decoupling capacitors installed and the performance with C4, C5, C6, C7, C8, C9, and C10 removed. By default, the EVM comes with all of the decoupling capacitors installed.
SLWU028B – January 2006 – Revised November 2006 7
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fIN − Input Frequency − MHz
SNR − Signal-to-Noise Ratio − dBFS
G001
9.97 19.94 30.13 40.33 50.13 60.13 69.59 79.87 89.75 100.33 130.13 170.13
68
69
70
71
72
73
74
1 Decoupling Cap
Baseline-All Decoupling Caps
Circuit Description
Table 2. EVM Power Options
BANANA JACK NAME VOLTAGE DESCRIPTION
J9 Device AGND GND J10 AGND GND J11 Device AVDD 3.3 Device analog supply J12 Amplifier negative –5 THS4509 Vs– supply
J13 Amplifier positive rail 5 THS4509 Vs+ supply J14 Auxiliary power 5 Supplies power to all peripheral circuitry including the FPGA
J15 Device DVDD 3.3 Device internal digital output supply J16 DGND GND J17 DGND GND J20 If TP11, TP12, and TP13 are tied low, the TPS75003 is
rail
and PROM. Voltages rails are created by using TI's TPS75003 voltage regulator.
disabled. In this case, one can supply 3.3 V to pin 1, 1.2 V to pin 2, and 2.2 V to pin 3 of J20 while connecting the ground to J17.
Figure 1. ADS5547 SNR Performance vs Decoupling

3.2.3 Analog Inputs

The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier inputs from a single-ended source. The inputs are provided via SMA connector J3 for transformer-coupled input or SMA connector J1 for differential amplifier input. To set up for one of these options, the EVM must be configured as follows:
1. For a 1:1 transformer-coupled input to the ADC, a single-ended source is connected to J3. Confirm that SJP4 has pins 2 and 3 shorted, and that SJP5 has pins 2 and 3 shorted. The transformer used, the Mini-Circuits TC4-1W, forms an inherent band-pass filter with a pass band from 3 MHz to 800 MHz. This is the default configuration for the EVM.
2. One can use a TI THS4509 amplifier to drive the ADC by applying an input to J1. Reconfigure SJP4 and SJP5 such that both have pins 1 and 2 shorted. A 5-VDC supply must be connected to the board to provide power to U3 for this configuration.
8 SLWU028B – January 2006 – Revised November 2006
The THS4509 amplifier path converts a single-ended signal presented on J1 into a differential signal.
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0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
f − Frequency − MHz
Amplitude − dBFS
G002
1
−135
−120
10
−130
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
2
3
4
5
x
Circuit Description
The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using the THS4509 path.

3.2.4 Clock Input

3.2.5 Digital Outputs

SLWU028B – January 2006 – Revised November 2006 9
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Figure 2. THS4509 + ADS5545 EVM Performance
A single-ended, harmonically filtered, low-phase-noise, 1.5-Vrms sinusoidal input should be applied to J7. The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 and SJP2 must have pins 1 and 2 shorted.
In the board default configuration, the transformer provides single-ended to differential conversion. The transformer has an impedance ratio of 4.
For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-V parallel CMOS data on header J4, independent of the ADC operational mode. The Xilinx™Spartan™-3E FPGA provides the necessary translation, and it configures itself using one of two different logic files stored in the PROM, based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 and is a standard 40-pin header on a 100-mil grid, which allows easy connection to a logic analyzer. The connector pinout is listed in Table 3 . For quick setup, the eye diagram is shown in Figure 3 . No setup or hold-time adjustments must be made to the logic analyzer if using the rising edge of the output clock to latch in the data.
Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. For
the ADC output timing, see the respective device data sheet.
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Circuit Description
Table 3. Output Connector J4
J4 PIN ADS5525/27 DESCRIPTION ADS5545/46/47 DESCRIPTION
1 CLK CLK 2 GND GND 3 NC NC 4 GND GND 5 Reserved Reserved 6 GND GND 7 Reserved Reserved 8 GND GND
9 NC Data bit 0 (LSB) 10 GND GND 11 NC Data bit 1 12 GND GND 13 Data bit 0 (LSB) Data bit 2 14 GND GND 15 Data bit 1 Data bit 3 16 GND GND 17 Data bit 2 Data bit 4 18 GND GND 19 Data bit 3 Data bit 5 20 GND GND 21 Data bit 4 Data bit 6 22 GND GND 23 Data bit 5 Data bit 7 24 GND GND 25 Data bit 6 Data bit 8 26 GND GND 27 Data bit 7 Data bit 9 28 GND GND 29 Data bit 8 Data bit 10 30 GND GND 31 Data bit 9 Data bit 11 32 GND GND 33 Data bit 10 Data bit 12 34 GND GND 35 Data bit 11 (MSB) Data bit 13 (MSB) 36 GND GND 37 NC NC 38 GND GND 39 NC NC 40 GND GND
10 SLWU028B – January 2006 – Revised November 2006
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C001
Circuit Description
Figure 3. Eye Diagram of Data on Header J4.

3.2.6 Test Points

For added EVM visibility and control, several test points are provided. Table 4 summarizes the test points available.
SLWU028B – January 2006 – Revised November 2006 11
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