TEXAS INSTRUMENTS ADS5521 Technical data

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12−Bit

Pipeline

ADC Core

S&H

CLK+ CLK

−

CLKOUT

VIN+

−

Digital

Error

Correction

Timing Circuitry

Internal

Reference

Control Logic

Serial Programming Register

Output

Control

. . .

D11

OVR DFS

ADS5521

GND

SEN SDATA

SCLK

DRV

Analog-To-Digital Converter

ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

12-Bit, 105MSPS

FEATURES

• 12-Bit Resolution

• 105MSPS Sample Rate

• High SNR: 70dBFS at 100MHz f

• High SFDR: 86dBc at 100MHz f

• 2.3V

• Internal Voltage Reference

• 3.3V Single-Supply Voltage

• Analog Power Dissipation: 571mW

– Output Buffer Power: 165mW

• Pin-Compatible with:

ADS5500 (14-Bit, 125MSPS) ADS5541 (14-Bit, 105MSPS) ADS5542 (14-Bit, 80MSPS) ADS5520 (12-Bit, 125MSPS) ADS5522 (12-Bit, 80MSPS)

Differential Input Voltage

• TQFP-64 PowerPAD™ Package

• Recommended Op Amps:

THS3201, THS3202, THS4503, THS4509, THS9001, OPA695, OPA847

APPLICATIONS

• Wireless Communication

– Communication Receivers – Base Station Infrastructure

• Test and Measurement Instrumentation

• Single and Multichannel Digital Receivers

• Communication Instrumentation

– Radar – Infrared

• Video and Imaging

• Medical Equipment

• Military Equipment

DESCRIPTION

The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5521 has excellent analog power dissipation of 571mW and output buffer power dissipation of 165mW from a 3.3V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic.

The ADS5521 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541, ADS5542, ADS5520, and ADS5522. This device is specified over the full temperature range of –40°C to +85°C.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

ADS5521 PAP –40C to +85C ADS5521I

HTQFP-64

PowerPAD

(2)

ADS5521IPAP Tray, 160

ADS5521IPAPR Tape and Reel, 1000

(1) For the most current package and ordering information, see the Package Option Addendum, or see the TI web site at www.ti.com . (2) Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max). θJA= 21.47 ° C/W and θJC= 2.99 ° C/W, when used with 2 oz. copper trace

and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

to A

Supply Voltage

Analog input to A Logic input to DR Digital data output to DR

GND GND GND

GND

, DRV

GND

to DR

GND

Operating temperature range –40 to +85 °C Junction temperature +105 °C Storage temperature range –65 to +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

to DR

(1)

ADS5521 UNIT

GND

–0.3 to +3.7 V

±0.1 V

–0.3 to minimum (AVDD + 0.3, 3.6) V

–0.3 to DRV –0.3 to DRV

DD DD

V V

RECOMMENDED OPERATING CONDITIONS

PARAMETER MIN TYP MAX UNIT Supplies

Analog supply voltage, AV Output driver supply voltage, DRV

Analog input

Differential input range 2.3 V Input common-mode voltage, V

Digital Output

Maximum output load 10 pF Clock Input

ADCLK input sample rate (sine wave) 1/t

Clock amplitude, sine wave, differential Clock duty cycle Open free-air temperature range –40 +85 °C

(3)

(1)

(2)

DLL ON 60 105 MSPS DLL OFF 2 80 MSPS

(1) Input common-mode should be connected to CM. (2) See Figure 48 for more information. (3) See Figure 47 for more information.

3.0 3.3 3.6 V

1.45 1.55 1.65 V

1 3 V

50 %

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ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS

Typical values given at TA= +25 ° C, min and max specified over the full temperature range of –40 ° C to +85 ° C, AV DRV

= 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3V

differential clock, and –1dBFS differential

input, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

Resolution 12 Bits Analog Inputs

Differential input range 2.3 V Differential input capacitance See Figure 39 4 pF Analog input common-mode current

(per input) Analog input bandwidth Source impedance = 50 Ω 750 MHz

Voltage overload recovery time 4

Internal Reference Voltages

Reference bottom voltage, V Reference top voltage, V

REFM

REFP

Reference error –4 ±0.9 +4 % Common-mode voltage output, V

1.50 1.55 1.60 V

Dynamic DC Characteristics and Accuracy

No missing codes Tested Differential nonlinearity error, DNL fIN= 55MHz –0.5 ±0.25 +0.5 LSB Integral nonlinearity error, INL fIN= 55MHz –1.5 ±0.55 +1.5 LSB Offset error ±1.5 mV Offset temperature coefficient 0.02 %/°C

DC power-supply rejection ratio, DC PSRR 0.25 mV/V

∆ offset error/ ∆ AV AV

= 3.6V

from AV

= 3.0V to

Gain error ±0.3 %FS Gain temperature coefficient –0.02 ∆ %/°C

Dynamic AC Characteristics

fIN= 10MHz 71 dBFS

fIN= 55MHz

+25°C to +85°C 68.0 70.5 dBFS Full temp range 66.8 69.0 dBFS

Signal-to-noise ratio. SNR fIN= 70MHz 70.3 dBFS

fIN= 100MHz 70.0 dBFS fIN= 150MHz 69.3 dBFS fIN= 220MHz 67.8 dBFS

RMS idle channel noise Input tied to common-mode 0.32 LSB

fIN= 10MHz 83.0 dBc

fIN= 55MHz

Room temp 78.0 86.0 dBc Full temp range 76.0 85.0 dBc

Spurious-free dynamic range, SFDR fIN= 70MHz 81.0 dBc

fIN= 100MHz 86.0 dBc fIN= 150MHz 75.0 dBc fIN= 220MHz 72.0 dBc

250 µA

1.0 V

2.15 V

Clock

cycles

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ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

Typical values given at TA= +25 ° C, min and max specified over the full temperature range of –40 ° C to +85 ° C, AV DRV input, unless otherwise noted.

= 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3V

PARAMETER CONDITIONS MIN TYP MAX UNIT

fIN= 10MHz 90.0 dBc

fIN= 55MHz

Second-harmonic, HD2 fIN= 70MHz 81.0 dBc

fIN= 100MHz 88.0 dBc fIN= 150MHz 75.0 dBc fIN= 220MHz 72.0 dBc fIN= 10MHz 83.0 dBc

fIN= 55MHz

Third-harmonic, HD3 fIN= 70MHz 87.0 dBc

fIN= 100MHz 86.0 dBc fIN= 150MHz 80.0 dBc fIN= 220MHz 78.0 dBc

Worst-harmonic/spur (other than HD2 and HD3)

Signal-to-noise + distortion, SINAD fIN= 70MHz 69.6 dBFS

Total harmonic distortion, THD fIN= 70MHz 78.0 dBc

Effective number of bits, ENOB fIN= 55MHz 11.3 Bits

Two-tone intermodulation distortion, IMD f = 50.1MHz, 55.1MHz (-7dBFS each tone) 96.6 dBFS

fIN= 55MHz 87.0 dBc fIN= 10MHz 70.7 dBFS

fIN= 55MHz

fIN= 100MHz 69.3 dBFS fIN= 150MHz 68.2 dBFS fIN= 220MHz 65.8 dBFS fIN= 10MHz 79.0 dBc

fIN= 55MHz

fIN= 100MHz 84.0 dBc fIN= 150MHz 74.0 dBc fIN= 220MHz 70.3 dBc

f = 10.1MHz, 15.1MHz (-7dBFS each tone) 94.6 dBFS

f = 150.1MHz, 155.1MHz (-7dBFS each tone) 84.7 dBFS

Room temp 78.0 86.0 dBc Full temp range 76.0 85.0 dBc

Room temp 78.0 88.0 dBc Full temp range 76.0 87.0 dBc

Room temp 67.0 70.0 dBFS Full temp range 65.8 68.5 dBFS

Room temp 76.0 83.0 dBc Full temp range 74.0 82.0 dBc

differential clock, and –1dBFS differential

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ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

Typical values given at TA= +25 ° C, min and max specified over the full temperature range of –40 ° C to +85 ° C, AV DRV

= 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3V

differential clock, and –1dBFS differential

input, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

Power Supply

Total supply current, ICC fIN= 55MHz 223 250 mA Analog supply current, IAVDD fIN= 55MHz 173 185 mA Output buffer supply current, IDRVDD fIN= 55MHz 50 65 mA

Analog only 571 611 mW

Power dissipation

Output buffer power with 10pF load on digital output to ground

165 215 mW

Standby power With Clocks running 180 250 mW

DIGITAL CHARACTERISTICS

Valid over full temperature range of T otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

Digital Inputs

High-level input voltage, V Low-level input voltage, V High-level input current, I Low-level input current, I Input current for RESET –20 µA Input capacitance 4 pF

Digital Outputs

Low-level output voltage, V High-level output voltage, V Output capacitance 3 pF

= –40°C to T

MIN

MAX

= +85°C, AV

= DRV

= 3.3V, and 3V

differential clock, unless

2.4 V

= 10pF 0.3 0.4 V

LOAD

= 10pF 2.4 3.0 V

LOAD

0.8 V 10 µA 10 µA

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NOTE: It isrecommended thattheloading at CLKOUTand all data lines areaccurately matched to ensure thattheabove timing

matchescloselywith the specifiedvalues.

Sample

Analog

Input

Signal

Input Clock

Data Invalid

Output Clock

Data Out

(D0 to D11)

N−17 N−16 N−15 N−14 N−13 N−3 N−2 N−1 N

16.5 Clock Cycles

N + 2

N + 3

N + 4

N + 14

HOLD

START

END

SETUP

PDI

= t

START

+ t

SETUP

N + 15

N + 16

N + 17

ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

TIMING CHARACTERISTICS

Typical values given at TA= +25 ° C, min and max specified over the full temperature range of –40 ° C to +85 ° C, AV DRV otherwise noted.

(1) Timing parameters are ensured by design and characterization, and not tested in production. (2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies. (3) Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW. (4) Refer to the Output Information section for details on using the input clock for data capture. (5) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect

= 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, 3V

PARAMETER DESCRIPTION MIN TYP MAX UNIT

Switching Specification

Aperture delay, t

Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs Data setup time, t Data hold time, t

Input clock to output data valid start, Input clock rising edge to data valid start delay 1.9 2.8 ns

(4)

START

Input clock to output data valid end, Input clock rising edge to data valid end delay 5.8 7.3 ns

(4)

END

Output clock jitter, t Output clock rise time, t Output clock fall time, t Data rise time, t

Data fall time, t

SETUP

HOLD

JIT

RISE

FALL

Output enable(OE) to data output delay Time required for outputs to have stable timings 1000 Clock

Wakeup time Time to valid data after coming out of software 1000 Clock

to input clock.

(1) (2)

differential clock, and –1dBFS differential input, unless

Input CLK falling edge to data sampling point 1 ns

Data valid 50% of CLKOUT rising edge to data becoming 2.2 2.5 ns

invalid

(3)

to 50% of CLKOUT rising edge 2.2 2.8 ns

(3)

Uncertainty in CLKOUT rising edge, peak-to-peak 175 250 ps Rise time of CLKOUT from 20% to 80% of DRV Fall time of CLKOUT from 80% to 20% of DRV

2.0 2.2 ns

1.7 1.8 ns

Data rise time measured from 20% to 80% of 4.4 5.1 ns DRV

Data fall time measured from 80% to 20% of 3.3 3.8 ns DRV

with regard to input clock

(5)

after OE is activated cycles

power down, after stopping and restarting the input cycles clock

Figure 1. Timing Diagram

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≥

10ms

≥2µ

s SEN Active

Power Supply (AVDD, DRVDD)

RESET (Pin 35)

ADDRESS

SDATA

MSB

DATA

A2 A1 A0 D11 D10 D9 D0

SBAS309A – MAY 2004 – REVISED APRIL 2005

RESET TIMING CHARACTERISTICS

Typical values given at TA= +25 ° C, min and max specified over the full temperature range of –40 ° C to +85 ° C, AV DRV

= 3.3V, and 3V

PARAMETER DESCRIPTION MIN TYP MAX UNIT

Switching Specification

Power-on delay, t

Reset pulse width, t Register write delay, t

Power-up time Delay from power-up of AV

differential clock, unless otherwise noted.

Delay from power-on of AVDD and 10 ms DRVDD to RESET pulse active

Pulse width of active RESET signal 2 µs Delay from RESET disable to SEN 2 µs

active

DRV

to output stable

and 40 ms

ADS5521

Figure 2. Reset Timing Diagram

SERIAL PROGRAMMING INTERFACE CHARACTERISTICS

The ADS5521 has a three-wire serial interface. The • Data is loaded at every 16th SCLK falling edge ADS5521 latches serial data SDATA on the falling while SEN is low. edge of serial clock SCLK when SEN is active.

• Serial shift of bits is enabled when SEN is low. bits, the excess bits are ignored. SCLK shifts serial data at the falling edge.

• Minimum width of data stream for a valid loading within a single active SEN pulse. is 16 clocks

Figure 3. DATA Communication is 2-Byte, MSB First

• In case the word length exceeds a multiple of 16

• Data can be loaded in multiples of 16-bit words

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SLOADS

WSCLK

SCLK

16 x M

MSB LSB LSBMSB

SLOADH

SCLK

SEN

SDATA

DFS



 AV

 AVDD V

DFS



 AV

 AVDD V

DFS



 AV

DFS



10 12

 AV

ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

Figure 4. Serial Programming Interface Timing Diagram

Table 1. Serial Programming Interface TIming Characteristics

SYMBOL PARAMETER MIN

SCLK

WSCLK

SLOADS

SLOADH

(1) Typ, min, and max values are characterized, but not production tested.

SCLK period 50 ns

SCLK duty cycle 25 50 75 %

SEN to SCLK setup time 8 ns

SCLK to SEN hold time 6 ns

Data setup time 8 ns

Data hold time 6 ns

(1)

TYP

(1)

MAX

UNIT

Table 2. Serial Register Table

A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION

1 1 0 1 0 0 0 0 0 0 0 0 0 0 DLL 0 DLL OFF = 0: Internal DLL is on; recommended for 60MSPS

OFF to 105MSPS clock speeds.

1 1 1 0 0 TP<1> TP<0> 0 0 0 0 0 0 0 0 0 TP<1:0> - Test modes for output data capture

1 1 1 1 PDN 0 0 0 0 0 0 0 0 0 0 0 PDN = 0: Normal mode of operation

(1)

DLL OFF = 1: Internal DLL is off; recommended for 2MSPS to 80MSPS clock speeds.

TP<1:0> = 00: Normal mode of operation TP<1:0> = 01: All outputs forced to 0 TP<1:0> = 10: All outputs forced to 1 TP<1:0> = 11: Each output bit toggles between 0 and 1.

There is no ensured relationship between the bits.

PDN = 1: Device is put in power-down (low-current) mode.

(1) All register contents default to zero on reset. (2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode

outputs will be the binary two's complement equivalent of these patterns.

Table 3. Data Format Select (DFS) Table

DFS-PIN VOLTAGE (V

) DATA FORMAT CLOCK OUTPUT POLARITY

DFS

Straight Binary Data valid on rising edge

Two's Complement Data valid on rising edge

Straight Binary Data valid on falling edge

(2)

Two's Complement Data valid on falling edge

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

GND

D1 D0 (LSB) NC NC CLKOUT DR

GND

OE DFS AV

GND

RESET AV

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

GND

SCLK

SDATA

SEN

GND

CLKP

CLKM

GND

OVR

D11 (MSB)

D10

GND

DRV

GND

DRV

GND

INP

INM

GND

REFP

REFM

IREF

GND

64 63 62 61 60 59 58 57 56 55 54

17 18 19 20 21 22 23 24 25 26 27

53 52 51 50 49

28 29 30 31 32

PowerPAD

(Connected to Analog Ground)

ADS5521

SBAS309A – MAY 2004 – REVISED APRIL 2005

PIN CONFIGURATION

PAP PACKAGE

HTQFP-64

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