This user's guide describes the function and use of the ADS54J20 evaluation module. Included in this
document are a quick-start guide, instructions for optimizing evaluation results, software description,
alternate hardware configurations, and jumper, connector, and LED descriptions.
The ADS54J20EVM is an evaluation module (EVM) designed to evaluate the ADS54J20 high-speed,
JESD204B interface ADCs. The EVM includes an onboard clocking solution (LMK04828), transformer
coupled inputs, full power solution, and easy-to-use software GUI and USB interface.
The following features apply to this EVM:
•Transformer-coupled signal input network allowing a single-ended signal source from 0.4 MHz to 800
MHz
•LMK04828 system clock generator that generates field-programmable gate array (FPGA) reference
clocks for the high-speed serial interface and may be used to generate the ADC sampling clock
(default setting)
•Transformer-coupled clock input network to test the ADC performance with a very low-noise clock
source
•High-speed serial data output over a standard FPGA Mezzanine Card (FMC) interface connector
The ADS54J20EVM is designed to work seamlessly with the TSW14J56EVM, Texas Instruments’
JESD204B data capture/ pattern generator card, through the High Speed Data Converter Pro (HSDC Pro)
software tool for high-speed data converter evaluation. The ADS54J20EVM was also designed to work
with many of the development kits from leading FPGA vendors that contain an FMC connector.
www.ti.com
1.1Required Hardware
The following equipment is included in the EVM evaluation kit:
•ADS54J20 Evaluation Board (EVM)
•Power supply cable
•Mini-USB cable
The following list of equipment are items that are not included in the EVM evaluation kit but are items
required for evaluation of this product in order to achieve the best performance:
•TSW14J56EVM Data Capture Board, two +5-V power supplies and Mini-USB cable
•Computer running Microsoft®Windows®8, Windows 7, or Windows XP
This section guides the user through the EVM test procedure to obtain a valid data capture from the
ADS54J20EVM using the TSW14J56EVM capture card. This should be the starting point for all
evaluations.
2.1Software Installation
The proper software must be installed before beginning evaluation. See Section 1.2 for a list of the
required software. The References section of this document contains links to find the software on the TI
website.
Important: The software must be installed before connecting the ADS54J20EVM and TSW14J56 to the
computer for the first time.
2.1.1ADS54Jxx EVM GUI Installation
The ADS54Jxx EVM GUI is used to control the ADS54J20EVM. It must be used to properly configure the
devices on the EVM.
1. Download the ADS54Jxx EVM GUI from the TI website. The References section of this document
contains links to find the software on the TI website.
2. Extract the files from the zip file.
3. Run setup.exe and follow the installation prompts.
2.1.2High Speed Data Converter Pro GUI Installation
High Speed Data Converter Pro (HSDC Pro) is used to control the TSW14J56EVM and analyze the
captured data. Please see the HSDC Pro user’s guide (SLWU087) for more information.
1. Download HSDC Pro from the TI website. The References section of this document contains the link to
find the software on the TI website.
2. Extract the files from the zip file.
3. Run setup.exe and follow the installation prompts.
A typical test setup using the ADS54J20EVM and TSW14J56EVM is shown in Figure 2. This is the test
setup used for the quick start procedure. The rest of this section describes the hardware setup steps.
Quick Start Guide
2.2.1TSW14J56EVM Setup
Figure 2. Quick Start Test Setup
First, setup the TSW14J56EVM using the following steps:
1. Connect the ADS54J20EVM to the TSW14J56EVM using the FMC connectors.
2. Connect the included power supply cable to connector J11 (+5V IN) and the other end to a +5 VDC
±0.3 VDC 3-A power supply.
3. Connect the included mini-USB cable to the USB connector (J9).
4. turn on the power supply. Flip the power switch (SW6) to the ON position. The board should draw
around 0.5 A after power up. This will increase to around 1.7 A when loaded with firmware.
1. Connect the included 5-V power supply cable to connector J9 of the EVM. Connect the red wire to +5
VDC ±0.1 VDC of a power supply rated for at least 3 A. Connect the black wire to GND of the power
supply.
2. Connect the included mini-USB cable to the USB connector J8.
3. Turn on the power supply. The power draw should be around 0.66 A. When the board is configured, it
will draw approximately 1.35 A.
4. Set the analog input signal generator for 170 MHz, and about +15 dBm of power.
5. Place a narrow pass-band band-pass filter at the output of the analog signal generator to remove noise
and harmonics from the signal generator.
6. Connect the analog input signal generator to the EVM though SMA connector AINP (J2).
2.3Software Setup Procedure
The software can be opened and configured once the hardware is properly setup.
2.3.1ADS54J20 GUI Configuration
1. Open the ADS54Jxx EVM GUI by going to Start Menu → All Programs → Texas Instruments ADCs →
ADS54Jxx EVM GUI.
2. Verify that the green USB Status indicator is lit in the top right corner of the GUI. If it is not lit, click the
Reconnect USB button and check the USB Status indicator again. If it is still not lit, then verify the EVM
is connected to the computer through the included mini-USB cable.
3. Click on the Low Level View tab then click the Load Config button.
4. Navigate to C:\Program Files(86)\Texas Instruments\ADS54Jxx EVM GUI\Configuration Files, select
the file called LMK_Config_Onboard_983p04_MSPS.cfg, then click OK. This programs the LMK04828
to provide a 983.04 MHz clock to the ADC.
5. Verify that the LMK04828 phase lock loop (PLL) is locked by checking that the PLL2 LOCKED LED
(D3) is lit.
6. Once the LMK04828 PLL is locked, press SW1 (ADC RESET) to provide a hardware reset to the ADC.
This switch is located in the middle of the EVM.
7. In the Low Level View tab, click Load Config. Select the file called ADS54J20_LMF_8224.cfg and click
OK. The ADS54J20EVM is now configured for no decimation and 8 JESD204B lanes.