ADS5423/24/33 and ADS5411 EVM
User Guide
User's Guide
February 2006
SLWU020B
2 SLWU020B – February 2005 – Revised February 2006
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Contents
1 Overview ................................................................................................................... 5
1.1 Purpose .............................................................................................................. 5
1.2 EVM Basic Functions............................................................................................... 5
1.3 Power Requirements ............................................................................................... 5
1.3.1 Voltage Limits .............................................................................................. 5
1.4 EVM Operational Procedure ...................................................................................... 5
2 Circuit Description ..................................................................................................... 7
2.1 Schematic Diagram ................................................................................................. 7
2.2 Circuit Function ..................................................................................................... 7
2.2.1 Analog Inputs .............................................................................................. 7
2.2.2 Power ........................................................................................................ 7
2.2.3 Outputs ...................................................................................................... 7
3 Parts List .................................................................................................................. 9
4 Physical Description ................................................................................................. 11
4.1 PCB Layout ........................................................................................................ 11
4.2 Schematics ......................................................................................................... 17
SLWU020B – February 2005 – Revised February 2006 Contents 3
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List of Figures
4-1 Top Layer .................................................................................................................... 11
4-2 Layer 2, Ground Plane .................................................................................................... 12
4-3 Layer 3, Power Plane #1 .................................................................................................. 13
4-4 Layer 4, Power Plane #2 .................................................................................................. 14
4-5 Layer 5, Ground Plane .................................................................................................... 15
4-6 Layer 6, Bottom Layer .................................................................................................... 16
List of Tables
1-1 Three Pin Jumper List Table ............................................................................................... 6
2-1 Output Connector J9 ........................................................................................................ 8
2-2 Test Point Description ....................................................................................................... 8
3-1 Bill of Materials for EVM .................................................................................................... 9
4 List of Figures SLWU020B – February 2005 – Revised February 2006
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1.1 Purpose
1.2 EVM Basic Functions
Chapter 1
SLWU020B – February 2005 – Revised February 2006
Overview
This User’s Guide document gives a general overview of the ADS5423/24/33 and ADS5411 evaluation
module (EVM) and provides a general description of the features and functions to be considered while
using this module.
The EVM provides a platform for evaluating the ADS5423/24/33 14-bit analog-to-digital converter (ADC)
under various signals, references, and supply conditions. This evaluation module also allows the
evaluation of the ADS5411, an 11-bit analog-to-digital converter. This document should be used in
combination with the EVM schematic diagram supplied.
Analog input to the ADC is provided via external SMA connectors. The single-ended input the user
provides is converted into a differential signal at the input of the device. One input path uses a differential
amplifier, while the other input is transformer coupled.
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input the user
provides is converted into a differential signal at the input of the device.
Digital output from the EVM is via a 40-pin connector. The digital outputs from the ADC are buffered
before going to the connector.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC
analog and digital supplies, the external buffer supply, and the differential amplifier supply.
1.3 Power Requirements
The EVM can be powered directly with only two supplies: a 3.3-V supply for the ADC digital driver supply
and external buffer supply, and 5 V for the ADC analog supply if using the EVM with transformer coupled
analog inputs. If using the differential amplifier analog inputs, ±5 V is required. Provision has also been
made to allow the EVM to be powered with independent 3.3-V supplies to provide higher performance.
1.3.1 Voltage Limits
Exceeding the maximum input voltages can damage EVM components. Under voltage may cause
improper operation of some or all of the EVM components.
1.4 EVM Operational Procedure
The EVM provides a flexible means of evaluating the ADS5423/24/33 or ADS5411 in a number of modes
of operation. A basic setup procedure that can be used as a board confidence check is as follows:
1. Verify all jumper settings against the schematic jumper list in Table 1-1 .
SLWU020B – February 2005 – Revised February 2006 Overview 5
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captured max code * captured min code
2
N
, where N is the number of bits.
EVM Operational Procedure
Table 1-1. Three Pin Jumper List Table
JUMPER FUNCTION LOCATION: PINS 1–2 LOCATION: PINS 2–3 DEFAULT
SJP3 Provides AIN+ source to ADC Source provided from T2 Source provided from Diff Amp 1–2
device
SJP4 Provides AIN– source to ADC Source provided from Diff Amp Source provided from T2 2-3
device
2. Connect supplies to the EVM as follows:
+5 V (4.75 V–5.25 V) ADC analog supply to J3 and return to J2.
+3.3 V (3 V–3.6 V) digital buffer supply to J4 and J1 and return to J6
3. Switch power supplies on.
4. Use a function generator with 50- Ω output to input a 105-MHz, 0-V offset, 1-Vrms sine-wave signal into
J5. The frequency of the clock must be within the specification for the device speed grade.
5. Supply an input signal by using a frequency generator with a 50- Ω output to provide a 15.5 MHz, 0-V
offset, –1-dBFS amplitude sine-wave signal into J11. A full-scale input tone into the ADC device is a
differential 2.2 Vpp and dBFS can be calculated by using the following formula:
6. The digital pattern on the output connector J9 should now represent a 2's compliment sine wave and
can be monitored using a logic analyzer.
6 Overview SLWU020B – February 2005 – Revised February 2006
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2.1 Schematic Diagram
The schematic diagram for the EVM is attached at the end of this document.
2.2 Circuit Function
The following paragraphs describe the function of EVM circuits. See the relevant data sheet for the device
operating characteristics.
2.2.1 Analog Inputs
The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier
inputs from a single-ended source. The default configuration uses the transformer configuration for which
the layout has been optimized to give the best performance. The inputs are provided via SMA connectors
J11 for transformer coupled input and J10 for differential amplifier input. To setup for one of these options,
the EVM must be configured as follows:
1. For a 1:1 transformer coupled input to the ADC, a single ended source is connected to J11. SJP3 has
2. For a differential input into the amplifier, the input source is connected to J10. SJP3 has pins 2 and 3
Chapter 2
SLWU020B – February 2005 – Revised February 2006
Circuit Description
pins 1 and 2 shorted and SJP4 has pins 2 and 3 shorted. This is the default configuration for the EVM.
shorted and SJP4 has pins 1 and 2 shorted. ±5VDC must be connected to the board to provide power
to U3 and U4 for this configuration.
2.2.2 Power
Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a +3.3V
digital buffer supply (J1 and J2), 5-V analog supply (J3 and J2), ±5-V amplifier supply (J7, J8, and J12),
and 3.3-V external buffer supply (J4 and J6). A single 3.3-V buffer supply could be used by installing L6.
In this case, connect the 3.3 V to J1 and the return to J2.
2.2.3 Outputs
The data outputs from the ADC are buffered using a Texas Instruments SN74AVC16244. Output data
header J9 is a standard 40-pin header on a 100-mil grid, and allows easy connection to a logic analyzer.
The connector pinout is listed in Table 2-1 . Furthermore, two test points are provided and can be
monitored using a multimeter. Description of the test points is listed in Table 2-2 .
SLWU020B – February 2005 – Revised February 2006 Circuit Description 7
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Circuit Function
Table 2-1. Output Connector J9
J9 PIN DESCRIPTION J9 PIN DESCRIPTION
1 CLK 21 DATA BIT 6
2 GND 22 GND
3 NC 23 DATA BIT 7
4 GND 24 GND
5 NC 25 DATA BIT 8
6 GND 26 GND
7 NC 27 DATA BIT 9
8 GND 28 GND
9 DATA BIT 0 (LSB) 29 DATA BIT 10
10 GND 30 GND
11 DATA BIT 1 31 DATA BIT 11
12 GND 32 GND
13 DATA BIT 2 33 DATA BIT 12
14 GND 34 GND
15 DATA BIT 3 35 DATA BIT 13 (MSB)
16 GND 36 GND
17 DATA BIT 4 37 OVERFLOW
18 GND 38 GND
19 DATA BIT 5 39 DRV
20 GND 40 GND
DD
Table 2-2. Test Point Description
TEST POINT FUNCTION
J14 Monitor Vref (AVDD/2)
J17 Monitor DMID (DVDD/2)
Circuit Description8 SLWU020B – February 2005 – Revised February 2006
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Chapter 3
SLWU020B – February 2005 – Revised February 2006
Parts List
Table 3-1 lists the parts used in constructing the EVM
Table 3-1. Bill of Materials for EVM
VALUE QTY PART NUMBER VENDOR REF DES NOT
CAPACITORS
0.1 µ F, 25 V, +80/–20% 4 ECJ-0EF1E104Z Panasonic C1, C2, C3, C4
Capacitor
0.01 µ F, 25 V, +80/–20% 6 ECJ-0EF1E103Z Panasonic C30, C31, C32, C33,
Capacitor C34, C35
220 pF, 50 V, 5%, Capacitor 6 ECJ-OEC1H221J Panasonic C41–C46
22 pF, 50 V, 5%, Capacitor 1 ECJ-1VC1H220J Panasonic C26
220 pF, 50 V, 5%, Capacitor 3 ECJ-1VC1H221J Panasonic C47, C48, C49
0.01 µ F,16 V, 10% Capacitor 7 ECJ-1VB1C103K Panasonic C27, C28, C29, C36,
C37, C38, C39
0.1 µ F,16 V, 10% Capacitor 12 ECJ-1VB1C104K Panasonic C6, C8, C11, C12,
C14, C16, C17, C18,
C19, C24, C25, C40
470 pF,50 V, 5% Capacitor 4 ECJ-1VC1H471J Panasonic C20, C21, C22, C23
10 µ F, 10 V, 10%, Capacitor 1 ECS-T1AX106R Panasonic C15
33 µ F, 10 V, 10% Capacitor 5 ECS-T1AX336R Panasonic C5, C7, C9, C10,
C13
RESISTORS
51.1 Ω 2 CTS_742 CTS R5, R25
0 Ω 2 CTS_742 CTS R7, R8
24.9 Ω resistor, 1/16 W, 1% 4 ERJ-3EKF24R9V Panasonic R6, R11, R12, R27
49.9 Ω resistor, 1/16 W, 1 % 5 ERJ-6EKF49R9V Panasonic R1, R4, R10, R18, R9
R23
36.5 Ω resistor, 1/16 W, 1% 2 ERJ-6EKF36R5V Panasonic R2, R3
499 Ω resistor, 1/16 W, 1% 4 ERJ-6EKF4990V Panasonic R14, R15, R16, R17
0 Ω resistor, 1/16 W, 1% 1 ERJ-6ENF0R00V Panasonic R24
200 Ω resistor, 1/16 W, 1% 0 ERJ-3RKF2000X Panasonic R13
FERRITE BEAD, JUMPER, TRANSFORMER, JACKS, CONN etc.
Ferrite Bead 5 EXC-ML32A680U Minicircuits L1–L5
ADT1-1WT 1 ADT1-1WT Minicircuits T2
ADT4-1WT 1 ADT4-1WT NEWARK T3
SMA End Small 3 16F3627 Keystone J5, J10, J11
Red Test Point 1 5001K-ND Keystone J14
Black Test Point 1 5000K-ND Allied J17
Red Banana Jack 5 ST-351A Allied J1, J3, J4, J8, J12
Black Banana Jack 3 ST-351B Samtec J2, J6, J7
40-Pin IDC Connector 1 TSW-120-07-L-D J9
3 Circuit Jumper 2 SJP3, SJP4
INSTALLED
SLWU020B – February 2005 – Revised February 2006 Parts List 9
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Table 3-1. Bill of Materials for EVM (continued)
VALUE QTY PART NUMBER VENDOR REF DES NOT
ICs
ADS5423/24/33 or ADS5411 1 ADS5423/24/33 or Texas Instruments U1
ADS5411
SN74AVC16244 1 SN74AVC16244DGG Texas Instruments U2
THS4503 1 THS4503 Texas Instruments U3
THS4601 1 THS4601 Texas Instruments U4
Surface Mount Jumper Location: SJP3 (2–1), SJP4 (2–3)
INSTALLED
Parts List10 SLWU020B – February 2005 – Revised February 2006
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4.1 PCB Layout
Chapter 4
SLWU020B – February 2005 – Revised February 2006
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.
The EVM is constructed on a 6-layer, 4.77-inch × 3.4-inch, 0.062-inch thick PCB using FR-4 material. The
individual layers are shown in Figure 4-1 through Figure 4-6 .
SLWU020B – February 2005 – Revised February 2006 Physical Description 11
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Figure 4-1. Top Layer
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PCB Layout
12 Physical Description SLWU020B – February 2005 – Revised February 2006
Figure 4-2. Layer 2, Ground Plane
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PCB Layout
SLWU020B – February 2005 – Revised February 2006 Physical Description 13
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Figure 4-3. Layer 3, Power Plane #1
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PCB Layout
14 Physical Description SLWU020B – February 2005 – Revised February 2006
Figure 4-4. Layer 4, Power Plane #2
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PCB Layout
SLWU020B – February 2005 – Revised February 2006 Physical Description 15
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Figure 4-5. Layer 5, Ground Plane
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PCB Layout
Physical Description16 SLWU020B – February 2005 – Revised February 2006
Figure 4-6. Layer 6, Bottom Layer
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Schematics
4.2 Schematics
SLWU020B – February 2005 – Revised February 2006 Physical Description 17
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1 2 3 4 56
A
B
C
D
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DOCUMENTCONTROL #
ADS5424
A
1
J. SETON
Y. DEWONCK
NOTE 1. DO NOT INSTALL
1
2
3 4
5
J5
SMA_PCB_MT_MOD
C1
.1uF
C2
.1uF
CLK+
CLK-
CLK+
CLK-
R4
49.9
C40
.1uF
1
2
3 4
5
J11
SMA_PCB_MT_MOD
1
2
3 4
5
J10
SMA_PCB_MT_MOD
R10
49.9
R9
49.9
C24
.1uF
31
2
SJP3
31
2
SJP4
AIN+
AIN-
AIN+
AIN-
R11
24.9
R12
24.9
R17
499
R14
499
R6
24.9
R18
49.9
R16
499
R15
499
R27
24.9
+VCC
-VCC
R13
200
3
2
6
7 4
U4
THS4601
VCM
R24
0
VREF
VREF
+VCC
-VCC
R23
49.9
C26
20pF
4
(Sh 2)
(Sh 2)
(Sh 2)
(Sh 2)
(Sh 2)
5
4
8
1
2
+
-
VOCM
VOUT-
VOUT+
36
+VCC
-VCC
7
NC
U3
THS4503
R2
36.5
R3
36.5
3
1 6
2
4
5
T2
ADT 1-1WT
3
1 6
2
4
5
T3
ADT 4-1WT
(Note 1)
(Note 1)
(2-1)
(2-1)
(2-3)
1 2 3 4 56
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DOCUMENTCONTROL #
ADS5424
A
2
J. SETON
Y. DEWONCK
NOTE 1. DO NOT INSTALL
3.3V_DVDD
CLK+
CLK-
CLK+
CLK-
AIN+
AIN-
AIN+
AIN-
5V_AVDD
C3
.1uF
C4
.1uF
OVR
D0D1D2
D3
D4
D5
D6D7D8
D9
D10
D11
D12
D13
VREF
VREF
C25
.1uF
DRY
DVDD
1
AVSS
2
VBG
3
VSS
4
+ENC
5
-ENC
6
LVSS
7
LVDD
8
CVDD
9
CVSS
10
+AIN
11
-AIN
12
AVSS
13
AVDD14ABVSS15ABVDD16AVSS17AVDD18AVSS19CEXT120AVSS21AVDD22AVSS23CEXT224AVSS25AVDD
26
PBKG
27
ADVDD
28
ADVSS
29
AVDD
30
DNC
31
OVR
32
DVDD
33
DVSS
34
DMID
35
D0
36
D1
37
D2
38
D3
39
D440D5
41
DVSS
42
DVDD
43
D644D745D846D9
47
D1048D1149D1250D13
51
DRY
52
U1A
ADS5424
OVR
D0D1D2
D3
D4
D5
D6D7D8D9D10
D11
D12
D13
DRY
PPAD
61
PPAD
62
PPAD
63
PPAD
64
PPAD
65
PPAD
66
PPAD
67
PPAD
68
PPAD
69
PPAD
70
PPAD
71
PPAD
72
PPAD73PPAD
74
PPAD
75
PPAD
76
PPAD
77
PPAD
78
PPAD
79
PPAD
80
PPAD
81
PPAD
82
PPAD
83
PPAD
84
PPAD
85
PPAD
86
U1B
ADS5424
4
(Sh 1)
(Sh 1)
(Sh 1)
(Sh 1)
(Sh 1)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
(Sh 3)
J14
RED
J17
BLACK
1 2 3 4 56
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DOCUMENTCONTROL #
ADS5424
A
3
J. SETON
Y. DEWONCK
NOTE 1. DO NOT INSTALL
1 0E
1
1Y1
2
1Y2
3
GND
4
1Y3
5
1Y4
6
VCC
7
2Y1
8
2Y2
9
GND
10
2Y3
11
2Y4
12
3Y1
13
3Y2
14
GND
15
3Y3
16
3Y4
17
VCC
18
4Y1
19
4Y2
20
GND
21
4Y3
22
4Y4
23
4 OE
24
3 OE
25
4A4
26
4A3
27
GND
28
4A2
29
4A1
30
VCC
31
3A4
32
3A3
33
GND
34
3A2
35
3A1
36
2A4
37
2A3
38
GND
39
2A2
40
2A1
41
VCC
42
1A4
43
1A3
44
GND
45
1A2
46
1A1
47
2 OE
48
U2
SN74AVC16244DGG
DRVDD
C16
.1uF
C17
.1uF
C18
.1uF
C19
.1uF
CLK
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J9
40PIN_IDC
(SH 1)
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
R5
220
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
R7
0
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
R8
0
OVR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
DRY
+
C15
10uF
C20
470pF
C21
470pF
C22
470pF
C23
470pF
4
OVR
DRY
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
R25
220
R1
220
(SH 1)
OVR/
OVR/
CLK
DRVDD
1 2 3 4 56
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C14
.1uF
DRVDD
C6
.1uF
5V_AVDD
+VCC
+3.3VA-PS
ADS5424
A
44
1 2
L5
1 2
L1
1 2
L3
+
C13
33uF
+
C5
33uF
J. SETON
Y. DEWONCK
1 2
L6
C27
.01uF
C28
.01uF
C29
.01uF
C30
.01uF
C31
.01uF
C32
.01uF
C33
.01uF
C34
.01uF
C35
.01uF
C36
.01uF
C37
.01uF
C38
.01uF
C39
.01uF
C8
.1uF
+
C7
33uF
1 2
L2
1 2
L4
C11
.1uF
+
C9
33uF
C12
.1uF
+
C10
33uF
-VCC
C41
200pF
C42
200pF
C43
200pF
C44
200pF
C45
200pF
C46
200pF
C48
200pF
C49
200pF
C47
200pF
J1
DVDD
J2
GND
J3
AVDD
3.3V_DVDD
J4
DRVDD
J6
GND
J8
+VCC
J7
GND
J12
-VEE
NOTE 1. DO NOT INSTALL
(Note 1)
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Schematics
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a
finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being
provided are not intended to be complete in terms of required design-, marketing-, and/or
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measures typically found in end products that incorporate such semiconductor components or
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TI assumes no liability for applications assistance, customer product design, software
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Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s
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22 Physical Description SLWU020B – February 2005 – Revised February 2006
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Schematics
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a
finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices
pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against
radio frequency interference. Operation of this equipment in other environments may cause
interference with radio communications, in which case the user at his own expense will be
required to take whatever measures may be required to correct this interference.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the AVDD voltage range of –0.3 V to 3.8 V and the
DVDD voltage range of –0.3 V to 3.8 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage
to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User's Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
25 ° C. The EVM is designed to operate properly with certain components above 50 ° C as long as
the input and output ranges are maintained. These components include but are not limited to
linear regulators, switching transistors, pass transistors, and current sense resistors. These types
of devices can be identified using the EVM schematic located in the EVM User's Guide. When
placing measurement probes near these devices during operation, please be aware that these
devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
SLWU020B – February 2005 – Revised February 2006 Physical Description 23
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Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
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