Texas Instruments ADS5411, ADS5423 EVM, ADS5424 EVM, ADS5433 EVM, ADS5411 EVM User Manual

ADS5423/24/33 and ADS5411 EVM
User Guide

User's Guide

February 2006

SLWU020B

2 SLWU020B – February 2005 – Revised February 2006

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Contents

1 Overview ................................................................................................................... 5

1.1 Purpose .............................................................................................................. 5

1.2 EVM Basic Functions............................................................................................... 5

1.3 Power Requirements ............................................................................................... 5

1.3.1 Voltage Limits .............................................................................................. 5

1.4 EVM Operational Procedure ...................................................................................... 5

2 Circuit Description ..................................................................................................... 7

2.1 Schematic Diagram ................................................................................................. 7

2.2 Circuit Function ..................................................................................................... 7

2.2.1 Analog Inputs .............................................................................................. 7

2.2.2 Power ........................................................................................................ 7

2.2.3 Outputs ...................................................................................................... 7

3 Parts List .................................................................................................................. 9

4 Physical Description ................................................................................................. 11

4.1 PCB Layout ........................................................................................................ 11

4.2 Schematics ......................................................................................................... 17

SLWU020B – February 2005 – Revised February 2006 Contents 3

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List of Figures

4-1 Top Layer .................................................................................................................... 11

4-2 Layer 2, Ground Plane .................................................................................................... 12

4-3 Layer 3, Power Plane #1 .................................................................................................. 13

4-4 Layer 4, Power Plane #2 .................................................................................................. 14

4-5 Layer 5, Ground Plane .................................................................................................... 15

4-6 Layer 6, Bottom Layer .................................................................................................... 16

List of Tables

1-1 Three Pin Jumper List Table ............................................................................................... 6

2-1 Output Connector J9 ........................................................................................................ 8

2-2 Test Point Description ....................................................................................................... 8

3-1 Bill of Materials for EVM .................................................................................................... 9

4 List of Figures SLWU020B – February 2005 – Revised February 2006

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1.1 Purpose

1.2 EVM Basic Functions

Chapter 1

SLWU020B – February 2005 – Revised February 2006

Overview

This User’s Guide document gives a general overview of the ADS5423/24/33 and ADS5411 evaluation
module (EVM) and provides a general description of the features and functions to be considered while
using this module.

The EVM provides a platform for evaluating the ADS5423/24/33 14-bit analog-to-digital converter (ADC)
under various signals, references, and supply conditions. This evaluation module also allows the
evaluation of the ADS5411, an 11-bit analog-to-digital converter. This document should be used in
combination with the EVM schematic diagram supplied.

Analog input to the ADC is provided via external SMA connectors. The single-ended input the user
provides is converted into a differential signal at the input of the device. One input path uses a differential
amplifier, while the other input is transformer coupled.

The EVM provides an external SMA connector for input of the ADC clock. The single-ended input the user
provides is converted into a differential signal at the input of the device.

Digital output from the EVM is via a 40-pin connector. The digital outputs from the ADC are buffered
before going to the connector.

Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC
analog and digital supplies, the external buffer supply, and the differential amplifier supply.

1.3 Power Requirements

The EVM can be powered directly with only two supplies: a 3.3-V supply for the ADC digital driver supply
and external buffer supply, and 5 V for the ADC analog supply if using the EVM with transformer coupled
analog inputs. If using the differential amplifier analog inputs, ±5 V is required. Provision has also been
made to allow the EVM to be powered with independent 3.3-V supplies to provide higher performance.

1.3.1 Voltage Limits

Exceeding the maximum input voltages can damage EVM components. Under voltage may cause
improper operation of some or all of the EVM components.

1.4 EVM Operational Procedure

The EVM provides a flexible means of evaluating the ADS5423/24/33 or ADS5411 in a number of modes
of operation. A basic setup procedure that can be used as a board confidence check is as follows:

1. Verify all jumper settings against the schematic jumper list in Table 1-1 .

SLWU020B – February 2005 – Revised February 2006 Overview 5

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captured max code * captured min code

2

N

, where N is the number of bits.

EVM Operational Procedure

Table 1-1. Three Pin Jumper List Table

JUMPER FUNCTION LOCATION: PINS 1–2 LOCATION: PINS 2–3 DEFAULT

SJP3 Provides AIN+ source to ADC Source provided from T2 Source provided from Diff Amp 1–2

device

SJP4 Provides AIN– source to ADC Source provided from Diff Amp Source provided from T2 2-3

device

2. Connect supplies to the EVM as follows:
+5 V (4.75 V–5.25 V) ADC analog supply to J3 and return to J2.
+3.3 V (3 V–3.6 V) digital buffer supply to J4 and J1 and return to J6

3. Switch power supplies on.

4. Use a function generator with 50- Ω output to input a 105-MHz, 0-V offset, 1-Vrms sine-wave signal into
J5. The frequency of the clock must be within the specification for the device speed grade.

5. Supply an input signal by using a frequency generator with a 50- Ω output to provide a 15.5 MHz, 0-V
offset, –1-dBFS amplitude sine-wave signal into J11. A full-scale input tone into the ADC device is a
differential 2.2 Vpp and dBFS can be calculated by using the following formula:

6. The digital pattern on the output connector J9 should now represent a 2's compliment sine wave and
can be monitored using a logic analyzer.

6 Overview SLWU020B – February 2005 – Revised February 2006

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2.1 Schematic Diagram

The schematic diagram for the EVM is attached at the end of this document.

2.2 Circuit Function

The following paragraphs describe the function of EVM circuits. See the relevant data sheet for the device
operating characteristics.

2.2.1 Analog Inputs

The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier
inputs from a single-ended source. The default configuration uses the transformer configuration for which
the layout has been optimized to give the best performance. The inputs are provided via SMA connectors
J11 for transformer coupled input and J10 for differential amplifier input. To setup for one of these options,
the EVM must be configured as follows:

1. For a 1:1 transformer coupled input to the ADC, a single ended source is connected to J11. SJP3 has

2. For a differential input into the amplifier, the input source is connected to J10. SJP3 has pins 2 and 3

Chapter 2

SLWU020B – February 2005 – Revised February 2006

Circuit Description

pins 1 and 2 shorted and SJP4 has pins 2 and 3 shorted. This is the default configuration for the EVM.
shorted and SJP4 has pins 1 and 2 shorted. ±5VDC must be connected to the board to provide power

to U3 and U4 for this configuration.

2.2.2 Power

Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a +3.3V
digital buffer supply (J1 and J2), 5-V analog supply (J3 and J2), ±5-V amplifier supply (J7, J8, and J12),
and 3.3-V external buffer supply (J4 and J6). A single 3.3-V buffer supply could be used by installing L6.
In this case, connect the 3.3 V to J1 and the return to J2.

2.2.3 Outputs

The data outputs from the ADC are buffered using a Texas Instruments SN74AVC16244. Output data
header J9 is a standard 40-pin header on a 100-mil grid, and allows easy connection to a logic analyzer.
The connector pinout is listed in Table 2-1 . Furthermore, two test points are provided and can be
monitored using a multimeter. Description of the test points is listed in Table 2-2 .

SLWU020B – February 2005 – Revised February 2006 Circuit Description 7

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Circuit Function

Table 2-1. Output Connector J9

J9 PIN DESCRIPTION J9 PIN DESCRIPTION

1 CLK 21 DATA BIT 6
2 GND 22 GND
3 NC 23 DATA BIT 7
4 GND 24 GND
5 NC 25 DATA BIT 8
6 GND 26 GND
7 NC 27 DATA BIT 9
8 GND 28 GND

9 DATA BIT 0 (LSB) 29 DATA BIT 10
10 GND 30 GND
11 DATA BIT 1 31 DATA BIT 11
12 GND 32 GND
13 DATA BIT 2 33 DATA BIT 12
14 GND 34 GND
15 DATA BIT 3 35 DATA BIT 13 (MSB)
16 GND 36 GND
17 DATA BIT 4 37 OVERFLOW
18 GND 38 GND
19 DATA BIT 5 39 DRV
20 GND 40 GND

DD

Table 2-2. Test Point Description

TEST POINT FUNCTION

J14 Monitor Vref (AVDD/2)
J17 Monitor DMID (DVDD/2)

Circuit Description8 SLWU020B – February 2005 – Revised February 2006

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Chapter 3

SLWU020B – February 2005 – Revised February 2006

Parts List

Table 3-1 lists the parts used in constructing the EVM

Table 3-1. Bill of Materials for EVM

VALUE QTY PART NUMBER VENDOR REF DES NOT

CAPACITORS

0.1 µ F, 25 V, +80/–20% 4 ECJ-0EF1E104Z Panasonic C1, C2, C3, C4
Capacitor

0.01 µ F, 25 V, +80/–20% 6 ECJ-0EF1E103Z Panasonic C30, C31, C32, C33,
Capacitor C34, C35

220 pF, 50 V, 5%, Capacitor 6 ECJ-OEC1H221J Panasonic C41–C46
22 pF, 50 V, 5%, Capacitor 1 ECJ-1VC1H220J Panasonic C26
220 pF, 50 V, 5%, Capacitor 3 ECJ-1VC1H221J Panasonic C47, C48, C49

0.01 µ F,16 V, 10% Capacitor 7 ECJ-1VB1C103K Panasonic C27, C28, C29, C36,
C37, C38, C39

0.1 µ F,16 V, 10% Capacitor 12 ECJ-1VB1C104K Panasonic C6, C8, C11, C12,

C14, C16, C17, C18,

C19, C24, C25, C40
470 pF,50 V, 5% Capacitor 4 ECJ-1VC1H471J Panasonic C20, C21, C22, C23
10 µ F, 10 V, 10%, Capacitor 1 ECS-T1AX106R Panasonic C15
33 µ F, 10 V, 10% Capacitor 5 ECS-T1AX336R Panasonic C5, C7, C9, C10,

C13

RESISTORS

51.1 Ω 2 CTS_742 CTS R5, R25
0 Ω 2 CTS_742 CTS R7, R8

24.9 Ω resistor, 1/16 W, 1% 4 ERJ-3EKF24R9V Panasonic R6, R11, R12, R27

49.9 Ω resistor, 1/16 W, 1 % 5 ERJ-6EKF49R9V Panasonic R1, R4, R10, R18, R9

R23

36.5 Ω resistor, 1/16 W, 1% 2 ERJ-6EKF36R5V Panasonic R2, R3
499 Ω resistor, 1/16 W, 1% 4 ERJ-6EKF4990V Panasonic R14, R15, R16, R17
0 Ω resistor, 1/16 W, 1% 1 ERJ-6ENF0R00V Panasonic R24
200 Ω resistor, 1/16 W, 1% 0 ERJ-3RKF2000X Panasonic R13

FERRITE BEAD, JUMPER, TRANSFORMER, JACKS, CONN etc.

Ferrite Bead 5 EXC-ML32A680U Minicircuits L1–L5
ADT1-1WT 1 ADT1-1WT Minicircuits T2
ADT4-1WT 1 ADT4-1WT NEWARK T3
SMA End Small 3 16F3627 Keystone J5, J10, J11
Red Test Point 1 5001K-ND Keystone J14
Black Test Point 1 5000K-ND Allied J17
Red Banana Jack 5 ST-351A Allied J1, J3, J4, J8, J12
Black Banana Jack 3 ST-351B Samtec J2, J6, J7
40-Pin IDC Connector 1 TSW-120-07-L-D J9
3 Circuit Jumper 2 SJP3, SJP4

INSTALLED

SLWU020B – February 2005 – Revised February 2006 Parts List 9

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Table 3-1. Bill of Materials for EVM (continued)

VALUE QTY PART NUMBER VENDOR REF DES NOT

ICs

ADS5423/24/33 or ADS5411 1 ADS5423/24/33 or Texas Instruments U1

ADS5411
SN74AVC16244 1 SN74AVC16244DGG Texas Instruments U2
THS4503 1 THS4503 Texas Instruments U3
THS4601 1 THS4601 Texas Instruments U4
Surface Mount Jumper Location: SJP3 (2–1), SJP4 (2–3)

INSTALLED

Parts List10 SLWU020B – February 2005 – Revised February 2006

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4.1 PCB Layout

Chapter 4

SLWU020B – February 2005 – Revised February 2006

Physical Description

This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.

The EVM is constructed on a 6-layer, 4.77-inch × 3.4-inch, 0.062-inch thick PCB using FR-4 material. The
individual layers are shown in Figure 4-1 through Figure 4-6 .

Figure 4-1. Top Layer

SLWU020B – February 2005 – Revised February 2006 Physical Description 11

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PCB Layout

Figure 4-2. Layer 2, Ground Plane

12 Physical Description SLWU020B – February 2005 – Revised February 2006

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PCB Layout

Figure 4-3. Layer 3, Power Plane #1

SLWU020B – February 2005 – Revised February 2006 Physical Description 13

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PCB Layout

Figure 4-4. Layer 4, Power Plane #2

14 Physical Description SLWU020B – February 2005 – Revised February 2006

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PCB Layout

Figure 4-5. Layer 5, Ground Plane

SLWU020B – February 2005 – Revised February 2006 Physical Description 15

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PCB Layout

Figure 4-6. Layer 6, Bottom Layer

Physical Description16 SLWU020B – February 2005 – Revised February 2006

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Schematics

4.2 Schematics

SLWU020B – February 2005 – Revised February 2006 Physical Description 17

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54321

6

D

J10

J11

5

SMA_PCB_MT_MOD

1

3 4

2

J5

SMA_PCB_MT_MOD

1

C

B

3 4

5

R4

2

49.9

T3

ADT 4-1WT

3

5

1 6

C1

4

2

CLK+

.1uF

C2

CLK-

.1uF

C40

.1uF

CLK+

CLK-

(Sh 2)

(Sh 2)

SMA_PCB_MT_MOD

1

3 4

2

5

R16

499

R18

49.9

T2

ADT 1-1WT

1 6

R9

5

49.9

(Note 1)

3

R17

499

R10

49.9

8

2

1

R15

499

(2-1)

2

4

R2

R3

C24

.1uF

+VCC

R14

499

7

NC

+

VOCM

-

36.5

36.5

VOUT-

VOUT+

+VCC

-VCC

36

U3

THS4503

5

4

-VCC

R6

24.9

C26

VCM

20pF

R23

49.9

-VCC

U4

AIN+

R13

200

(Note 1)

AIN-

7 4

2

3

THS4601

AIN+

AIN-

(Sh 2)

(Sh 2)

R24

VREF

0

VREF

(Sh 2)

R27

24.9

31

2

SJP3

(2-1)

31

(2-3)

SJP4

2

6

+VCC

R11

24.9

R12

24.9

D

C

B

A

NOTE 1. DO NOT INSTALL

A

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D

3.3V_DVDD

J14

RED

VREF

(Sh 1)

(Sh 1)

(Sh 1)

(Sh 1)

VREF

CLK+

CLK-

AIN+

AIN-

CLK+

CLK-

AIN+

AIN-

C25

.1uF

10

11

12

13

(Sh 1)

C

B

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

D8

D9

D10

D11

D12

D13

DRY

D8

D9

D10

D11

D12

D13

DRY

52

51

DRY

1

DVDD

2

AVSS

3

VBG

4

VSS

5

+ENC

6

-ENC

7

LVSS

8

LVDD

9

CVDD

CVSS

+AIN

-AIN

AVSS

AVDD14ABVSS15ABVDD16AVSS17AVDD18AVSS19CEXT120AVSS21AVDD22AVSS23CEXT224AVSS25AVDD

47

D1048D1149D1250D13

U1A

ADS5424

D7

(Sh 3)

D7

D6

(Sh 3)

D6

D644D745D846D9

43

DVDD

42

DVSS

D5

41

(Sh 3)

D5

(Sh 3)

D4

D4

D440D5

ADVSS

ADVDD

26

DMID

DVSS

DVDD

OVR

DNC

AVDD

PBKG

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

(Sh 3)

D0

D1

D2

D3

D2

D3

39

D3

38

D2

37

D1

36

D0

35

34

33

32

31

30

29

28

27

5V_AVDD

OVR

OVR

D0

D1

J17

BLACK

D

C

B

A

NOTE 1. DO NOT INSTALL

C3

.1uF

1 2 3 4 56

C4

.1uF

U1B

ADS5424

61
62
63
64
65
66
67
68
69
70
71
72

PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD73PPAD

PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD

86
85
84
83
82
81
80
79
78
77
76
75
74

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2

54321

6

D

(SH 1)

DRY

C

DRY

D13

D13

D12

D12

D11

D11

D10

D10

D9

D9

D8

D8

D7

D7

D6

D6

(SH 1)

D5

D5

D4

D4

D3

D3

D2

D2

D1

D1

D0

D0

OVR

OVR

B

R1

220

R5

1 16
2 15
3 14
4 13
5
6
7
8

220

R25

1 16
2 15
3 14
4 13
5
6
7
8

220

12
11
10
9

12
11
10
9

DRVDD

C15

10uF

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

C16

+

.1uF

U2

SN74AVC16244DGG

3 OE

4A4

4A3

GND

4A2

4A1

VCC

3A4

3A3

GND

3A2

3A1

2A4

2A3

GND

2A2

2A1

VCC

1A4

1A3

GND

1A2

1A1

2 OE

C17

C18

C19

C20

C21

C22

.1uF

.1uF

.1uF

470pF

24

4 OE

23

4Y4

22

4Y3

21

GND

20

4Y2

19

4Y1

18

VCC

17

3Y4

16

3Y3

15

GND

14

3Y2

13

3Y1

12

2Y4

11

2Y3

10

GND

9

2Y2

8

2Y1

7

VCC

6

1Y4

5

1Y3

4

GND

3

1Y2

2

1Y1

1

1 0E

470pF

470pF

C23

470pF

R7

0

1 16
2 15
3 14
4 13
5
6
7
8

R8
0

1 16
2 15
3 14
4 13
5
6
7
8

OVR/

CLK

DRVDD

J9

39 40
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11 12
9 10
7 8
5 6
3 4
1 2

40PIN_IDC

CLK

12
11
10
9

12
11
10

OVR/

9

D

C

B

A

NOTE 1. DO NOT INSTALL

A

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D

C

B

J4

DRVDD

J6

GND

J1

DVDD

J2

GND

J3

AVDD

J8

+VCC

J7

L5

1 2

L1

1 2

L2

1 2

L3

1 2

C13

+

33uF

L6

1 2

(Note 1)

C5

+

33uF

+

C9

+

33uF

33uF

DRVDD

D

C14

.1uF

3.3V_DVDD

C6

C27

C28

C29

.1uF

.01uF

.01uF

.01uF

C30

C36

.01uF

.01uF

+VCC

C31

.01uF

C37

.01uF

C8

C7

.1uF

C11

.1uF

C32

.01uF

C47

200pF

C33

.01uF

C48

200pF

C34

.01uF

C49

200pF

C35

.01uF

C41

200pF

C42

200pF

C43

200pF

C44

200pF

C45

200pF

C46

200pF

C

5V_AVDD

B

A

NOTE 1. DO NOT INSTALL

GND

J12

-VEE

1 2 3 4 56

L4

1 2

C10

+

33uF

C38

.01uF

C39

.01uF

-VCC

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Schematics

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Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,

DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a
finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being
provided are not intended to be complete in terms of required design-, marketing-, and/or
manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or
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(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the
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FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY,
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TI assumes no liability for applications assistance, customer product design, software

performance, or infringement of patents or services described herein.

Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s
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No license is granted under any patent right or other intellectual property right of TI covering or
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22 Physical Description SLWU020B – February 2005 – Revised February 2006

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Schematics

FCC Warning

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a

finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices
pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against
radio frequency interference. Operation of this equipment in other environments may cause
interference with radio communications, in which case the user at his own expense will be
required to take whatever measures may be required to correct this interference.

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Copyright © 2006, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the AVDD voltage range of –0.3 V to 3.8 V and the
DVDD voltage range of –0.3 V to 3.8 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage
to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User's Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than
25 ° C. The EVM is designed to operate properly with certain components above 50 ° C as long as
the input and output ranges are maintained. These components include but are not limited to
linear regulators, switching transistors, pass transistors, and current sense resistors. These types
of devices can be identified using the EVM schematic located in the EVM User's Guide. When
placing measurement probes near these devices during operation, please be aware that these
devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2006, Texas Instruments Incorporated

SLWU020B – February 2005 – Revised February 2006 Physical Description 23

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Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
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Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
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Low Power www.ti.com/lpw Video & Imaging www.ti.com/video

Wireless

Wireless www.ti.com/wireless

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Copyright © 2007, Texas Instruments Incorporated