Texas Instruments ADS5410 EVM User Manual

ADS5410 EVM
User’s Guide
June 2002 AAP High-Speed Data Converter (Dallas)
SLAU082
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party , or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING
DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM Users Guide, the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM W arnings and Restrictions notice in the EVM Users Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM Users Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 40°C. The EVM is designed to operate properly with certain components above 40°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM Users Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
About This Manual
This user’s guide is to assist the user with the operation of the EVM using the ADS5410 devices.
How to Use This Manual
Information About Cautions and Warnings
Preface
Read This First
This document contains the following chapters:
- Chapter 1Overview
- Chapter 2Physical Description
- Chapter 3Circuit Description
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement. A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially
cause harm to you
.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
v
Contents
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
vi
Contents
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EVM Basic Functions 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 ADS5410 EVM Operational Procedure 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Physical Description 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Bill of Materials 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Description 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Circuit Function 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Analog Inputs 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Clock Inputs 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Control Inputs 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Power 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 Outputs 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Schematic Diagram 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
2–1 Top Layer 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Inner Layer 1, Ground Plane 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Inner Layer 2, Power Plane 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Bottom Layer 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
Contents
Tables
1–1 Two Pin Jumper List 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Three Pin Jumper List 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Bill of Materials 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Output Connector J15 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes, Cautions, and W arnings
Voltage Limits 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Chapter 1
Overview
This user’s guide gives a general overview of the ADS5410 evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module.
Topic Page
1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EVM Basic Functions 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 ADS5410 EVM Operational Procedure 1-3. . . . . . . . . . . . . . . . . . . . . . . . . .
Overview
1-1
Purpose
1.1 Purpose
The ADS5410 EVM provides a platform for evaluating the ADS5410 analog-to-digital converter (ADC) under various signal, reference, and supply conditions. Use this document in combination with the EVM schematic diagram supplied.
1.2 EVM Basic Functions
Analog input to the ADC is provided via two external SMA connectors. The single-ended input the user provides is converted into a differential signal at the input of the device. One input uses a differential amplifier , while the other input is transformer coupled.
The EVM provides an external SMA connection for input of the ADC clock. The user can send this clock to the output connector with the digital data or provide a second clock source to be sent in place of the ADC clock. This allows the user to provide the required setup and hold times of the output data with respect to the output clock. See the Clock Inputs section for the proper configuration and operation.
Digital output from the EVM is via a 40-pin connector. The digital lines from the ADC are buffered before going to this connector. More information on this connector can be found in the ADC output section.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the analog and digital supply.
1.3 Power Requirements
The EVM can be powered directly with only a 1.8-V and 3.3-V supply if using the module with a transformer coupled input and an internal reference source.
A voltage of ±5 V is required if using the differential amplifier input. Provision has also been made to allow the EVM to be powered with independent analog, digital, and I/O supplies to provide higher performance.
Voltage Limits Exceeding the maximum input voltages can damage EVM
components. Undervoltage may cause improper operation of some or all of the EVM components.
1-2
ADS5410 EVM Operational Procedure
1.4 ADS5410 EVM Operational Procedure
The ADS5410 EVM provides a flexible means of evaluating the ADS5410 in a number of modes of operation. A basic setup procedure that can be used as a board confidence check is as follows:
1) Verify all jumper settings against the schematic jumper list in Table 1–1 and Table 1–2:
Table 1–1.Two Pin Jumper List
Jumper Function Installed Removed Default
W10 N/A Removed W11 N/A Removed R37 Positive analog input Transformer coupled No connection Installed R39 Negative analog input Transformer coupled No connection Installed R36 Positive analog input Differential amplifier No connection Removed R38 Negative analog input Differential amplifier No connection Removed R43, R44 Output clock option ADC clock at output connector Buff clock at output
connector
R62 Optional output clock
parallel termination
R40 Single-ended clock option Single-ended clock to ADC Differential clock input
Provides pullup termination No pullup termination Removed
to ADC
Removed
Removed
Table 1–2.Three Pin Jumper List
Jumper Function Location: Pins 1–2 Location: Pins 2–3
W3 Transformer and diff amp
common mode select W6 Power-down select Power-down mode Operate mode 2–3 W1 Reference select N/A Internal reference 2–3
ADC output common mode voltage
N/A 1–2
2) Connect supplies to the EVM as follows:
J 1.8-V digital supply to J9 and return to J10 J 3.3-V driver supply to J13 and return to J14 J 3.3-V analog supply to J6 and return to J5
3) Switch power supplies on.
Default
4) Use a function generator with 50-Ω output to input a 80-MHz differential
sine wave, 0-V offset, 1 V
(p-p)
to 6 V
. T o provide the ADC clock, connect
(p-p)
the positve output into J3 and the negative output into J16.
Note:
The frequency of the clock must be within the specification for the device speed grade.
Overview
1-3
ADS5410 EVM Operational Procedure
5) Use a function generator with 50-Ω output to input a 1.5-V offset, 3-V
(p-p)
amplitude square wave signal into J4 to be used as the buffered output clock.
Note:
This signal must be the same frequency and synchronized with the ADC clock.
6) Use a frequency generator with 50-Ω output to input a 17-MHz, 0-V offset,
1.5-V
amplitude sine wave signal into J2. This provides a transformer
(p-p)
coupled differential signal to the ADC.
7) The digital pattern on the output connector J15 now represents a sine wave and can be monitored using a logic analyzer.
1-4
Chapter 2
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module.
Topic Page
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Bill of Materials 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Description
2-1
PCB Layout
2.1 PCB Layout
Figure 2–1.Top Layer
The EVM is constructed on a 4-layer, 104 mm (4.1 inch) x 114 mm (4.5 inch) x 1,57 mm (0.062 inch) thick PCB using FR–4 material. Figure 2–1 through Figure 2–4 show the individual layers.
2-2
Figure 2–2.Inner Layer 1, Ground Plane
PCB Layout
Physical Description
2-3
PCB Layout
Figure 2–3.Inner Layer 2, Power Plane
2-4
Figure 2–4.Bottom Layer
PCB Layout
Physical Description
2-5
Bill of Materials
2.2 Bill of Materials
Table 2–1 lists the parts used in constructing the EVM.
Table 2–1.Bill of Materials
Description QTY Part Number MFG REF DES Not Installed
47 µF, 10 V, 10% tantalum ca­pacitor
5 10TPA47M Sanyo C72–C76
0.1 µF, 16 V, 10% capacitor 36 ECJ–1VB1C104K Panasonic C4, C8, C9, C12, C14–C20, C22, C23, C29–C37, C41, C44, C47, C62–C66, C81, C85, C86–C89
10 µF, 10 V, 10% capacitor 6 GRM42X5R106K10 Murata C67–C71, C83 C51–C54
0.01 µF, 50 V, 10% capacitor 13 06035A103KATZA AVX C13, C21, C40, C42, C43, C45, C46 C50, C78, C79, C82, C84, C90
1 µF, 10 V , 10% capacitor 0 ECJ-1VF1A105Z Panasonic C77 22 pF, 50 V , 5%, capacitor 2 PCC220ACVCT AVX C38, C39
0.047 µF, 50 V, 10% capacitor 0 PCC1758CT Panasonic C55, C56, C57
12 pF, 50 V , 10% 1 PCC12ACVCT Panasonic C10 2 pF, 16 V, 10% capacitor 2 ECU-V1H020CCV Panasonic C1, C2 470 pF, 50 V , 10% capacitor 2 PCC471BVCT Panasonic C3, C5 C6, C7
2.2 µF, 16 V, 10% capacitor 0 PCC1851CT Panasonic C61
Ferrite bead 5 D01608C-472 Coil Craft FB1–FB5 100- resistor, 1/16 W, 1% 0 ERJ-3EKF1000V Panasonic R30, R31, R32 392- resistor, 1/16 W, 1% 2 ERJ–3EKF392R0V Panasonic R10, R11 374- resistor, 1/16 W, 1% 1 ERJ–3EKF374R0V Panasonic R9 402- resistor, 1/16 W, 1% 1 ERJ–3EKF402R0V Panasonic R12 499- resistor, 1/16 W, 1% 0 ERJ–3EKF499R0V Panasonic R22
2.87-k resistor, 1/16 W, 1% 0 ERJ–3EKF2871V Panasonic R23
2.55-k resistor, 1/16 w, 1% 0 ERJ-3EKF2551V Panasonic R24
4.99-k resistor, 1/16 w, 1% 0 ERJ-3EKF4991V Panasonic R26
56.2- resistor, 1/16 W, 1% 1 ERJ–3EKF56R2V Panasonic R1
49.9- resistor, 1/16 W, 1% 6 ERJ–3EKF49R9V Panasonic R2–R4, R13, R14, R63
C24–C28,C80
C60
R5, R6, R7, R42
5.62-k resistor, 1/16 w, 1% 0 ERJ-3EKF5621V Panasonic R21
10- resistor, 1/16 W, 10% 2 ERJ-3EKF10R0V Panasonic R37, R39 10-k resistor, 1/16 W, 1% 0 ERJ-3EKF1002V Panasonic R18, R19, R20 1-k resistor, 1/16 W, 1% 0 ERJ-3EKF1001V Panasonic R16, R17 2-k resistor, 1/16 W, 1% 0 ERJ-3EKF2001V Panasonic R25, R33, R34,
2-6
R35
Bill of Materials
Description Not InstalledREF DESMFGPart NumberQTY
0- resistor, 1/16 W, 1% 1 ERJ–3EKF0R00V Panasonic R41 R36, R38, R40,
1K Pot 0 3296Y–102 Bourns R27, R28, R29 Transformer 1 ADT1–1WT T1 Transformer 0 T1–6T–KK81 Mini-Circuits T2 SMA connectors 6 713–4339
(901–144–8RFX) Black test point 3 5011K Keystone TP10, TP11, TP12 Red test point 1 5000K Keystone TP1 TP7, TP8, TP9 2POS header 0 TSW–150–07–L–S Samtec W10, W11 3POS header 3 TSW–150–07–L–S Samtec W1, W3, W6 2-circuit jumpers 3 863–3285 Allied
40-pin header 1 TSW–120–07–L–D Samtec J15 Red banana jacks 5 ST–351A Allied J6, J7, J9, J11, J13 Black banana jacks 4 ST351B Allied J5, J8, J10, J14 ADS5410 1 ADS5410PFB TI U2 TPS79225 0 TPS79225DBVR TI U4 100- R-pack 2 742C163101JCT Bourns RP1, RP2 SN74AVC16244DGG 1 SN74AVC16244DGG TI U5 THS4503 1 THS4503ID TI U1 OPA4227UA 0 OPA4227UA TI U3 Stand off hex (1/4” x 1”) 4 219–2063 Allied
Allied J1, J2, J3, J4, J12,
J16
(molex)
R43, R44, R45, R62
Physical Description
2-7
2-8
Chapter 3
Circuit Description
This chapter describes the circuit function and shows the schematic for the EVM.
Topic Page
3.1 Circuit Function 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Schematic Diagram 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description
3-1
Circuit Function
3.1 Circuit Function
The following paragraphs describe the function of the individual circuits. See data sheet for device operating characteristics.
3.1.1 Analog Inputs
The ADC has either transformer-coupled inputs or differential-amplifier inputs from a single-ended source. The inputs are provided via the SMA connectors J1 and J2 on the EVM, which must be configured as follows:
- For a 1:1 transformer coupled input to the ADC, a single ended source is
- For a differential amplifier input to the ADC, a single ended source is
3.1.2 Clock Inputs
connected to J2. R36 and R38 must be removed, and R37 and R39 must be installed. The input is ac-coupled and has a 50- terminator. This is the EVM initial configuration.
connected to J1. R36 and R38 must be installed, and R37 and R39 must be removed. The input has a 50-Ω terminator.
The EVM provides separate inputs for the ADC clock and output buffer clock. This allows the user to send a modified version of the ADC clock (inverted, delayed, etc.) with the output data to generate the required setup and hold times for the user interface.
3.1.2.1 Differential ADC Clock
The initial configuration of this EVM converts a single-ended input clock into a differential clock using transformer T2. To provide a true differential ADC clock, configure the board as follows:
1) Install J3, J16, R40, and R45.
2) Remove T2 and R42.
3) Connect the positive clock input to J3 and the negative clock input to J16.
3.1.2.2 Single-Ended ADC Clock
To provide a single-ended ADC clock, configure the EVM as follows:
1) Install J3, R40, and C80.
2) Remove T2, R42, and R45.
3) Apply the clock input to the SMA connector J3.
3-2
The following paragraphs describe the function of the individual circuits. See data sheet for device operating characteristics.
3.1.2.3 Buffer Clock
To provide a clock to the output buffer, apply a clock input to J4. To provided the single-ended ADC clock to the output buffer do the following:
1) Insert R43 and R44.
2) Remove R41.
3) Install R62 if a pull-up resistor is desired. Since the input clock will now be terminated at both loads, the clock signal am-
plitude should be adjusted to provide the appropriate levels at the loads.
3.1.3 Control Inputs
The ADC has one discrete input to control the operation of the device.
3.1.3.1 Power Down
With jumper W6 installed between pins 1 and 2, the ADC is in power-down mode. The device is in operate mode with jumper W6 installed between pin 2 and pin32.
3.1.4 Power
3.1.5 Outputs
Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a 3.3-V analog supply (J6 and J5), a 1.8-V digital supply (J9 and J10), a 1.8/3.3-V digital driver supply (J13 and J14), and a ±5-V analog supply (J7, J8, and J11).
The data outputs from the ADC are buffered using a SN74AVC16244 before going to header J15. The ADC and output buffer can provide 1.8-V or 3.3-V output levels. The voltage placed at the driver power inputs (J13 and J14) selects this. J15 is a standard 40-pin header on a 100-mil grid, and allows easy connection to a logic analyzer. The connector pin out is listed in Table 3–1.
Circuit Description
3-3
Schematic Diagram
Table 3–1.Output Connector J15
J15 Pin Description J15 Pin Description
1 Data bit 0 (LSB) 21 Data bit 10 2 GND 22 GND 3 Data bit 1 23 Data bit 11 4 GND 24 GND 5 Data bit 2 25 NC 6 GND 26 GND 7 Data bit 3 27 NC 8 GND 28 GND 9 Data bit 4 29 Output clock
10 GND 30 GND
11 Data bit 5 31 NC 12 GND 32 GND 13 Data bit 6 33 NC 14 GND 34 GND 15 Data bit 7 35 NC 16 GND 36 GND 17 Data bit 8 37 NC 18 GND 38 GND 19 Data bit 9 39 NC 20 GND 40 GND
3.2 Schematic Diagram
The following figures show the schematic diagram for the EVM.
3-4
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
SHEET: OF:
FILE: SIZE:
DATE:
REV:
11-Jun-2002
Drawn By:
Engineer:
Revision History
REV ECN N umber Approved
Sheet1_RevA.Sch
DOCUMENTCONTROL #
1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9
RP1
100
1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9
RP2
100
C40
0.01 uF
C13
0.01 uF
C20
0.1 uF
C43
0.01 uF
C42
0.01 uF
C19
0.1 uF
C79 .01 uF
C88
0.1 uF
C22
0.1 uF
C45
0.01 uF
C23
0.1 uF
C46
0.01 uF
DVDD
AVDD
AVDD
DRVDD
ADS5410
A
14
J. SETON
Y. DEWONCK
D11
D10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D0
D1
D10
D11
D2
D3
D4
D5
D6
D7
D8
D9
1
3
2
W6
316
2
4
T1
ADT1-1WT
1
2
3 4
5
J2
AIN
C15
0.1 uF R13
49.9
C3
470 pF
C12
0.1 uF
C38
22 pF
C5
470 pF
C18
0.1 uF
R9
374
R12
402
R1
56.2
1
2
3 4
5
J1
AIN
R11
392
R2
49.9
R3
49.9
-5VA
R10
392
+5VA
5
4
8
1
2
+
-
VOCM
VOUT-
VOUT+
36
+VCC
-VCC
7
NC
U1
THS4503
C47
0.1 uF
C16
0.1 uF
C1
2 pF
C2
2 pF
C39
22 pF
1
3
2
W3
EXTERNAL_CML
R38
0
R39
10
R37
10
R36
0
PWD High = Power Down PWD Low = Operate
Note 1. Part not installed
Note 1
Note 1
AVDD
1
AVSS
2
VINP
3
VINM
4
AVSS
5
VCM
6
AVDD
7
VREFB
8
VREFT
9
AVDD
10
AVSS
11
N/C
12
VBG13NC14NC15PWD16NC17AVDD18CLK19CLKC20AVSS21DRVSS22DRVDD23NC
24
D11
25
D10
26
D9
27
D8
28
D7
29
D6
30
D5
31
D4
32
D3
33
D2
34
D1
35
D0
36
NC
37
DRVDD
38
DRVSS
39
DVDD
40
DVSS41AVSS42AVSS
43
AVDD44AVDD
45
AVSS
46
AVDD
47
AGND
48
U2
ADS5410
C14
0.1 uF
C90
0.01 uF
C21
0.01 uF
C86
0.1 uF
C87
0.1 uF
C82
0.01 uF
C4
0.1 uF
C81
0.1 uF
C78 .01 uF
C44
0.1 uF
C41
0.1 uF
C89
0.1 uF
+
C83 10 uF
C17
0.1 uF
C50
0.01 uF
TP1
EXTERNAL_CML
REFB
REFT
REFB
REFT
1
3
2
W1
AVDD
R4
49.9
R14
49.9
1
2
3 4
5
J3
1
2
3 4
5
J16
1
2
3 4
5
J12
ADC CLOCK
C84
.01uF
CLK
CLKC
(Note 1)
R16
1K
(Note 1)
R17
1K
AVDD
C85 .1uF
R43
0
ADC_CLK
ADC_CLK
(Note 1)
C80
.1uF
(Note 1)
(Note 1)
(Note 1)
DRVDD
R42
49.9
C10
12pF
6435809
4
6
3
2
1
T2
T1-6T-KK81
R40
0
R45
0
Note 2. Part replaced with 0.1 uF capacitor for true differential clock option
(Note 2)
(Note 2)
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
FILE:
Drawn By:
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12500 TI Boulevard. Dallas, Texas 75243
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DOCUMENTCONTROL #
ADS5410
A
24
Note 1. Part not Installed
C8
0.1 uFC90.1 uF
D11
D2
D3
D4
D5
D6
D7
D8
D9
D10
D0
D1
1
2
3 4
5
J4
BUFF CLOCK
J. SETON
Y. DEWONCK
R41
0
(Note 1)
ADC_CLK
R44
0
ADC_CLK
OUTCLK
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J15
40PIN_IDC
BCLK
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
C35
0.1 uF
C36
0.1 uF
C34
0.1 uF
DRVDD
C37
0.1 uF
R62
0
R63
49.9
DRVDD
(Note 1)
A0D0
D1
D2
D3
D4
D5
D7
D8
D9
D10
D11
/OE1
1
1Y1
2
1Y2
3
1Y3
5
1Y4
6
2A1
41
2A2
40
2A3
38
2A4
37
1A1
47
1A2
46
1A3
44
1A4
43
2Y1
8
2Y2
9
2Y3
11
2Y4
12
VCC
7
GND
4
/OE2
48
/OE3
25
/OE4
24
3A1
36
3A2
35
3A3
33
3A4
32
4A1
30
4A2
29
4A3
27
4A4
26
3Y1
13
3Y2
14
3Y3
16
3Y4
17
4Y1
19
4Y2
20
4Y3
22
4Y4
23
GND
10
GND
15
GND
21
GND
28
GND
34
GND
39
GND
45
VCC
18
VCC
31
VCC
42
U5
SN74AVC16244DGG
D6
DRVDD
6435809
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
FILE:
Drawn By:
Engineer:
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
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DOCUMENTCONTROL #
C77 1 uF
C61
2.2 uF
+5VA
R23
2.87K
R22
499
R21
5.62K
1
2
3
R27
1K
R18
10K
C24
0.1 uF
R30
100
C25
0.1 uF
C6 470 pF
C55
0.047 uF
C27
0.1 uF
+5VA
R5
49.9
R33
2.0 K
W10
W11
REFT
REFT
R19
10K
R24
2.55K
R25
2K
REFB
C26
0.1 uFC7470 pF
-5VA
EXTERNAL_CML
REFB
EXTERNAL_CML
2
3
1
411
U3A
OPA4227UA
5
6
7
U3B
OPA4227UA
10
9
8
U3C
OPA4227UA
TP7
TP8
+
C51
10 uF
+
C52 10 uF
1
2
3
R28
1K
+
C53
10 uF
R31
100
C56
0.047 uF
R6
49.9
R34
2.0 K
0.1%
0.1%
C28
0.1 uF
R20
10K
R26
4.99K
1
2
3
R29
1K
+
C54
10 uF
R32
100
C57
0.047 uF
R7
49.9
R35
2.0 K
0.1%
12
13
14
U3D
OPA4227UA
TP9
EN3BYPASS
4
OUT
5
GND
2
IN
1
U4
TPS79225
C60
.01 uF
+2.5V
(2.15V TYP)
(1.15V TYP)
(1.65 V TYP)
ADS5410
A
34
J. SETON
Y. DEWONCK
6435809
Note 1. Part not installed
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
FILE:
Drawn By:
Engineer:
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
SHEET: OF:
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REV:
11-Jun-2002
DOCUMENTCONTROL #
C29
0.1 uF
AVDD ADC Analog Supply (+3.3V)
C31
0.1 uF
DVDD
ADC Digital Supply (+1.8V)
C33
0.1 uF
DRVDD
ADC Driver Supply (+1.8V/3.3v)
+3.3VA-PS
+1.8VD-PS
+3.3VD-PS
ADS5410
A
44
J6
BANANA_JACK
J5
BANANA_JACK
FB1
FB2
FB5
J9
BANANA_JACK
J10
BANANA_JACK
J13
BANANA_JACK
J14
BANANA_JACK
+
C67 10 uF
+
C72 47 uF
+
C69 10 uF
+
C71 10 uF
+
C74 47 uF
+
C76 47 uF
C62
0.1 uF
C64
0.1 uF
C66
0.1uF
TP12 TP10 TP11
C30
0.1 uF
+5VA
Diff Driver +5V supply
C32
0.1 uF
-5VA
Diff Driver -5V supply
+5VA-PS
-5VA-PS
J7
BANANA_JACK
J8
BANANA_JACK
FB3
FB4
J11
BANANA_JACK
+
C68 10 uF
+
C73 47 uF
+
C70 10 uF
+
C75 47 uF
C63
0.1 uF
C65
0.1 uF
J. SETON
Y. DEWONCK
6435809
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments: ADS5410EVM
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