Texas Instruments ADS42JB46, ADS42JB49, ADS42JB69 User Manual

User's Guide

SLAU467D–November 2012–Revised February 2017

ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation

Module

This document outlines the basic steps and functions that are required to ensure the proper operation of the Texas Instruments (TI) ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Modules (hereafter in this document, ADS42JBxxEVM or EVM). The EVM package includes an ADS42JBxxEVM, a 5-VDC power supply, and a mini-USB cable. This EVM is designed to be used with the TSW14J5xEVM (a JESD204B data capture card). The ADS42JBxx EVM can also be connected to all FPGA development platforms with an FMC connector for evaluation. The ADS42JBxxEVM includes either an ADS42JB49 (14bit), or ADS42JB69 (16-bit) dual-channel, 250-MSPS, or an ADS42JB46 (14-bit) dual channel, 160-MSPS analog-to-digital converter. The EVM also includes a TI LMK04828 clock jitter cleaner to provide a low jitter/phase noise sampling clock to the ADC. This user's guide outlines the steps to quickly evaluate the performance of the ADS42JBxx ADC by capturing and displaying signal waveforms using the TSW14J5xEVM and the High Speed Data Converter Pro GUI software. The EVM schematics, BOMs, and layout files are found in the design package under the ADS42JBxxEVM product folder available on

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Contents

1 Introduction ................................................................................................................... 2

1.1 Overview............................................................................................................. 2

1.2 Block Diagram....................................................................................................... 3

2 Software Control ............................................................................................................. 4

2.1 Installation Instructions for ADS42JBxxEVM GUI .............................................................. 4

2.2 Quick Start........................................................................................................... 5

3 Software Operation.......................................................................................................... 9

3.1 Top Level GUI Controls............................................................................................ 9

3.2 ADC Controls ...................................................................................................... 10

3.3 LMK Controls ...................................................................................................... 13

3.4 Low Level View.................................................................................................... 17

List of Figures

1 Block Diagram of the ADS42JBxxEVM................................................................................... 3

2 EVM Hardware Setup....................................................................................................... 5

3 ADS42JBxx EVM GUI Setup............................................................................................... 6

4 HSDC Pro Software Setup ................................................................................................. 7

5 ADC Data Capture, 25 MHz Sinusoid, 250 MSPS Sampling Rate ................................................... 8

6 Top-Level Block Diagram Window of the ADS42JBxx GUI............................................................ 9

7 ADC Controls Window of the ADS42JBxx GUI ........................................................................ 10

8 LMK04828 Outputs Control Window of the ADS42JBxx GUI ........................................................ 13

9 LMK04828 PLL2 Controls................................................................................................. 14

10 LMK04828 SYSREF and SYNC Settings............................................................................... 15

11 LMK04828 Output Clock Settings........................................................................................ 16

12 Low Level View............................................................................................................. 17

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Introduction

1 Input and Output Connectors and Jumper Descriptions of the ADS42JBxxEVM................................... 4

2 ADC device ini file selection in HSDC Pro ............................................................................... 7

3 ADC Controls Window Descriptions ..................................................................................... 11

Trademarks

Microsoft, Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

1 Introduction

1.1 Overview

The ADS42JBxxEVM is an evaluation module (EVM) used to evaluate Texas Instruments’ ADS42JBxx ADC. The ADS42JB49 (14-bit) and ADS42JB69 (16-bit) are low-power, 250-MSPS analog-to-digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. The ADS42JB46 (14-bit) is a low power 160-MSPS ADC version of the same family of ADC's. The EVM has transformer-coupled analog inputs accommodating a wide range of signal sources and frequencies. The onboard LMK04828 provides an ultra-low jitter and phase-noise ADC sample clock along with system reference clocks (SYSREF) for the ADC and the mating FPGA capture board (TSW14J5xEVM), for a complete JESD204B subclass 1 clocking solution.

The ADS42JBxx and LMK04828 are controlled through an easy-to-use software GUI enabling quick configuration for a variety of modes.

The TSW14J5xEVM is an FPGA-based data capture platform that mates with the ADS42JBxxEVM across an FMC connector. Sampled data from the ADS42JBxx EVM is captured by the FPGA and stored in external DDR3 memory. The HSDC Pro software interface is available for reading and displaying the stored ADC samples in both frequency and time domains.

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List of Tables

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ADS42JBxxEVM

CHA

CHB

LMK04828 JESD204B

Clock Generator

USB

5VDC

SYSREF A

FMC Connector (Male)

DEVCLK A

SYSREF B

DEVCLK B

SYNC

4 TX

ADS42JBxx

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1.2 Block Diagram

The block diagram for the ADS42JB69EVM is shown in Figure 1. The various inputs, outputs, and jumper configurations of the ADS42JBxxEVM are described in Table 1.

Introduction

Figure 1. Block Diagram of the ADS42JBxxEVM

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Table 1. Input and Output Connectors and Jumper Descriptions of the ADS42JBxxEVM

Component Description

J1 (AINP) Single-ended analog input for channel A J2 (BINP) Single-ended analog input for channel B J19 (EXT_ADC_CLK) Single-ended ADC clock input J8 (+5V) Positive power connection (5 V) J9 (GND) Negative power connection (GND) J13 (Main PWR) 5-V input for provided power cable J14 (REF OSC_IN) External reference option for LMK04828, REFOUT1 source on J16 and CPLD_CLK J16 (REFOUT1) 10-MHz CMOS level reference output or frequency of REF OSC_IN if option selected J6 (USB) USB connection J3 JESD204B FMC interface connector J5 (LMK SYNC) LMK04828 sync input J7 (LMK CLKIN1_P) CLKIN0 input for LMK04828. Option to provide an external clock source to the LMK in place of on-

J10 (CLKOUT10P) DCLKOUT6p from LMK04828. Default is LVPECL at 250 MHz. J15 (CLKOUT10N) DCLKOUT6n from LMK04828. Default is LVPECL at 250 MHz. J17 (CLKOUT12P) SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz. J4 (CLKOUT12M) SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz. J18 (PROG CPLD) JTAG interface for CPLD U3 SW1 (ADC_RESET) Switch to reset the ADC using the RESET input pin SW3 (CPLD) Switch inputs to CPLD. Currently not used. SW2 (Reset CPLD) CPLD reset SJP12 ADC CNTRL1 pin. Not used by ADC. Connected to GND. JP3 ADC CNTRL2 pin. Not used by ADC. Connected to GND. JP6 (XO_PWR) Provides power to VCXO Y2 or oscillator Y3 SJP3 (REF_SEL) Selects input or external reference source for LMK, J16 and CPLD. Default is internal 10-MHz source. JP2 (CDC_CLK) Reference clock buffer output enable JP5 (REF_PWR) Power enable for 10-MHz reference oscillator SJP1 (REF_EN) Enable for 10-MHz reference oscillator SJP4-SJP11 USB/FMC Interface select. Default is using USB. SJP2 (WP) EEPROM write protect. JP4 (ENABLE) U11 enable. Install jumper to disable switcher U11. Default is uninstalled. JP1 (PWRGD) Test point for power good output pin from U11.

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board 100-MHz VCXO.

2 Software Control

This section provides installation instructions for the ADS42JBxx GUI and descriptions of the various controls. Please note, any illustration and textual references to ADS42JB69 or ADS42JBx9 in this section apply to the ADS42JB46 as well.

2.1 Installation Instructions for ADS42JBxxEVM GUI

1. Download the software installation package (SLAC544) from the ADS42JBxxEVM product page.

2. Extract the files from the zip file named ADS42JBx9 GUI vXpY installer.zip where XpY represents the version number.

3. Run setup.exe and follow the installation prompts to install the software.

4. After successfully installing the software, start the GUI by going to Start Menu → All Programs →

Texas Instruments ADCs → ADS42JBxx GUI

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AINP

AINM

ADC

Reset

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2.2 Quick Start

Figure 2 illustrates the EVM hardware setup.

Software Control

Figure 2. EVM Hardware Setup

Use the following steps to set up the ADS42JBxxEVM and TSW14J5xEVM for evaluation:

1. Connect the ADS42JBxx EVM to the TSW14J5x via the FMC connector.

2. Plug one end of the provided 5-V power cables into both EVMs and connect the other ends to a +5V DC power supply capable of providing 4 amps.

3. Plug a mini-USB into both EVMs. Plug the other end of USB to the PC or laptop running the ADS42JBxx software and HSDC Pro software. Note: When plugging the ADS42JBxxEVM board into the computer through the USB cable for the first time, you are prompted to install the USB drivers.

• Microsoft®Windows®XP: If Windows XP does not automatically install the drivers, follow the

prompts on the screen to do so. Do not let Windows XP search Microsoft Update for the drivers, but do let Windows XP install the drivers automatically.

• Windows 7: After installing the GUI, Windows 7 should automatically be able to install the drivers

for the ADS42JBxxEVM with no user input.

4. Move SW6 on the TSW14J56 (or SW3 on the TSW14J57) to the ‘ON’ position to power up the board.

5. IMPORTANT: Push the hardware reset (SW1) on the ADS42JBxx EVM board. This is required each time the EVM is powered up to ensure proper operation.

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Figure 3. ADS42JBxx EVM GUI Setup

6. Start the ADS42JBxxEVM software (Figure 3).

• On Windows platforms, start the ADS42JBxx EVM GUI software from Start → All Programs →

Texas Instruments ADCs → ADS42JBxx.

7. Go to "Low Level View" and click the "Load Config" button. ADS42JB69_EVM_LMF421_250M.cfg. This configuration file should be located in the GUI software installation directory.

• The configuration file sets the ADC up for Fsampling = 250 MHz, lane rate = 2.5 GHz, L = 4, M =

2, F = 1.

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Figure 4. HSDC Pro Software Setup

8. Start the HSDC Pro GUI and follow the onscreen prompts to connect to the TSW14J5x board.

9. In the ADC selection box, select ADS42JBxx_LMF_421. xx represents the unique part number for the device being evaluated. Table 2 summarizes the ADC to choose based on the device and mode being evaluated.

Table 2. ADC device ini file selection in HSDC Pro

Device Mode HSDC Pro ini file

ADS42JB46 20x ADS42JB46_LMF_222 ADS42JB46 10x ADS42JB46_LMF_421 ADS42JB49 20x ADS42JB49_LMF_222 ADS42JB49 10x ADS42JB49_LMF_421 ADS42JB69 20x ADS42JB69_LMF_222 ADS42JB69 10x ADS42JB69_LMF_421

10. After selecting the appropriate ADC, click Yes when prompted to download firmware.

11. After the firmware downloads, LED's D8 and D3 should be ON for the TSW14J5xEVM.

12. Set the data capture to 65536 samples and the ADS Sampling Rate as 250MSPS.

13. Click the Capture button to capture data from the ADC.

• With no input signal connected to the ADC inputs, the captured noise floor of the ADC should look

like Figure 4.

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14. Connect an analog signal to analog INP or analog INM and capture the data again from the ADC.

Figure 5 shows data captured from the ADC with a 25-MHz sinusoid at analog INP and sampling rate

of 250 MSPS.

• You can switch between data from channel 1 and 2 of the ADC from the HSDC Pro GUI interface.

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Refer to the HSDC Pro GUI users guide (SLWU087) for more details.

Figure 5. ADC Data Capture, 25 MHz Sinusoid, 250 MSPS Sampling Rate

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Texas Instruments ADS42JB46, ADS42JB49, ADS42JB69 User Manual

Specifications and Main Features

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