TEXAS INSTRUMENTS ADS1602 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

查询ADS1602供应商查询ADS1602供应商

ADS1602

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

16-Bit, 2.5MSPS

Analog-to-Digital Converter

FEATURES

D High Speed:

Data Rate: 2.5MSPS
Bandwidth: 1.23MHz

D Outstanding Performance:

SNR: 91dB at fIN = 100kHz, −1dBFS
THD: −101dB at fIN = 100kHz, −6dBFS
SFDR: 103dB at fIN = 100kHz, −6dBFS

D Ease-of-Use:

High-Speed 3-Wire Serial Interface
Directly Connects to TMS320 DSPs
On-Chip Digital Filter Simplifies Anti-Alias

Requirements

Simple Pin-Driven Control—No On-Chip

Registers to Program
Selectable On-Chip Voltage Reference
Simultaneous Sampling with Multiple

ADS1602s

D Low Power:

530mW at 2.5MSPS
Power-Down Mode

APPLICATIONS

D Sonar
D Vibration Analysis
D Data Acquisition

VREFP VREFN RBIASVMID VCAP AVDD DVDD IOVDD

Referenceand Bias Circuits

AINP
AINN

Modulator

ADS1602

∆Σ

FIR Digital Filter

InterfaceLinear Phase

Serial

DGNDAGND

CLK
SYNC
FSO
FSO
SCLK
SCLK
DOUT
DOUT
OTR

PD
REFEN

DESCRIPTION

The ADS1602 is a high-speed, high-precision,
delta-sigma analog-to-digital converter (ADC)
manufactured on an advanced CMOS process. The
ADS1602 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is −101dB, and the spurious-free dynamic range
(SFDR) is 103dB.

Optimized for power and performance, the ADS1602
dissipates only 530mW while providing a full-scale
differential input range of ±3V. Having such a wide input
range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. Th e d i fferential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1602.

The ADS1602 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 38.6MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 40MSPS, depending on f
decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and

0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial

interface at rates up to 2.5MSPS, with a −3dB bandwidth
of 1.23MHz. The output data or its complementary format
directly connects to DSPs such as TI’s TMS320 family,
FPGAs, or ASICs. A dedicated synchronization pin
enables simultaneous sampling with multiple ADS1602s
in multi-channel systems. Power dissipation is set by an
external resistor that allows a reduction in dissipation
when operating at slower speeds. All of the ADS1602
features are controlled by dedicated I/O pins, which
simplify operation by eliminating the need for on-chip
registers.

The high performing, easy-to-use ADS1602 is especially
suitable for demanding measurement applications in
sonar, vibration analysis, and data acquisition. The
ADS1602 is offered in a small, 7mm x 7mm TQFP-48
package and is specified from −40°C to +85°C.

, while the 16x

CLK

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All other trademarks are the property of their respective owners.

         
          
 !     !   

www.ti.com

Copyright  2004−2005, Texas Instruments Incorporated

"#$%&

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

www.ti.com

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information see
the Package Option Addendum located at the end of this
datasheet or visit the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operat i n g f ree-air temperature range unless otherwise noted

ADS1602 UNIT

AVDD to AGND −0.3 to +6 V
DVDD to DGND −0.3 to +3.6 V
IOVDD to DGND −0.3 to +6 V
AGND to DGND −0.3 to +0.3 V
Input Current 100mA, Momentary
Input Current 10mA, Continuous
Analog I/O to AGND −0.3 to AVDD + 0.3 V
Digital I/O to DGND −0.3 to IOVDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range −40 to +105 °C
Storage Temperature Range −60 to +150 °C
Lead Tem perature (soldering, 10s) +260 °C

(1)

Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.

(1)

This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be

handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ADS1602 passes standard 200V machine model and 1.5K CDM
testing. ADS1602 passes 1kV human body model testing (TI Standard
is 2kV).

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.

2

"#$%&

Signal-to-noise ratio (SNR)

Total harmonic distortion (THD)

Signal-to-noise + distortion (SINAD)

Spurious-free dynamic range (SFDR)

www.ti.com

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS

All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
and R

Analog Input

Differential input voltage (VIN)
(AINP − AINN)

Common-mode input voltage (VCM)
(AINP + AINN) / 2

Absolute input voltage
(AINP or AINN with respect to AGND)

Dynamic Specifications

Data Rate

Signal-to-noise ratio (SNR)

Total harmonic distortion (THD)

Signal-to-noise + distortion (SINAD)

Spurious-free dynamic range (SFDR)

Intermodulation distortion (IMD)

Aperture delay 4 ns

= 37kΩ, unless otherwise noted.

BIAS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0dBFS ±V

fIN = 10kHz, −1dBFS 92 dB
fIN = 10kHz, −3dBFS 87 90 dB

fIN = 10kHz, −6dBFS 84 87 dB
fIN = 100kHz, −1dBFS 91 dB
fIN = 100kHz, −3dBFS 87 89 dB
fIN = 100kHz, −6dBFS 84 86 dB
fIN = 800kHz, −1dBFS 91 dB
fIN = 800kHz, −3dBFS 89 dB
fIN = 800kHz, −6dBFS 86 dB

fIN = 10kHz, −1dBFS −94 dB

fIN = 10kHz, −3dBFS −106 −92 dB

fIN = 10kHz, −6dBFS −108 −93 dB
fIN = 100kHz, −1dBFS −90 dB
fIN = 100kHz, −3dBFS −96 −90 dB
fIN = 100kHz, −6dBFS −101 −92 dB
fIN = 800kHz, −1dBFS −116 dB
fIN = 800kHz, −3dBFS −114 dB
fIN = 800kHz, −6dBFS −110 dB

fIN = 10kHz, −1dBFS 89 dB

fIN = 10kHz, −3dBFS 85 90 dB

fIN = 10kHz, −6dBFS 82 87 dB
fIN = 100kHz, −1dBFS 87 dB
fIN = 100kHz, −3dBFS 85 88 dB
fIN = 100kHz, −6dBFS 82 86 dB
fIN = 800kHz, −1dBFS 91 dB
fIN = 800kHz, −3dBFS 89 dB
fIN = 800kHz, −6dBFS 86 dB

fIN = 10kHz, −1dBFS 95 dB

fIN = 10kHz, −3dBFS 90 107 dB

fIN = 10kHz, −6dBFS 93 112 dB
fIN = 100kHz, −1dBFS 91 dB
fIN = 100kHz, −3dBFS 90 96 dB
fIN = 100kHz, −6dBFS 93 103 dB
fIN = 800kHz, −1dBFS 120 dB
fIN = 800kHz, −3dBFS 119 dB
fIN = 800kHz, −6dBFS 114 dB

f1 = 995kHz, −6dBFS

f2 = 1005kHz, −6dBFS

= 40MHz, External V

CLK

= +3V , VCM = +1.45V ,

REF

ADS1602

REF

1.45 V

−0.1 4.6 V

f

CLK

ǒ

2.50

Ǔ

40MHz

94 dB

V

MSPS

3

"#$%&

www.ti.com

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
and R

Digital Filter Characteristics

Passband 0

Passband ripple ±0.001 dB

Passband transition

Stop band

Stop band attenuation 75 dB

Group delay

Settling time Complete settling

Static Specifications

Resolution 16 Bits
No missing codes 16 Bits
Input-referred noise 0.5 0.85 LSB, rms
Integral nonlinearity −1dBFS signal 0.75 LSB
Differential nonlinearity 0.25 LSB
Offset error −0.1 %FSR
Offset error drift −0.1 ppmFSR/°C
Gain error 0.25 %
Gain error drift Excluding reference drift 10 ppm/°C
Common-mode rejection At DC 75 dB
Power-supply rejection At DC 65 dB
Internal Voltage Reference REFEN = low
V

REF

VREFP 3.5 4.0 4.3 V
VREFN 0.5 1.0 1.3 V
VMID 2.3 2.5 2.7 V
V

REF

Startup time 15 ms
External Voltage Reference REFEN = high
V

REF

VREFP 3.5 4 4.25 V
VREFN 0.5 1 1.5 V
VMID 2.3 2.5 2.6 V

= 37kΩ, unless otherwise noted.

BIAS

PARAMETER UNITMAXTYPMINTEST CONDITIONS

−0.1dB attenuation

−3.0dB attentuation

= (VREFP − VREFN) 2.75 3 3.25 V

drift 50 ppm/°C

= (VREFP − VREFN) 2.0 3 3.25 V

= 40MHz, External V

CLK

1.4

ǒ

40MHz

f

CLK

= +3V , VCM = +1.45V ,

REF

ADS1602

f

CLK

ǒ

40MHz

ǒ

40MHz

f

CLK

Ǔ

Ǔ

1.15

1.23

Ǔ

40MHZ

ǒ

40MHZ

ǒ

f

CLK

f

CLK

Ǔ

Ǔ

10.4

20.4

1.1

38.6

ǒ

40MHz

ǒ

40MHz

f

f

CLK

CLK

MHz

Ǔ

MHz

MHz

MHz

Ǔ

µs

µs

4

"#$%&

Power dissipation

Power dissipation

www.ti.com

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
and R

Clock Input

Frequency (f
Duty Cycle f

Digital Input/Output

V

IH

V

IL

V

OH

V

OL

Input leakage DGND < V

Power-Supply Requirements

AVDD 4.75 5.25 V
DVDD 2.7 3.3 V
IOVDD IOH = 50µA 2.7 5.25 V

AVDD current (I

DVDD current (I
IOVDD current (I

Temperature Range

Specified −40 +85 °C
Operating −40 +105 °C
Storage −60 +150 °C

= 37kΩ, unless otherwise noted.

BIAS

PARAMETER UNITMAXTYPMINTEST CONDITIONS

) 40 MHz

CLK

= 40MHz 45 55 %

CLK

IOH = 50µA IOVDD − 0.5 V
IOL = 50µA DGND + 0.5 V

< IOVDD ±10 µA

DIGIN

)

AVDD

) IOVDD = 3V 25 30 mA

DVDD

) IOVDD = 3V 8 10 mA

IOVDD

REFEN = low 110 125 mA

REFEN = high 88 98 mA

AVDD = 5V, DVDD = 3V,

IOVDD = 3V, REFEN

PD = low, CLK disabled 10 mW

= high

= 40MHz, External V

CLK

0.7 x IOVDD IOVDD V

= +3V , VCM = +1.45V ,

REF

ADS1602

DGND 0.3 x IOVDD V

530 610 mW

5

"#$%&

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

DEFINITIONS

www.ti.com

Absolute Input Voltage

Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.

Aperture Delay

Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.

Common-Mode Input Voltage

Common-mode input voltage (VCM) is the average voltage
of the analog inputs:

(AINP ) AINN)

2

Differential Input Voltage

Differential input voltage (VIN) is the voltage difference
between the analog inputs (AINP−AINN).

Differential Nonlinearity (DNL)

DNL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.

Full-Scale Range (FSR)

FSR is the difference between the maximum and minimum
measurable input signals (FSR = 2V

REF

).

Gain Error

Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.

Gain Error Drift

Gain error drift, given in ppm/_C, is the drift over
temperature of t h e g a i n e r r o r. The gain error is specified as
the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.

Integral Nonlinearity (INL)

INL, given in least-significant bits of the output code (LSB),
is the maximum deviation of the output codes from a best
fit line.

Intermodulation Distortion (IMD)

IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.

Offset Error

Offset Error , given in % of FSR, is the output reading when
the differential input is zero.

Offset Error Drift

Offset error drift, given in ppm of FSR/_C, is the drift over
temperature of the of fset error. The offset error is specified
as the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.

Signal-to-Noise Ratio (SNR)

SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f

/2 (the Nyquist frequency) excluding the first six

CLK

harmonics of the input signal and the dc component.

Signal-to-Noise and Distortion (SINAD)

SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f

/2 (the Nyquist frequency) including the harmonics of

CLK

the input signal but excluding the dc component.

Spurious-Free Dynamic Range (SFDR)

SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.

Total Harmonic Distortion (THD)

THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.

6

www.ti.com

FUNCTION

DESCRIPTION

PIN ASSIGNMENTS

VREFP

VREFP

VMID

VREFN

VREFN

VCAP

AVDD

AGND

CLK

AGND

48 47 46 45 44 43 42 41 40 39 38

"#$%&

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

DGND

IOVDD

NC

36

DGND

35

NC

34

DVDD

33

DGND

32

FSO

31

FSO

30

DOUT

29

DOUT

28

SCLK

27

SCLK

26

NC

25

NC

TQFP PACKAGE

(TOP VIEW)

AGND

AVDD

AGND

AINN
AINP

AGND

AVDD

RBIAS

AGND

AVDD

AGND

AVDD

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 233724

NC

REFEN

RPULLUP

NC

ADS1602

PD

DVDD

SYNC

DGND

OTR

DVDD

DGND

Terminal Functions

TERMINAL

NAME NO.

AGND 1, 3, 6, 9, 11, 39, 41 Analog Analog ground
AVDD 2, 7, 10, 12, 42 Analog Analog supply
AINN 4 Analog input Negative analog input
AINP 5 Analog input Positive analog input
RBIAS 8 Analog Terminal for external analog bias setting resistor.
REFEN 13 Digital input: active low Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
NC 14, 16, 24−26, 35 Do not connect These terminals must be left unconnected.
RPULLUP 15 Digital Input Pull-up to DVDD with 10kΩ resistor (see Figure 53).
PD 17 Digital input: active low Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
DVDD 18, 23, 34 Digital Digital supply
DGND 19, 22, 33, 36, 38 Digital Digital ground
SYNC 20 Digital input Synchronization control input
OTR 21 Digital output Indicates analog input signal is out of range.
SCLK 28 Digital output Serial clock output
SCLK 27 Digital output Serial clock output, complementary signal.
DOUT 30 Digital output Data output

DOUT 29 Digital output Data output, complementary signal.

FSO 32 Digital output Frame synchronization output
FSO 31 Digital output Frame synchronization output, complementary signal.
IOVDD 37 Digital Digital I/O supply
CLK 40 Digital input Clock input
VCAP 43 Analog Terminal for external bypass capacitor connection to internal bias voltage.
VREFN 44, 45 Analog Negative reference voltage
VMID 46 Analog Midpoint voltage
VREFP 47, 48 Analog Positive reference voltage

7

"#$%&

t

Settling time of ADS1602

(1)

www.ti.com

SBAS341B − DECEMBER 2004 − REVISED APRIL 2005

TIMING DIAGRAMS

CLK

t

STL

SYNC

FSO

TIMING REQUIREMENTS

For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.

SYMBOL DESCRIPTION MIN TYP MAX UNIT

t

SYPW

STL

NOTE:(1) An FSO pulse occuring prior to T

SYNC positive pulse width

t

SYPW

Figure 1. Initialization Timing

≥ 816 CLK period should be ignored.

STL

2 16 CLK periods

51 52 Conversions

816 832 CLK periods

t

DPD

t

CPW

t

CPW

Bit 1 Bit 0 (LSB)Bit 15 (MSB) Bit14

New Data

CLK

FSO

SCLK

DOUT

t

C

t

CF

t

FPW

t

CS

t

DHD

Bit 0 (LSB)

Old Data

Figure 2. Data Retrieval Timing

TIMING REQUIREMENTS

For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.

SYMBOL DESCRIPTION MIN TYP MAX UNIT

t

C

t

CPW

t

CF

t

FPW

t

CS

t

DHD

t

DPD

CLK period (1/f

CLK

)
CLK positive or negative pulse width
Rising edge of CLK to rising edge of FSO
FSO positive pulse width
Rising edge of CLK to rising edge of SCLK
SCLK rising edge to old DOUT invalid (hold time)
SCLK rising edge to new DOUT valid (propagation delay)

25 ns

11.25 ns
15 ns

1 CLK period

15 ns

0 ns

5 ns

8