TEXAS INSTRUMENTS ADS1601 Technical data
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
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SBAS322 − DECEMBER 2004
FEATURES
D High Speed:
Data Rate: 1.25MSPS
Bandwidth: 615kHz
D Outstanding Performance:
SNR: 92dB at fIN = 100kHz, −1dBFS
THD: −103dB at fIN = 100kHz, −6dBFS
SFDR: 105dB at fIN = 100kHz, −6dBFS
D Ease-of-Use:
High-Speed 3-Wire Serial Interface
Directly Connects to TMS320 DSPs
On-Chip Digital Filter Simplifies Anti-Alias
Requirements
Simple Pin-Driven Control—No On-Chip
Registers to Program
Selectable On-Chip Voltage Reference
Simultaneous Sampling with Multiple
ADS1601s
D Low Power:
330mW at 1.25MSPS
145mW at 625kSPS
Power-Down Mode
APPLICATIONS
D Sonar
D Vibration Analysis
D Data Acquisition
VREFP VREFN RBIASVMID VCAP AVDD DVDD IOVDD
Referenceand Bias Circuits
AINP
AINN
Modulator
ADS1601
∆Σ
FIR Digital Filter
InterfaceLinear Phase
Serial
DGNDAGND
CLK
SYNC
FSO
FSO
SCLK
SCLK
DOUT
DOUT
OTR
PD
REFEN
DESCRIPTION
The ADS1601 is a high-speed, high-precision,
delta-sigma analog-to-digital converter (ADC)
manufactured on an advanced CMOS process. The
ADS1601 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is −103dB, and the spurious-free dynamic range
(SFDR) is 105dB.
Optimized for power and performance, the ADS1601
dissipates only 330mW while providing a full-scale
differential input range of ±3V. Having such a wide input
range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. Th e d i fferential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1601.
The ADS1601 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 19.3MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 20MSPS, depending on f
decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and
0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial
interface at rates up to 1.25MSPS, with a −3dB bandwidth
of 615kHz. The output data or its complementary format
directly connects to DSPs such as TI’s TMS320 family,
FPGAs, or ASICs. A dedicated synchronization pin
enables simultaneous sampling with multiple ADS1601s
in multi-channel systems. Power dissipation is set by an
external resistor that allows a reduction in dissipation
when operating at slower speeds. All of the ADS1601
features are controlled by dedicated I/O pins, which
simplify operation by eliminating the need for on-chip
registers.
The high performing, easy-to-use ADS1601 is especially
suitable for demanding measurement applications in
sonar, vibration analysis, and data acquisition. The
ADS1601 is offered in a small, 7mm x 7mm TQFP-48
package and is specified from −40°C to +85°C.
, while the 16x
CLK
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2004, Texas Instruments Incorporated
SBAS322 − DECEMBER 2004
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PACKAGE/ORDERING INFORMATION
For the most current package and ordering information see
the Package Option Addendum located at the end of this
datasheet.
ABSOLUTE MAXIMUM RATINGS
over operat i n g f ree-air temperature range unless otherwise noted
ADS1601 UNIT
AVDD to AGND −0.3 to +6 V
DVDD to DGND −0.3 to +3.6 V
IOVDD to DGND −0.3 to +6 V
AGND to DGND −0.3 to +0.3 V
Input Current 100mA, Momentary
Input Current 10mA, Continuous
Analog I/O to AGND −0.3 to AVDD + 0.3 V
Digital I/O to DGND −0.3 to IOVDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range −40 to +105 °C
Storage Temperature Range −60 to +150 °C
Lead Tem perature (soldering, 10s) +260 °C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(1)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ADS1601 passes standard 200V machine model and 1.5K CDM
testing. ADS1601 passes 1kV human body model testing (TI Standard
is 2kV).
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
2
Signal-to-noise ratio (SNR)
Total harmonic distortion (THD)
Signal-to-noise + distortion (SINAD)
Spurious-free dynamic range (SFDR)
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SBAS322 − DECEMBER 2004
ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
Differential input voltage (VIN)
(AINP − AINN)
Common-mode input voltage (VCM)
(AINP + AINN) / 2
Differential input voltage (VIN)
(AINP or AINN with respect to AGND)
Dynamic Specifications
Data Rate
Signal-to-noise ratio (SNR)
Total harmonic distortion (THD)
Signal-to-noise + distortion (SINAD)
Spurious-free dynamic range (SFDR)
Intermodulation distortion (IMD)
Aperture delay 4 ns
0dBFS ±V
0dBFS −0.1 3.5 V
fIN = 10kHz, −1dBFS 92 dB
fIN = 10kHz, −3dBFS 87 90 dB
fIN = 10kHz, −6dBFS 84 87 dB
fIN = 100kHz, −1dBFS 92 dB
fIN = 100kHz, −3dBFS 87 90 dB
fIN = 100kHz, −6dBFS 84 87 dB
fIN = 500kHz, −1dBFS 91 dB
fIN = 500kHz, −3dBFS 89 dB
fIN = 500kHz, −6dBFS 87 dB
fIN = 10kHz, −1dBFS −91 dB
fIN = 10kHz, −3dBFS −100 −90 dB
fIN = 10kHz, −6dBFS −104 −97 dB
fIN = 100kHz, −1dBFS −88 dB
fIN = 100kHz, −3dBFS −96 −90 dB
fIN = 100kHz, −6dBFS −103 −96 dB
fIN = 500kHz, −1dBFS −115 dB
fIN = 500kHz, −3dBFS −112 dB
fIN = 500kHz, −6dBFS −110 dB
fIN = 10kHz, −1dBFS 88 dB
fIN = 10kHz, −3dBFS 85 89 dB
fIN = 10kHz, −6dBFS 84 87 dB
fIN = 100kHz, −1dBFS 87 dB
fIN = 100kHz, −3dBFS 85 88 dB
fIN = 100kHz, −6dBFS 84 86 dB
fIN = 500kHz, −1dBFS 91 dB
fIN = 500kHz, −3dBFS 89 dB
fIN = 500kHz, −6dBFS 87 dB
fIN = 10kHz, −1dBFS 92 dB
fIN = 10kHz, −3dBFS 91 100 dB
fIN = 10kHz, −6dBFS 98 109 dB
fIN = 100kHz, −1dBFS 88 dB
fIN = 100kHz, −3dBFS 90 97 dB
fIN = 100kHz, −6dBFS 97 105 dB
fIN = 500kHz, −1dBFS 120 dB
fIN = 500kHz, −3dBFS 118 dB
fIN = 500kHz, −6dBFS 115 dB
f1 = 499kHz, −6dBFS
f2 = 501kHz, −6dBFS
= 20MHz, V
CLK
= +3V , VCM = +2.7V , and R
REF
ADS1601
REF
2.7 V
f
CLK
ǒ
1.25
20MHz
94 dB
= 60kΩ,
BIAS
Ǔ
V
MSPS
3
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SBAS322 − DECEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
PARAMETER UNITMAXTYPMINTEST CONDITIONS
Digital Filter Characteristics
Passband 0
Passband ripple ±0.001 dB
−0.1dB attenuation
Passband transition
−3.0dB attentuation
Stop band
Stop band attenuation 75 dB
Group delay
Settling time Complete settling
Static Specifications
Resolution 16 Bits
No missing codes 16 Bits
Input-referred noise 0.5 0.75 LSB, rms
Integral nonlinearity −0.5dBFS signal 0.75 LSB
Differential nonlinearity 0.25 LSB
Offset error −0.05 %FSR
Offset error drift 0.5 ppmFSR/°C
Gain error 0.25 %
Gain error drift Excluding reference drift 10 ppm/°C
Common-mode rejection At DC 75 dB
Power-supply rejection At DC 65 dB
Internal Voltage Reference REFEN = low
V
= (VREFP − VREFN) 2.75 3 3.25 V
REF
VREFP 3.5 3.8 4.1 V
VREFN 0.5 0.8 1.1 V
VMID 2.3 2.4 2.6 V
V
drift 50 ppm/°C
REF
Startup time 15 ms
External Voltage Reference REFEN = High
V
= (VREFP − VREFN) 2.0 3 3.25 V
REF
VREFP 3.5 4 4.25 V
VREFN 0.5 1 1.5 V
VMID 2.3 2.5 2.6 V
= 20MHz, V
CLK
= +3V , VCM = +2.7V , and R
REF
ADS1601
f
CLK
ǒ
575
20MHz
f
CLK
ǒ
615
20MHz
f
CLK
ǒ
20MHz
Ǔ
20MHZ
ǒ
20.8
f
CLK
20MHZ
ǒ
40.8
f
CLK
0.7
= 60kΩ,
BIAS
f
CLK
ǒ
550
20MHz
Ǔ
Ǔ
f
CLK
ǒ
19.3
20MHz
Ǔ
Ǔ
kHz
Ǔ
kHz
kHz
MHz
Ǔ
µs
µs
4
Power dissipation
Power dissipation
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SBAS322 − DECEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
PARAMETER UNITMAXTYPMINTEST CONDITIONS
Clock Input
Frequency (f
Duty Cycle f
Digital Input/Output
V
IH
V
IL
V
OH
V
OL
Input leakage DGND < V
Power-Supply Requirements
AVDD 4.75 5.25 V
DVDD 2.7 3.3 V
IOVDD IOH = 50µA 2.7 5.25 V
AVDD current (I
DVDD current (I
IOVDD current (I
Temperature Range
Specified −40 +85 °C
Operating −40 +105 °C
Storage −60 +150 °C
) 20 MHz
CLK
= 20MHz 45 55 %
CLK
IOH = 50µA IOVDD − 0.5 V
IOL = 50µA DGND + 0.5 V
< IOVDD ±10 µA
DIGIN
)
AVDD
) IOVDD = 3V 15 18 mA
DVDD
) IOVDD = 3V 3 8 mA
IOVDD
REFEN = low 65 77 mA
REFEN = high 55 65 mA
AVDD = 5V, DVDD = 3V,
IOVDD = 3V, REFEN
PD = low, CLK disabled 10 mW
= high
= 20MHz, V
CLK
= +3V , VCM = +2.7V , and R
REF
BIAS
= 60kΩ,
ADS1601
0.7 IOVDD IOVDD V
DGND 0.3 IOVDD V
330 380 mW
5
SBAS322 − DECEMBER 2004
DEFINITIONS
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Absolute Input Voltage
Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.
Aperture Delay
Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.
Common-Mode Input Voltage
Common-mode input voltage (VCM) is the average voltage
of the analog inputs:
(AINP ) AINN)
2
Differential Input Voltage
Differential input voltage (VIN) is the voltage difference
between the analog inputs (AINP−AINN).
Differential Nonlinearity (DNL)
DNL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.
Full-Scale Range (FSR)
FSR is the difference between the maximum and minimum
measurable input signals (FSR = 2V
REF
).
Gain Error
Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.
Gain Error Drift
Gain error drift, given in ppm/_C, is the drift over
temperature of t h e g a i n e r r o r. The gain error is specified as
the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.
Integral Nonlinearity (INL)
INL, given in least-significant bits of the output code (LSB),
is the maximum deviation of the output codes from a best
fit line.
Intermodulation Distortion (IMD)
IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.
Offset Error
Offset Error , given in % of FSR, is the output reading when
the differential input is zero.
Offset Error Drift
Offset error drift, given in ppm of FSR/_C, is the drift over
temperature of the of fset error. The offset error is specified
as the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.
Signal-to-Noise Ratio (SNR)
SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f
/2 (the Nyquist frequency) excluding the first six
CLK
harmonics of the input signal and the dc component.
Signal-to-Noise and Distortion (SINAD)
SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f
/2 (the Nyquist frequency) including the harmonics of
CLK
the input signal but excluding the dc component.
Spurious-Free Dynamic Range (SFDR)
SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.
Total Harmonic Distortion (THD)
THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.
6
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FUNCTION
DESCRIPTION
PIN ASSIGNMENTS
VREFP
VREFP
VMID
VREFN
VREFN
VCAP
AVDD
AGND
CLK
AGND
48 47 46 45 44 43 42 41 40 39 38
SBAS322 − DECEMBER 2004
DGND
IOVDD
TQFP PACKAGE
(TOP VIEW)
AGND
AVDD
AGND
AINN
AINP
AGND
AVDD
RBIAS
AGND
AVDD
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 233724
NC
REFEN
ADS1601
PD
NC
RPULLUP
DVDD
DGND
SYNC
OTR
DVDD
DGND
NC
36
DGND
35
NC
34
DVDD
33
DGND
32
FSO
31
FSO
30
DOUT
29
DOUT
28
SCLK
27
SCLK
26
NC
25
NC
Terminal Functions
TERMINAL
NAME NO.
AGND 1, 3, 6, 9, 11, 39, 41 Analog Analog ground
AVDD 2, 7, 10, 12, 42 Analog Analog supply
AINN 4 Analog input Negative analog input
AINP 5 Analog input Positive analog input
RBIAS 8 Analog Terminal for external analog bias setting resistor.
REFEN 13 Digital input: active low Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
NC 14, 16, 24−26, 35 Do not connect These terminals must be left unconnected.
RPULLUP 15 Digital Input Pull-up to DVDD with 10kΩ resistor (see Figure 50).
PD 17 Digital input: active low Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
DVDD 18, 23, 34 Digital Digital supply
DGND 19, 22, 33, 36, 38 Digital Digital ground
SYNC 20 Digital input Synchronization control input
OTR 21 Digital output Indicates analog input signal is out of range.
SCLK 28 Digital output Serial clock output
SCLK 27 Digital output Serial clock output, complementary signal.
DOUT 30 Digital output Data output
DOUT 29 Digital output Data output, complementary signal.
FSO 32 Digital output Frame synchronization output
FSO 31 Digital output Frame synchronization output, complementary signal.
IOVDD 37 Digital Digital I/O supply
CLK 40 Digital input Clock input
VCAP 43 Analog Terminal for external bypass capacitor connection to internal bias voltage.
VREFN 44, 45 Analog Negative reference voltage
VMID 46 Analog Midpoint voltage
VREFP 47, 48 Analog Positive reference voltage
7
t
Settling time of ADS1601
(1)
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SBAS322 − DECEMBER 2004
TIMING DIAGRAMS
CLK
t
STL
SYNC
FSO
TIMING REQUIREMENTS
For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
SYPW
STL
NOTE: (1) An FSO pulse occuring prior to T
SYNC positive pulse width
t
SYPW
Figure 1. Initialization Timing
≥ 816 CLK period should be ignored.
STL
2 16 CLK periods
51 52 Conversions
816 832 CLK periods
t
DPD
t
CPW
t
CPW
Bit 1 Bit 0 (LSB)Bit 15 (MSB) Bit14
New Data
CLK
FSO
SCLK
DOUT
t
C
t
CF
t
FPW
t
CS
t
DHD
Bit 0 (LSB)
Old Data
Figure 2. Data Retrieval Timing
TIMING REQUIREMENTS
For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
t
CPW
t
CF
t
FPW
t
CS
t
DHD
t
DPD
C
CLK period (1/f
CLK
)
CLK positive or negative pulse width
Rising edge of CLK to rising edge of FSO
FSO positive pulse width
Rising edge of CLK to rising edge of SCLK
SCLK rising edge to old DOUT invalid (hold time)
SCLK rising edge to new DOUT valid (propagation delay)
50 ns
25 ns
15 ns
1 CLK period
15 ns
0 ns
5 ns
8
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