TEXAS INSTRUMENTS ADS1294, ADS1294R Technical data

Control

CLK

GPIOANDCONTROL

Oscillator

SPI

TestSignalsand

Monitors

PACE

SPI

RLD

Wilson

Terminal

WCT

Reference

REF

ADC7

ADC8

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

A7

A8

A1

A2

A3

A4

A5

A6

MUX

INPUTS

¼ ¼

¼

ToChannel

RESP

Resp

RESP

DEMOD

ADS129xR

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ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

用于生物电位测量的低功率，

查询样品

1

特性

23

• 8个低噪音PGA和8个高分辨率ADC(ADS1298, ADS1298R)

• 低功耗：每通道 0.75 mW

• 输入参考噪声：4μVPP(150Hz BW, G = 6)

• 输入偏置电流：200pA

• 数据速率：250SPS至32kSPS

• CMRR：–115dB

• 可编程增益：1，2，3，4，6，8或者12

• 支持AAMI

EC11，EC13，IEC60601-1，IEC60601-2-27，和IEC60601-2-51标准

• 单极或双极电源：

AVDD = 2.7V至5.25V，DVDD = 1.65V至3.6V

• 内置右腿驱动放大器，检测，WCT，PACE检测，

测试信号

• 集成的呼吸阻抗测量（只适用

于ADS1294R/6R/8R）

• 数字PACE检测功能

• 内置振荡器与参考

• 灵活的断电，待机模式

• 串行外设接口(SPI)™- 兼容串口

• 运行温度范围：

–40°C至+85°C

: ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

8通道，24位模拟前端

借助于其高水平的集成和出色的性

能，ADS1294/6/8/4R/6R/8R系列产品可以用大大减小

的尺寸，功率，和总体成本来开发可扩展的医疗仪器。

ADS1294/6/8/4R/6R/8R在每通道上有一个灵活输入复

用器，此复用器可独立连接至用于测试，温度，和持续断线检测的内部生成信号。此外，可选择输入通道的

各种配置生成右腿驱动器 (RLD) 输出信号。 ADS1294/6/8/4R/6R/8R运行数据速率最高可达32KSPS，因此可实现软件PACE检测。可通过上

拉／下拉电阻器或激磁电流源极／汲极为该器件内部实

施持续断线检测。 3个集成的放大器生成标准12引线ECG所需的威尔逊(Wilson)中心终端(WCT)和高德伯格(Goldberger)中心终端(GCT)。 ADS1294R/6R/8R版

本包括一个完全集成的，呼吸阻抗测量功能。

多个ADS1294/6/8/4R/6R/8R器件可使用菊花链配置级

联在高通道数量系统中。

封装选项包括微小型 8mm × 8mm ，64焊球 BGA 与TQFP-64封装。 ADS1294/6/8 BGA版本商用额定温度范围为0°C至+70°C。 ADS1294R/6R/8R BGA 和ADS1294/6/8 TQFP版本工业用额定温度范围是–40°C至+85°C。

应用范围

• 医疗仪器（ECG，EMG和EEG）

病人监护：动态心电图，事件，压力，和包括ECG，AED在内的重要生命体征信号，远程医疗双谱指数(BIS)，诱发音频电位(EAP)，睡眠监护仪

• 高精度，同步，多通道信号采集

说明

ADS1294/6/8/4R/6R/8R是多通道，同步采样，24位，三角积分(ΔΣ)模数转换器(ADC)系列产品，此产品具有内置的可编程增益放大器(PGA)，内部基准，和一个板载振荡器。 ADS1294/6/8/4R/6R/8R包含了所有医疗心电图(ECG)和脑电图(EEG)应用所通常要求的所有特

性。

1

2串行外设接口(SPI) is a trademark of Motorola. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not English Data Sheet: SBAS459 necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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FAMILY AND ORDERING INFORMATION

PRODUCT OPTION CHANNELS RESOLUTION (kSPS) RANGE CIRCUITRY

ADS1194

ADS1196

ADS1198

ADS1294 BGA 4 24 32 0°C to +70°C External

ADS1294R BGA 4 24 32 –40°C to +85°C Yes

ADS1294 TQFP 4 24 32 –40°C to +85°C External ADS1296 BGA 6 24 32 0°C to +70°C External

ADS1296R BGA 6 24 32 –40°C to +85°C Yes

ADS1296 TQFP 6 24 32 –40°C to +85°C External ADS1298 BGA 8 24 32 0°C to +70°C External

ADS1298R BGA 8 24 32 –40°C to +85°C Yes

ADS1298 TQFP 8 24 32 –40°C to +85°C External

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

PACKAGE NUMBER OF ADC SAMPLE RATE TEMPERATURE RESPIRATION

BGA 4 16 8 0°C to +70°C No

TQFP 4 16 8 0°C to +70°C No

BGA 6 16 8 0°C to +70°C No

TQFP 6 16 8 0°C to +70°C No

BGA 8 16 8 0°C to +70°C No

TQFP 8 16 8 0°C to +70°C No

(1)

MAXIMUM OPERATING

(1)

Over operating free-air temperature range, unless otherwise noted.

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

AVDD to AVSS –0.3 to +5.5 V DVDD to DGND –0.3 to +3.9 V AVSS to DGND –3 to +0.2 V V

input to AVSS AVSS – 0.3 to AVDD + 0.3 V

REF

Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V Digital output voltage to DGND –0.3 to DVDD + 0.3 V Input current (momentary) 100 mA Input current (continuous) 10 mA

Operating temperature range

ESD ratings

Storage temperature range –60 to +150 °C Maximum junction temperature (TJ) +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

Commerical Grade: ADS1294, ADS1296, ADS1298 0 to +70 °C Industrial grade: ADS1294I, ADS1296I, ADS1298I,

ADS1294RI, ADS1296RI, ADS1298RI Human body model (HBM)

JEDEC standard 22, test method A114-C.01, all pins Charged device model (CDM)

JEDEC standard 22, test method C101, all pins

–40 to +85 °C

±2000 V

±500 V

UNIT

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V V

= 2.4V, external f

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale differential input voltage (AINP – AINN) ±V

Input common-mode range subsection of the PGA Settings and Input

Input capacitance 20 pF

Input bias current TA= 0°C to +70°C, input = 1.5V ±1 nA

DC input impedance Current source lead-off detection 500 MΩ

PGA PERFORMANCE

Gain settings 1, 2, 3, 4, 6, 8, 12 Bandwidth See Table 6

ADC PERFORMANCE

Resolution 16kSPS data rate 19 Bits

Data rate

CHANNEL PERFORMANCE

DC Performance

Input-referred noise

Integral nonlinearity ADS1294R/6R/8R channel 1

Offset error ±500 µV Offset error drift 2 µV/°C Gain error Excluding voltage reference error ±0.2 ±0.5 % of FS Gain drift Excluding voltage reference drift 5 ppm/°C Gain match between channels 0.3 % of FS

(1) Performance is applicable for 5V operation as well. Production testing for limits is performed at 3V. (2) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted

(without electrode resistance) over a 10-second interval.

= 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

CLK

TA= +25°C, input = 1.5V ±200 pA

TA= –40°C to +85°C, input = 1.5V ±1.2 nA No lead-off 1000 MΩ

Pull-up resistor lead-off detection 10 MΩ

Data rates up to 8kSPS, no missing codes 24 Bits

32kSPS data rate 17 Bits f

= 2.048MHz, High-Resolution mode 500 32000 SPS

CLK

f

= 2.048MHz, Low-Power mode 250 16000 SPS

CLK

(2)

Gain = 6 Gain = 6, 256 points, 0.5 seconds of data 4 7 μV Gain settings other than 6, data rates other

than 500SPS Full-scale with gain = 6, best fit 8 ppm Full-scale with gain = 6, best fit,

–20dBFS with gain = 6, best fit, ADS1294R/6R/8R channel 1

, 10 seconds of data 5 μV

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

(1)

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

/GAIN V

REF

See the Input Common-Mode Range

Range section

See Noise Measurements section

40 ppm

8 ppm

,

PP PP

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V V

= 2.4V, external f

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CHANNEL PERFORMANCE (continued)

AC Performance

Common-mode rejection ratio (CMRR) fCM= 50Hz, 60Hz Power-supply rejection ratio (PSRR) fPS= 50Hz, 60Hz 90 dB Crosstalk fIN= 50Hz, 60Hz –126 dB Signal-to-noise ratio (SNR) fIN= 10Hz input, gain = 6 112 dB

Total harmonic distortion (THD)

DIGITAL FILTER

–3dB bandwidth 0.262f Digital filter settling Full setting 4 Conversions

RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS

RLD integrated noise BW = 150Hz 7 μV PACE integrated noise BW = 8kHz 20 µV PACE amplifier crosstalk Crosstalk between PACE amplifiers 60 dB Gain bandwidth product 50kΩ || 10pF load, gain = 1 100 kHz Slew rate 50kΩ || 10pF load, gain = 1 0.25 V/μs

PACE and RLD amplifier drive strength

PACE and RLD current

PACE amplifier output resistance 100 Ω Total harmonic distortion fIN= 100Hz, gain = 1 –70 dB Common-mode input range AVSS + 0.7 AVDD – 0.3 V Common-mode resistor matching Internal 200kΩ resistor matching 0.1 % Short-circuit current ±0.25 mA Quiescent power consumption Either RLD or PACE amplifier 20 μA

WILSON CENTRAL TERMINAL (WCT) AMPLIFIER

Integrated noise BW = 150Hz See Table 5 nV/√Hz Gain bandwidth product See Table 5 kHz Slew rate See Table 5 V/s Total harmonic distortion fIN= 100Hz 90 dB Common-mode input range AVSS + 0.3 AVDD – 0.3 V Short-circuit current Through internal 30kΩ resistor ±0.25 mA Quiescent power consumption See Table 5 μA

(3) CMRR is measured with a common-mode signal of AVSS + 0.3V to AVDD – 0.3V. The values indicated are the maximum of the eight

channels.

(4) Harmonics above the second harmonic are attenuated by the digital filter.

= 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

CLK

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

(3)

10Hz, –0.5dBFs –98 dB ADS1294R/6R/8R channel 1, 10Hz, –0.5dBFs –70 dB 100Hz, –0.5dBFs ADS1294R/6R/8R channel 1,

100Hz, –0.5dBFs ADS1294R/6R/8R channel 1,

100Hz, –20dBFs

Short-circuit to GND (AVDD = 3V) 270 μA Short-circuit to supply (AVDD = 3V) 550 μA Short-circuit to GND (AVDD = 5V) 490 μA Short-circuit to supply (AVDD = 5V) 810 μA Peak swing (AVSS + 0.3V to AVDD + 0.3V)

at AVDD = 3V Peak swing (AVSS + 0.3V to AVDD + 0.3V)

at AVDD = 5V

(4)

–105 –115 dB

–100 dB

–68 dB

–86 dB

DR

50 μA

75 μA

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(1)

,

Hz

RMS RMS

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V V

= 2.4V, external f

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LEAD-OFF DETECT

Frequency See the Register Map section for settings 0, fDR/4 kHz Current See the Register Map section for settings 6, 12, 18, 24 nA Current accuracy ±20 % Comparator threshold accuracy ±30 mV

RESPIRATION (ADS1294R/6R/8R Only)

Frequency

Phase shift See the Register Map section for settings 22.5 90 157.5 Degrees Impedance range I

Impedance measurement noise 20 mΩ

Modulator current 29 µA

EXTERNAL REFERENCE

Reference input voltage

Negative input (VREFN) AVSS V Positive input (VREFP) AVSS + 2.5 V Input impedance 10 kΩ

INTERNAL REFERENCE

Output voltage

V

accuracy ±0.2 %

REF

Internal reference drift Commerical grade, 0°C to +70°C 35 ppm

Start-up time 150 ms

SYSTEM MONITORS

Analog supply reading error 2 % Digital supply reading error 2 %

Device wake up

Temperature sensor reading, voltage TA= +25°C 145 mV Temperature sensor reading, coefficient 490 μV/°C

Test Signal

Signal frequency See Register Map section for settings Hz Signal voltage See Register Map section for settings ±1, ±2 mV Accuracy ±2 %

= 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

CLK

Internal source 32, 64 kHz External source 32 64 kHz

= 30μA 10 kΩ

RESP

0.05Hz to 2Hz brick wall filter, 32kHz modulation clock, phase = 112.5, using I gain = 4 test condition

internal reference, signal path = 82kΩ, baseline = 2.21kΩ

3V supply V 5V supply V

Register bit CONFIG3.VREF_4V = 0, AVDD ≥ 2.7V

Register bit CONFIG3.VREF_4V = 1, AVDD ≥ 4.4V

TA= +25°C 35 ppm/°C

Industrial grade, –40°C to +85°C 45 ppm

From power-up to DRDY low 150 ms STANDBY mode 9 ms

= 30μA with 2kΩ baseline load,

RESP

= (VREFP – VREFN) 2.5 V

REF

= (VREFP – VREFN) 4.0 V

REF

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

2.4 V

4.0 V

CLK

20

/2

f

/221, f

CLK

(1)

,

PP

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V V

= 2.4V, external f

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLOCK

Internal oscillator clock frequency Nominal frequency 2.048 MHz

Internal clock accuracy

Internal oscillator start-up time 20 μs Internal oscillator power consumption 120 μW External clock input frequency CLKSEL pin = 0 1.94 2.048 2.25 MHz

DIGITAL INPUT/OUTPUT (DVDD = 1.65V to 3.6V)

Logic level

V

IH

V

IL

V

OH

V

OL

Input current (IIN) 0V < V

POWER-SUPPLY REQUIREMENTS

Analog supply (AVDD – AVSS) 2.7 3.0 5.25 V Digital supply (DVDD) 1.65 1.8 3.6 V AVDD – DVDD –2.1 3.6 V

SUPPLY CURRENT (RLD, WCT, and PACE Amplifiers Turned Off)

High-Resolution mode (ADS1298)

I

AVDD

I

DVDD

Low-Power mode (ADS1298)

I

AVDD

I

DVDD

POWER DISSIPATION (Analog Supply = 3V, RLD, WCT, and PACE Amplifiers Turned Off)

Quiescent power dissipation

ADS1298/8R

ADS1296/6R

ADS1294/4R

Power-down 10 μW Standby mode 2 mW Quiescent channel power PGA + ADC 818 μW

= 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

CLK

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

TA= +25°C ±0.5 % 0°C ≤ TA≤ +70°C ±2 % –40°C ≤ TA≤ +85°C,

ADS1298I industrial grade version only

0.8DVDD DVDD + 0.1 V –0.1 0.2DVDD V

IOH= –500μA DVDD – 0.4 V IOL= +500μA 0.4 V

< DVDD –10 +10 μA

DigitalInput

AVDD – AVSS = 3V 2.75 mA AVDD – AVSS = 5V 3.1 mA DVDD = 3.0V 0.5 mA DVDD = 1.8V 0.3 mA

AVDD – AVSS = 3V 1.8 mA AVDD – AVSS = 5V 2.1 mA DVDD = 3.0V 0.5 mA DVDD = 1.8V 0.3 mA

High-Resolution mode 8.8 9.5 mW Low-Power mode (250SPS) 6.0 7.0 mW High-Resolution mode 7.2 7.9 mW Low-Power mode 5.3 6.6 mW High-Resolution mode 5.4 6 mW Low-Power mode 4.1 4.4 mW

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±2.5 %

(1)

,

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V V

= 2.4V, external f

REF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER DISSIPATION (Analog Supply = 5V, RLD, WCT, and PACE Amplifiers Turned Off)

Quiescent power dissipation

ADS1298/8R

ADS1296/6R

ADS1294/4R

Power-down 20 μW Standby mode 4 mW Quiescent channel power PGA + ADC 1.5 mW

TEMPERATURE

Specified temperature range 0 +70 °C Operating temperature range 0 +70 °C Specified temperature range

(industrial grade only) Operating temperature range

(industrial grade only) Storage temperature range –60 +150 °C

= 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

CLK

High-Resolution mode 17.5 mW Low-Power mode 12.5 mW High-Resolution mode 14.1 mW Low-Power mode 10 mW High-Resolution mode 10.1 mW Low-Power mode 8.3 mW

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

ADS1294, ADS1296, ADS1298

ADS1294R, ADS1296R, ADS1298R

–40 +85 °C

(1)

,

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

NOISE MEASUREMENTS

NOTE

The ADS1294R/6R/8R channel performance differs from the ADS1294/6/8 in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R.

The ADS129x noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 and

Table 2 summarize the noise performance of the ADS129x in the High-Resolution (HR) mode and Low-Power

(LP) mode, respectively, with a 3V analog power supply. Table 3 and Table 4 summarize the noise performance of the ADS129x in the HR mode and LP mode, respectively, with a 5V analog power supply. The data are representative of typical noise performance at TA= +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. Thus, the ratio between rms noise and peak-to-peak noise is approximately 10. For the lower data rates, the ratio is approximately 6.6.

Table 1 to Table 4 show measurements taken with an internal reference. The data are also representative of the

ADS129x noise performance when using a low-noise external reference such as the REF5025.

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Table 1. Input-Referred Noise (μV

3V Analog Supply and 2.4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12

000 32000 8398 335/3553 168/1701 112/1100 85/823 58/529 42.5/378 28.6/248 001 16000 4193 56/613 28/295 18.8/188 14.3/143 9.7/94 7.4/69 5.2/44.3 010 8000 2096 12.4/111 6.5/54 4.5/37.9 3.5/29.7 2.6/21.7 2.2/17.8 1.8/13.8 011 4000 1048 6.1/44.8 3.2/23.3 2.4/17.1 1.9/14.0 1.5/11.1 1.3/9.7 1.2/8.5 100 2000 524 4.1/27.8 2.2/15.4 1.6/11.0 1.3/9.1 1.1/7.3 1.0/6.5 0.9/6.0 101 1000 262 2.9/19.0 1.6/10.1 1.2/7.5 1.0/6.2 0.8/5.0 0.7/4.6 0.6/4.1 110 500 131 2.1/12.5 1.1/6.8 0.9/5.1 0.7/4.3 0.6/3.5 0.5/3.1 0.5/2.9

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (μV

3V Analog Supply and 2.4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12

000 16000 4193 333/3481 166/1836 111/1168 84/834 56/576 42/450 28/284 001 8000 2096 56/554 28/272 19/177 14.3/133 9.7/85 7.4/64 5.0/42.4 010 4000 1048 12.5/99 6.5/51 4.5/35.0 3.4/25.9 2.4/18.8 2.0/14.5 1.5/11.3 011 2000 524 6.1/41.8 3.2/22.2 2.3/15.9 1.8/12.1 1.4/9.3 1.2/7.8 1.0/6.7 100 1000 262 4.1/26.3 2.2/14.6 1.6/9.9 1.3/8.1 1.0/6.2 0.8/5.4 0.7/4.7 101 500 131 3.0/17.9 1.6/9.8 1.1/6.8 0.9/5.7 0.7/4.2 0.6/3.6 0.5/3.4 110 250 65 2.1/11.9 1.1/6.3 0.8/4.6 0.7/4.0 0.5/3.0 0.5/2.6 0.4/2.4

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

/μVPP) in High-Resolution Mode

RMS

/μVPP) in Low-Power Mode

RMS

(1)

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ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Table 3. Input-Referred Noise (μV

5V Analog Supply and 4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12

000 32000 8398 521/5388 260/2900 173/1946 130/1403 87/917 65/692 44/483 001 16000 4193 86/1252 43/633 29/402 22/298 15/206 11/141 7/91 010 8000 2096 17/207 9/112 6/71 4/57 3/36 3/29 2/18 011 4000 1048 6.4/48.2 3.4/25.9 2.417.7 1.9/15.4 1.5/11.2 1.3/9.6 1.1/8.2 100 2000 524 4.2/29.9 2.3/15.9 1.6/11.1 1.3/9.3 1.0/7.5 0.9/6.6 0.8/5.8 101 1000 262 2.9/18.8 1.6/10.4 1.1/7.8 0.9/6.1 0.7/4.9 0.6/4.7 0.6/3.9 110 500 131 2.0/12.8 1.1/7.2 0.8/5.2 0.7/4.0 0.5/3.3 0.5/3.3 0.4/2.7

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (μV

5V Analog Supply and 4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

REGISTER (SPS) (Hz) GAIN = 1 GAIN = 2 GAIN = 3 GAIN = 4 GAIN = 6 GAIN = 8 GAIN = 12

000 16000 4193 526/5985 263/2953 175/1918 132/1410 88/896 66/681 44/458 001 8000 2096 88/1201 44/619 29/411 22/280 15/191 11/139 7/83 010 4000 1048 17/208 9/103 6/62 4/52 3/37 2/25 2/16 011 2000 524 6.0/41.1 3.3/23.3 2.2/15.5 1.8/12.3 1.3/9.8 1.1/7.8 0.9/6.5 100 1000 262 4.1/27.1 2.3/14.8 1.5/10.1 1.2/8.1 0.9/6.0 0.8/5.4 0.7/4.4 101 500 131 2.9/17.4 1.6/9.6 1.1/6.6 0.9/5.9 0.7/4.3 0.6/3.4 0.5/3.2 110 250 65 2.1/11.9 1.1/6.6 0.8/4.6 0.6/3.7 0.5/3.0 0.4/2.5 0.4/2.2

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

/μVPP) in High-Resolution Mode

RMS

/μVPP) in Low-Power Mode

RMS

(1)

Table 5. Typical WCT Performance

ANY ONE ANY TWO ALL THREE

PARAMETER (A, B, or C) (A+B, A+C, or B+C) (A+B+C) UNIT

Integrated noise 540 382 312 nV

Power 53 59 65 μW –3dB BW 30 59 89 kHz Slew rate BW limited BW limited BW limited —

RMS

1

2

3

4

5

6

7

8

H

G

F

E

D

C

B

A

IN8P

IN7P

IN6PIN5P

IN4P

IN3P

IN2PIN1P

IN8N

IN7N

IN6NIN5N

IN4N

IN3N

IN2NIN1N

RLDIN

RLDOUT

RLDINV

WCT

TESTP_

PACE_OUT1

TESTN_

PACE_OUT2

VCAP4

VREFP

AVDDAVDDRLDREF

AVSSRESV1

RESP_ MODN

RESP_

MODP

VREFN

AVSSAVSSAVSSAVSS

GPIO4GPIO1

PWDN

VCAP1

AVDDAVDDAVDD

DRDY

GPIO3

DAISY_IN

RESET

VCAP2

AVDD1

VCAP3DGNDDGNDGPIO2

CS

START

DGND

AVSS1

CLKSEL

DVDD

DVDDDOUTSCLKCLK

DIN

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)

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PIN CONFIGURATIONS

ZXG PACKAGE

BGA-64

(1) Connect unused terminals to AVDD.

NAME TERMINAL FUNCTION DESCRIPTION

(1)

IN8P

(1)

IN7P

(1)

IN6P

(1)

IN5P

(1)

IN4P

(1)

IN3P

(1)

IN2P

(1)

IN1P

(1)

IN8N

(1)

IN7N

(1)

IN6N

(1)

IN5N

(1)

IN4N

(1)

IN3N

(1)

IN2N

(1)

IN1N

BGA PIN ASSIGNMENTS

1A Analog input Differential analog positive input 8 (ADS1298/8R) 1B Analog input Differential analog positive input 7 (ADS1298/8R) 1C Analog input Differential analog positive input 6 (ADS1296/8/6R/8R) 1D Analog input Differential analog positive input 5 (ADS1296/8/6R/8R) 1E Analog input Differential analog positive input 4

1F Analog input Differential analog positive input 3 1G Analog input Differential analog positive input 2 1H Analog input Differential analog positive input 1 2A Analog input Differential analog negative input 8 (ADS1298/8R) 2B Analog input Differential analog negative input 7 (ADS1298/8R) 2C Analog input Differential analog negative input 6 (ADS1296/8/6R/8R) 2D Analog input Differential analog negative input 5 (ADS1296/8/6R/8R) 2E Analog input Differential analog negative input 4

2F Analog input Differential analog negative input 3 2G Analog input Differential analog negative input 2 2H Analog input Differential analog negative input 1

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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BGA PIN ASSIGNMENTS (continued)

NAME TERMINAL FUNCTION DESCRIPTION

(2)

RLDIN

RLDOUT 3B Analog output Right leg drive output

RLDINV 3C Analog input/output Right leg drive inverting input

WCT 3D Analog output Wilson Central Terminal output TESTP_PACE_OUT1 TESTN_PACE_OUT2

VCAP4 3G Analog output Analog bypass capacitor VREFP 3H Analog input/output Positivereference voltage

AVDD 4A Supply Analog supply AVDD 4B Supply Analog supply

RLDREF 4C Analog input Right leg drive noninverting input

AVSS 4D Supply Analog ground

RESV1 4E Digital input Reserved for future use; must tie to logic low (DGND).

RESP_MODN 4F Analog output side.

RESP_MODP 4G Analog output side.

VREFN 4H Analog input Negative reference voltage

AVSS 5A Supply Analog ground AVSS 5B Supply Analog ground AVSS 5C Supply Analog ground

AVSS 5D Supply Analog ground GPIO4 5E Digital input/output GPIO4 in normal mode GPIO1 5F Digital input/output General purpose input/output pin PWDN 5G Digital input Power-down; active low

VCAP1 5H Analog input/output Analog bypass capacitor

AVDD 6A Supply Analog supply AVDD 6B Supply Analog supply AVDD 6C Supply Analog supply DRDY 6D Digital output Data ready; active low

GPIO3 6E Digital input/output GPIO3 in normal mode

DAISY_IN 6F Digital input Daisy-chain input; if not used, short to DGND.

RESET 6G Digital input System reset; active low VCAP2 6H — Analog bypass capacitor AVDD1 7A Supply Analog supply for charge pump VCAP3 7B — Analog bypass capacitor; internally generated AVDD + 1.9V.

DGND 7C Supply Digital ground DGND 7D Supply Digital ground

GPIO2 7E Digital input/output General-purpose input/output pin

CS 7F Digital input SPI chip select; active low

START 7G Digital input Start conversion

DGND 7H Supply Digital ground

AVSS1 8A Supply Analog ground for charge pump

CLKSEL 8B Digital input Master clock select

DVDD 8C Supply Digital power supply DVDD 8D Supply Digital power supply DOUT 8E Digital output SPI data out

SCLK 8F Digital input SPI clock

CLK 8G Digital input/output External Master clock input or internal clock output. DIN 8H Digital input SPI data in

(2) (2)

(2) Connect unused terminals to AVDD.

3A Analog input Right leg drive input to MUX

3E Analog input/buffer output Internal test signal/single-ended buffer output based on register settings

3F Analog input/output Internal test signal/single-ended buffer output based on register settings

ADS1294R/6R/8R: modulation clock for respiration measurement, negative ADS1294/6/8: leave floating.

ADS1294R/6R/8R: modulation clock for respiration measurement, positive ADS1294/6/8: leave floating.

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DVDD

GPIO4

GPIO3

GPIO2

DOUT

GPIO1

DAISY_IN

SCLK

START

CLK

DIN

DGND

DRDY

CS

RESET

PWDN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

IN8N

IN8P

IN7N

IN7P

IN6N

IN6P

IN5N

IN5P

IN4N

IN4P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

WCT

RLDOUT

RLDIN

RLDINV

RLDREF

AVDD

AVSS

AVDD

VCAP3

AVDD1

AVSS1

CLKSEL

DGND

DVDD

DGND

TESTP_PACE_OUT1

TESTN_PACE_OUT2

AVDD

AVSS

AVDD

AVSS

VREFP

VREFN

VCAP4

NC

VCAP1

NC

VCAP2

RESV1

AVSS

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

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PAG PACKAGE

TQFP-64

(TOP VIEW)

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ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

PAG PIN ASSIGNMENTS

NAME PIN FUNCTION DESCRIPTION

(1)

IN8N

(1)

IN8P

(1)

IN7N

(1)

IN7P

(1)

IN6N

(1)

IN6P

(1)

IN5N

(1)

IN5P

(1)

IN4N

(1)

IN4P

(1)

IN3N

(1)

IN3P

(1)

IN2N

(1)

IN2P

(1)

IN1N

(1)

IN1P

TESTP_PACE_OUT1 TESTN_PACE_OUT2

(1) (1)

AVDD 19 Supply Analog supply

AVSS 20 Supply Analog ground

AVDD 21 Supply Analog supply AVDD 22 Supply Analog supply

AVSS 23 Supply Analog ground

VREFP 24 Analog input/output Positive reference voltage VREFN 25 Analog input Negative reference voltage VCAP4 26 Analog output Analog bypass capacitor

NC 27 — No connection

VCAP1 28 — Analog bypass capacitor

NC 29 — No connection VCAP2 30 — Analog bypass capacitor RESV1 31 Digital input Reserved for future use; must tie to logic low (DGND).

AVSS 32 Supply Analog ground

DGND 33 Supply Digital ground

DIN 34 Digital input SPI data in

PWDN 35 Digital input Power-down; active low

RESET 36 Digital input System reset; active low

CLK 37 Digital input/output External Master clock input or internal clock output.

START 38 Digital input Start conversion

CS 39 Digital input SPI chip select; active low

SCLK 40 Digital input SPI clock

DAISY_IN 41 Digital input Daisy-chain input; if not used, short to DGND.

GPIO1 42 Digital input/output General-purpose input/output pin

DOUT 43 Digital output SPI data out GPIO2 44 Digital input/output General-purpose input/output pin GPIO3 45 Digital input/output General-purpose input/output pin GPIO4 46 Digital input/output General-purpose input/output pin

DRDY 47 Digital output Data ready; active low

DVDD 48 Supply Digital power supply

DGND 49 Supply Digital ground

DVDD 50 Supply Digital power supply

1 Analog input Differential analog negative input 8 (ADS1298) 2 Analog input Differential analog positive input 8 (ADS1298) 3 Analog input Differential analog negative input 7 (ADS1298) 4 Analog input Differential analog positive input 7 (ADS1298) 5 Analog input Differential analog negative input 6 (ADS1296/8) 6 Analog input Differential analog positive input 6 (ADS1296/8) 7 Analog input Differential analog negative input 5 (ADS1296/8) 8 Analog input Differential analog positive input 5 (ADS1296/8)

9 Analog input Differential analog negative input 4 10 Analog input Differential analog positive input 4 11 Analog input Differential analog negative input 3 12 Analog input Differential analog positive input 3 13 Analog input Differential analog negative input 2 14 Analog input Differential analog positive input 2 15 Analog input Differential analog negative input 1 16 Analog input Differential analog positive input 1 17 Analog input/buffer output Internal test signal/single-ended buffer output based on register settings 18 Analog input/output Internal test signal/single-ended buffer output based on register settings

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

(1) Connect unused terminals to AVDD.

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

PAG PIN ASSIGNMENTS (continued)

NAME PIN FUNCTION DESCRIPTION

DGND 51 Supply Digital ground

CLKSEL 52 Digital input Master clock select

AVSS1 53 Supply Analog ground AVDD1 54 Supply Analog supply VCAP3 55 Analog Analog bypass capacitor; internally generated AVDD + 1.9V.

AVDD 56 Supply Analog supply

AVSS 57 Supply Analog ground AVSS 58 Supply Analog ground

AVDD 59 Supply Analog supply

RLDREF 60 Analog input Right leg drive noninverting input

RLDINV 61 Analog input/output Right leg drive inverting input

(1)

RLDIN

RLDOUT 63 Analog output Right leg drive output

WCT 64 Analog output Wilson Central Terminal output

62 Analog input Right leg drive input to MUX

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1

CS

SCLK

DIN

DOUT

2

3 8

1 2

83

t

CSSC

t

DIST

t

DIHD

t

DOHD

t

CSH

t

DOPD

t

SPWH

t

SPWL

t

SCCS

Hi-Z

t

CSDOZ

t

CSDOD

Hi-Z

t

SCLK

t

SDECODE

CLK

t

CLK

D ISY_INA

DOUT

SCLK

MSB

D1

t

DISCK2ST

MSB

21

3 216

217

218

MSB

D1

LSB

t

DISCK2HT

t

DOPD

Don’tCare

LSB

D1

219

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TIMING CHARACTERISTICS

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Figure 1. Serial Interface Timing

NOTE: Daisy-chain timing shown for eight-channel ADS1298, ADS1298R, and ADS1298I.

Figure 2. Daisy-Chain Interface Timing

Timing Requirements For Figure 1 and Figure 2

Specifications apply from –40°C to +85°C, unless otherwise noted. Load on D

PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT

t

CLK

t

CSSC

t

SCLK

t

SPWH, L

t

DIST

t

DIHD

t

DOHD

t

DOPD

t

CSH

t

CSDOD

t

SCCS

t

SDECODE

t

CSDOZ

t

DISCK2ST

t

DISCK2HT

Master clock period 414 514 414 514 ns CS low to first SCLK, setup time 6 17 ns SCLK period 50 66.6 ns SCLK pulse width, high and low 15 25 ns DIN valid to SCLK falling edge: setup time 10 10 ns Valid DIN after SCLK falling edge: hold time 10 11 ns SCLK falling edge to invalid DOUT: hold time 10 10 ns SCLK rising edge to DOUT valid: setup time 17 32 ns CS high pulse 2 2 t CS low to DOUT driven 10 20 ns Eighth SCLK falling edge to CS high 4 4 t Command decode time 4 4 t CS high to DOUT Hi-Z 10 20 ns DAISY_IN valid to SCLK rising edge: setup time 10 10 ns DAISY_IN valid after SCLK rising edge: hold time 10 10 ns

= 20pF || 100kΩ.

OUT

2.7V ≤ DVDD ≤ 3.6V 1.65V ≤ DVDD ≤ 2V

CLKs

CLKs CLKs

3

2

1

0

1

2

3

-

Time(sec)

Input-ReferredNoise( V)m

1 20 103 4 5 6 7 8 9

Peak-to-PeakOver10sec=5 Vm

1600

1400

1200

1000

800

600

400

200

0

Input-ReferredNoise( V)m

Occurrences

-2.88

-2.35

-1.85

-1.35

-0.84

-0.34

0.17

1.17

2.18

0.67

1.68

2.408

2.406

2.404

2.402

2.4

2.398

2.396

-40

85

Temperature( C)°

InternalReference(V)

-15 10

6035

-130

125

120

115

110

105

100

95

90

85

-

10

1k

Frequency(Hz)

Common-ModeRejectionRatio(dB)

100

Gain=1

DataRate=4kSPS AIN=AVDD 0.3VtoAVSS+0.3V-

Gain=2 Gain=3 Gain=4 Gain=6 Gain=8 Gain=12

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

0.3

4.8

InputVoltage(V)

InputLeakageCurrent(nA)

2.3

AVDD AVSS=5V PGA=1

-

1.81.30.8 2.8 3.3 3.8 4.3

1200

1000

800

600

400

200

0

-40

85

Temperature( C)°

LeakageCurrent(pA)

3510-15 60

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

TYPICAL CHARACTERISTICS

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock =

2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

INPUT-REFERRED NOISE NOISE HISTOGRAM

Figure 3. Figure 4.

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INTERNAL REFERENCE vs TEMPERATURE CMRR vs FREQUENCY

Figure 5. Figure 6.

LEAKAGE CURRENT vs INPUT VOLTAGE LEAKAGE CURRENT vs TEMPERATURE

Figure 7. Figure 8.

110

105

100

95

90

85

80

75

70

10

1k

Frequency(Hz)

Power-SupplyRejectionRatio(dB)

100

DataRate=4kSPS

Gain=2

Gain=4

Gain=1

Gain=12

Gain=3

Gain=8

Gain=6

-105

100

95

90

85

80

75

70

-

10

1k

Frequency(Hz)

TotalHarmonicDistortion(dB)

100

DataRate=4kSPS AIN=0.5dBFS

Gain=1

Gain=2

Gain=4

Gain=12

Gain=3

Gain=8

Gain=6

8

6

4

2

0

2

4

6

8

-

-1

1

InputRange(NormalizedtoFull-Scale)

IntegralNonlinearity(ppm)

-0.5

0.50

-40 C°

-20 C°

0 C° +25 C° +40 C° +60 C°

+70 C° +85 C°

10

8

6

4

2

0

2

4

6

8

10

-

Input(NormalizedtoFull-Scale)

IntegralNonlinearity(ppm)

-0.8-1.0 1.0-0.2 0.2 0.6-0.6 0.8-0.4 0 0.4

Gain=6 Gain=8 Gain=12

Gain=1 Gain=2 Gain=3 Gain=4

0

20

40

60

80

100

120

140

160

180

-

Frequency(Hz)

Amplitude(dBFS)

500 250100 150 200

PGAGain=1

THD= 102dB

SNR=115dB f =500SPS

f =ExternalClock

-

DR

CLK

0

20

40

60

80

100

120

140

160

180

-

Frequency(kHz)

Amplitude(dBFS)

20 164 6 8

PGAGain=6

THD= 104dB

SNR=74.5dB

-

f =32kSPS

DR

10 12 14

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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TYPICAL CHARACTERISTICS (continued)

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock =

2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

PSRR vs FREQUENCY THD vs FREQUENCY

Figure 9. Figure 10.

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

INL vs PGA GAIN INL vs TEMPERATURE

Figure 11. Figure 12.

THD FFT PLOT FFT PLOT

(60Hz Signal) (60Hz Signal)

Figure 13. Figure 14.

800

700

600

500

400

300

200

100

0

1

12

PGAGain

Offset( V)m

8642 109753 11

70

60

50

40

30

20

10

0

-0.53

Error(%)

NumberofBins

-0.41

-0.18

0.06

0.30

0.54

0.66

0.42

0.18

-0.06

-0.29

DataFrom31Devices,TwoLots

80

70

60

50

40

30

20

10

0

-20

ThresholdError(mV)

NumberofBins

-15

0

10

20

30

35

25

15

5

-10

DataFrom31Devices,TwoLots

120

100

80

60

40

20

0

-2.70

ErrorinCurrentMagnitude(nA)

NumberofBins

-2.14

-1.01

0.12

1.24

2.37

2.93

1.80

0.68

-0.45

-1.57

DataFrom31Devices,TwoLots CurrentSetting=24nA

17.5

15.5

13.5

11.5

9.5

7.5

5.5

3.5

1.5

Number of Channels Disabled

Power (mW)

10 84 62 3 5 7

AVDD = 3V AVDD = 5V

40

30

20

10

0

10

20

30

40

50

-

InputRange(NormalizedtoFull-Scale)

IntegralNonlinearity(ppm)

-0.8-1 1-0.2 0.2-0.6 -0.4 0 0.4 0.80.6

Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 Channel8

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

TYPICAL CHARACTERISTICS (continued)

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock =

2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

OFFSET vs PGA GAIN

(ABSOLUTE VALUE) TEST SIGNAL AMPLITUDE ACCURACY

Figure 15. Figure 16.

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LEAD-OFF COMPARATOR THRESHOLD ACCURACY DISTRIBUTION

LEAD-OFF CURRENT SOURCE ACCURACY

Figure 17. Figure 18.

ADS1294R/6R/8R NONLINEARITY ADS1298/8R CHANNEL POWER

Figure 19. Figure 20.

110

105

100

95

90

85

80

75

70

65

60

Channel

TotalHarmonicDistortion(dBc)

1 84 62 3 5 7

f =10Hz, 0.5dBFS-

IN

120

110

100

90

80

70

60

50

InputAmplitude(dBFS)

Signal-to-NoiseRatio(dB)

-50

-60 -0.5-20 -5-40 -30 -12 -2

InternalMasterClock,AVDD=3V

ExternalMasterClock,AVDD=3V ExternalMasterClock,AVDD=5V

InternalMasterClock,AVDD=5V

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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TYPICAL CHARACTERISTICS (continued)

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock =

2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

ADS129xR THD (10Hz Sine Wave)

Figure 21. Figure 22.

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

SNR vs INPUT AMPLITUDE

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

OVERVIEW

NOTE

The ADS1294R/6R/8R channel performance differs from the ADS1294/6/8 in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R.

The ADS129x are low-power, multichannel, simultaneously-sampling, 24-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry.

The ADS129x have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 250SPS to 32kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be synchronized using the START pin.

The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The device supports both hardware PACE detection and software PACE detection. The Wilson Central Terminal (WCT) block can be used to generate the WCT point of the standard 12-lead ECG.

Additionally, the ADS1294R, ADS1296R, and ADS1298R provide options for an internal respiration modulator and a demodulator circuit in the signal path of channel 1.

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DRDY

CLK

CLKSEL

START

MUX

Oscillator

Power-Supply Signal

SPI

DVDD

DGND

RLD

INV

RLD

OUT

RLD

REF

Lead-Off Excitation Source

PACE

OUT2

GPIO1

GPIO4/RCLKO

GPIO3/RCLKO

RESP

CLK

PACE

OUT1

CS

SCLK

DIN

DOUT

RLD

IN

ADS1298/8R

ADS1296/6R/8/8R

GPIO2

AVDD

AVSS

IN8P

IN8N

IN7P

IN7N

IN6P

IN6N

IN5P

IN5N

IN4P

IN4N

IN3P

IN3N

IN2P

IN2N

IN1P

IN1N

PGA1

DS

ADC1

PGA2

PGA3

PGA4

PGA5

PGA6

PGA7

PGA8

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

Temperature Sensor Input

RLD

Amplifier

PACE

Amplifier 2

PACE

Amplifier 1

WCT

B

C

A

From

Wmuxc

From

Wmuxa

From

Wmuxb

WCT

Reference

VREFP

VREFN

Control

PWDN

RESET

DS

ADC2

DS

ADC3

DS

ADC4

DS

ADC5

DS

ADC6

DS

ADC7

DS

ADC8

AVDD1

AVSS1

Test Signal

Internal Respiration

Modulator

( )ADS129xR

RESP

DEMOD

RESP_DEMOD_EN

ADS129xR

RESP_MODP

RESP_MODN

G = 0.4

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ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Figure 23. Functional Block Diagram

MUX[2:0]=101

TempP

MUX[2:0]= 100

MvddP

(1)

MUX[2:0]= 011

FromLoffP

MUX[2:0]= 000

MUX[2:0]= 110

MUX[2:0]= 001

ToPgaP

ToPgaN

MUX[2:0]= 001

RLDIN

MUX[2:0]= 010 RLD_MEAS

AND

MUX[2:0]= 111

VINP

VINN

MUX[2:0]= 000

FromLoffN

RLD_REF

MUX[2:0]= 010 RLD_MEAS

AND

MvddN

(1)

TempN

MUX[2:0]= 100

MUX[2:0]= 101

ADS129x

MUX

TestP

TestN

TESTP_PACE_OUT1

INT_TEST

TESTN_PACE_OUT2

INT_TEST

MUX[2:0]= 011

EMI

Filter

(AVDD+AVSS)

2

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

THEORY OF OPERATION

This section discusses the details of the ADS129x internal functional elements. The analog blocks are reviewed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end.

Throughout this document, f

denotes the frequency of the signal at the CLK pin, t

CLK

denotes the period of the

CLK

signal at the CLK pin, fDRdenotes the output data rate, tDRdenotes the time period of the output data, and f denotes the frequency at which the modulator samples the input.

EMI FILTER

An RC filter at the input acts as an EMI filter on all of the channels. The –3dB filter bandwidth is approximately 3MHz.

INPUT MULTIPLEXER

The ADS129x input multiplexers are very flexible and provide many configurable signal switching options.

Figure 24 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks,

one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. Selection of switch settings for each channel is made by writing the appropriate values to the CHnSET[2:0] register (see the CHnSET: Individual Channel Settings section for details) and by writing the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3: Configuration Register

3 subsection of the Register Map section for details). More details of the ECG-specific features of the multiplexer

are presented in the Input Multiplexer subsection of the ECG-Specifc Functions section.

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MOD

(1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN)

section.

Figure 24. Input Multiplexer Block for One Channel

Temperature( C)=°

TemperatureReading( V) 145,300 Vm - m

490 V/ Cm °

+25 C°

2x

1x

8x

AVDD

AVSS

TemperatureSensorMonitor

ToMUXTempP

ToMUXTempN

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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Device Noise Measurements

Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system.

Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing.

Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls switching at the required frequency.

The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins. A bit register (CONFIG2.INT_TEST = 0) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The test signal feature cannot be used in conjunction with the external hardware PACE feature (see the

External Hardware Approach subsection of the ECG-Specific Functions section for details).

Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)

When hardware PACE detect is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels. The performance of the differential input signal fed through these pins is identical to the normal channel performance.

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Temperature Sensor (TempP, TempN)

The ADS129x contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 25. The difference in current densities of the diodes yields a difference in voltage that is proportional to absolute temperature.

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS129x causes a higher reading than the temperature of the surrounding PCB.

The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to μV.

(1)

Figure 25. Measurement of the Temperature Sensor in the Input

ADS1298

- V to

+1/2V

REF

1/2

Common

Voltage

Single-EndedInput

ADS1298

V peak-to-peak

REF

V peak-to-peak

REF

Common

Voltage

DifferentialInput

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and for channel 4, (MVDDP – MVDDN) is DVDD/4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. For example, if AVDD = 2.5V and AVSS = –2.5V, then the measurement result would be 2.5V.

Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.

Auxiliary Single-Ended Input

The RLD_IN pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg drive electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The signal at the RLD_IN pin can be measured with respect to the voltage at the RLD_REF pin using any of the eight channels. This measurement is done by setting the channel multiplexer setting to '010' and the RLD_MEAS bit of the CONFIG3 register to '1'.

ANALOG INPUT

The analog input to the ADS1298 is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –V and AVDD + 0.3V. Refer to Table 8 for an explanation of the correlation between the analog input and the digital codes. There are two general methods of driving the analog input of the ADS1298: single-ended or differential, as shown in Figure 26 and Figure 27. Note that INP and INN are 180°C out-of-phase in the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + 1/2V is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2V common-mode – 1/2V differential configuration.

REF

to +V

REF

. Note that the the absolute range for INP and INN must be between AVSS – 0.3V

REF

) and the (common-mode – 1/2V

). When the input is differential, the common-mode

REF

). For optimal performance, it is recommended that the ADS1298 devices be used in a

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REF

to

Figure 26. Methods of Driving the ADS1298: Single-Ended or Differential

CM+1/2V

REF

+1/2V

REF

- V

REF

1/2

Single-EndedInputs

t

INP

CMVoltage

CM V-

REF

1/2

CM+1/2V

REF

DifferentialInputs

t

INP

INN

CMVoltage

CM 1/2V

REF

-

+V

REF

-V

REF

Common-ModeVoltage(DifferentialMode)=

(INP)+(INN)

2

,Common-ModeVoltage(Single-EndedMode)= INN.

INN=CMVoltage

InputRange(DifferentialMode)=(AINP AINN)=V ( V )=2V .-

REF REF

- -

REF

PgaP

R 50kW

2

R 20k

(forGain=6)

W

1

R 50kW

2

FromMuxP

PgaN

FromMuxN

ToADC

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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Figure 27. Using the ADS1298 in the Single-Ended and Differential Input Modes

PGA SETTINGS AND INPUT RANGE

The PGA is a differential input/differential output amplifier, as shown in Figure 28. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel

Settings subsection of the Register Map section for details). The ADS129x have CMOS inputs and hence have

negligible current noise. Table 6 shows the typical values of bandwidths for various gain settings. Note that

Table 6 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the

PGA.

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

Figure 28. PGA Implementation

Table 6. PGA Gain versus Small-Signal Bandwidth

GAIN TEMPERATURE (kHz)

1 237 2 146

3 127 4 96 6 64 8 48

12 32

NOMINAL BANDWIDTH AT ROOM

AVDD 0.2- -

GainV

MAX_DIFF

2

>CM>AVSS+0.2+

GainV

MAX_DIFF

2

Max(INP INN)<-

V

REF

Gain

Full-ScaleRange=

±V

REF

Gain

; =

2V

REF

Gain

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

0.001 0.01 0.1 1 Normalized Frequency (fIN/f

MOD

)

Power Spectral Density (dB)

G001

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.

Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 2:

where: V

MAX_DIFF

= maximum differential signal at the input of the PGA CM = common-mode range (2) For example:

If VDD= 3V, gain = 6, and V

MAX_DIFF

= 350mV

Then 1.25V < CM < 1.75V

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Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3.

(3)

The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300mV. For higher dynamic range, a 5V supply with a reference of 4V (set by the VREF_4V bit of the CONFIG3 register) can be used to increase the differential dynamic range.

ADC ΔΣ Modulator

Each channel of the ADS129x has a 24-bit ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of f mode and f shaped until f

= f

MOD

/8 for Low-Power mode. As in the case of any ΔΣ modulator, the noise of the ADS129x is

CLK

/2, as shown in Figure 29. The on-chip digital decimation filters explained in the next section

MOD

= f

/4 for High-Resolution

CLK

can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of the analog antialiasing filters that are typically needed with Nyquist ADCs.

Figure 29. Modulator Noise Spectrum Up To 0.5 × f

MOD

½H(z) =½

3

1 Z-

- N

1 Z-

- 1

3

sin

N fp

f

MOD

N sin´

pf

f

MOD

ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R

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DIGITAL DECIMATION FILTER

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications for implement software PACE detection and ac lead-off detection.

The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.

Sinc Filter Stage (sinx/x)

The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of f then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter.

Equation 4 shows the scaled Z-domain transfer function of the sinc filter.

The frequency domain transfer function of the sinc filter is shown in Equation 5.

. The sinc filter attenuates the high-frequency noise of the modulator,

MOD

ZHCS313I –JANUARY 2010– REVISED JANUARY 2012

(4)

where:

N = decimation ratio (5)

TEXAS INSTRUMENTS ADS1294, ADS1294R Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

应用范围

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

NOISE MEASUREMENTS

PIN CONFIGURATIONS

TIMING CHARACTERISTICS

TYPICAL CHARACTERISTICS

OVERVIEW

THEORY OF OPERATION

EMI FILTER

INPUT MULTIPLEXER

Device Noise Measurements

Test Signals (TestP and TestN)

Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)

Temperature Sensor (TempP, TempN)

Supply Measurements (MVDDP, MVDDN)

Lead-Off Excitation Signals (LoffP, LoffN)

Auxiliary Single-Ended Input

ANALOG INPUT

PGA SETTINGS AND INPUT RANGE

Input Common-Mode Range

Input Differential Dynamic Range

ADC ΔΣ Modulator

DIGITAL DECIMATION FILTER

Sinc Filter Stage (sinx/x)