TEXAS INSTRUMENTS ADS1294, ADS1296, ADS1298 Technical data

Control

CLK

GPIOANDCONTROL

Oscillator

SPI

TestSignalsand

Monitors

PACE

SPI

RLD

Wilson

Terminal

WCT

Reference

REF

ADC7

ADC8

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

MUX

INPUTS

¼ ¼

ToChannel

RESP

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Low-Power, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

Check for Samples: ADS1294, ADS1296, ADS1298

FEATURES

• Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1298)

• Low Power: 0.75mW/channel

• Input-Referred Noise: 4mVPP(150Hz BW, G = 6)

• Input Bias Current: 200pA

• Data Rate: 250SPS to 32kSPS

• CMRR: –115dB

• Programmable Gain: 1, 2, 3, 4, 6, 8, or 12

• Supplies: Unipolar or Bipolar – Analog: 2.7V to 5.25V – Digital: 1.65V to 3.6V

• Built-In Right Leg Drive Amplifier, Lead-Off Detection, WCT, Test Signals

• Pace Detection

• Digital Pace Detection Capability

• Built-In Oscillator and Reference

• Flexible Power-Down, Standby Mode

• SPI™-Compatible Serial Interface

• Operating Temperature Range: 0°C to +70°C (–40°C to +85°C grade available soon)

APPLICATIONS

• Medical Instrumentation (ECG and EEG) including:

– Patient monitoring; Holter, event, stress,

and vital signs ECG, AED, telemedicine, fetal ECG

– Bispectral index (BIS), Evoked audio

potential (EAP), Sleep study monitor

• High-Precision, Simultaneous, Multichannel Signal Acquisition

DESCRIPTION

The ADS1294/6/8 are a family of multichannel, simultaneous sampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with a built-in programmable gain amplifier (PGA), internal reference, and an onboard oscillator. The ADS1294/6/8 incorporate all of the features that are commonly required in medical electrocardiogram (ECG) and electroencephalogram (EEG) applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

With its high levels of integration and exceptional performance, the ADS1294/6/8 family enables the creation of scalable medical instrumentation systems at significantly reduced size, power, and overall cost.

The ADS1294/6/8 have a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS1294/6/8 operate at data rates as high as 32kSPS, thereby allowing the implementation of software pace detection. Lead-off detection can be implemented internal to the device, either with a pull-up/pull-down resistor or an excitation current sink/source. Three integrated amplifiers generate the Wilson Central Terminal (WCT) and the Goldberger Central Terminals (GCT) required for a standard 12-lead ECG.

Multiple ADS1294/6/8 devices can be cascaded in high channel count systems in a daisy-chain configuration.

Package options include a tiny 8mm × 8mm, 64-ball BGA and a TQFP-64. Both packages are specified from 0°C to +70°C (–40°C to +85°C for TQFP industrial grade version available soon).

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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FAMILY AND ORDERING INFORMATION

PRODUCT OPTION CHANNELS RESOLUTION (kSPS) RANGE CIRCUITRY

ADS1194

ADS1196

ADS1198

ADS1294 BGA 4 24 32 0°C to +70°C External ADS1296 BGA 6 24 32 0°C to +70°C External ADS1298 BGA 8 24 32 0°C to +70°C External

ADS1298I TQFP 8 24 32 –40°C to +85°C External

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

PACKAGE NUMBER OF ADC SAMPLE RATE TEMPERATURE RESPIRATION

BGA 4 16 8 0°C to +70°C No

TQFP 4 16 8 0°C to +70°C No

BGA 6 16 8 0°C to +70°C No

TQFP 6 16 8 0°C to +70°C No

BGA 8 16 8 0°C to +70°C No

TQFP 8 16 8 0°C to +70°C No

(1)

MAXIMUM OPERATING

(1)

Over operating free-air temperature range, unless otherwise noted.

ADS1294, ADS1296, ADS1298 UNIT

AVDD to AVSS –0.3 to +5.5 V DVDD to DGND –0.3 to +3.9 V AVSS to DGND –3 to +0.2 V V

input to AVSS AVSS – 0.3 to AVDD + 0.3 V

REF

Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V Digital output voltage to DGND –0.3 to DVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V Digital output voltage to DGND –0.3 to DVDD + 0.3 V Operating temperature range 0 to +70 °C Operating temperature range (industrial grade only) –40 to +85 °C Storage temperature range –60 to +150 °C Maximum junction temperature (TJ) +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

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ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD =

1.8V, AVDD – AVSS = 3V

unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale differential input voltage (AINP – AINN)

Input common-mode range Input capacitance 20 pF

Input bias current

DC input impedance Current source lead-off detection 500 MΩ

PGA PERFORMANCE

Gain settings 1, 2, 3, 4, 6, 8, 12 Bandwidth See Table 6

ADC PERFORMANCE

Resolution DR[2:0] = 001 19 Bits

Data rate

CHANNEL PERFORMANCE

DC Performance

Input-referred noise

Integral nonlinearity Full-scale with gain = 6, best fit 8 ppm Offset error ±500 mV Offset error drift 2 mV/°C Gain error Excluding voltage reference error ±0.2 ±0.5 % of FS Gain drift Excluding voltage reference drift 5 ppm/°C Gain match between channels 0.3 % of FS

AC Performance

Common-mode rejection fCM= 50Hz, 60Hz Power-supply rejection fPS= 50Hz, 60Hz 90 dB Crosstalk fIN= 50Hz, 60Hz –126 dB Signal-to-noise ratio (SNR) fIN= 10Hz input, gain = 6 112 dB

Total harmonic distortion (THD)

(1) Performance is applicable for 5V operation as well. Production testing for limits is performed at 3V. (2) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted

(without electrode resistance) over a 10-second interval.

(3) CMRR is measured with a common-mode signal of AVSS + 0.3V to AVDD – 0.3V. The values indicated are the minimum of the eight

channels.

(1)

, V

= 2.4V, external f

REF

TA= +25°C, input = 1.5V ±200 pA TA= 0°C to +70°C, input = 1.5V ±1 nA No lead-off 1000 MΩ

Pull-up resistor lead-off detection 10 MΩ

DR[2:0] = 011 to 110, no missing codes 24 Bits

DR[2:0] = 000 17 Bits f

= 2.048MHz 500 32000 SPS

CLK

= 2.048MHz, Low-Power mode 125 16000 SPS

CLK

Gain = 6 Gain = 6, 256 points, 0.5 seconds of data 4 7 mV Gain settings other than 6, data rate other

than 500SPS

10Hz, –0.5dBFs –98 dB 100Hz, –0.5dBFs –100 dB

(2)

, 10 seconds of data 5 mV

= 2.048MHz, data rate = 500SPS, high resolution mode, and gain = 6,

CLK

See the Input Common-Mode Range subsection of

the PGA Settings and Input Range section

(3)

SBAS459D –JANUARY 2010–REVISED MAY 2010

ADS1294, ADS1296, ADS1298

±V

/GAIN V

REF

See Noise Measurements section

105 115 dB

PP PP

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SBAS459D –JANUARY 2010–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD =

1.8V, AVDD – AVSS = 3V

6, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS

Integrated noise BW = 150Hz 7 mV Gain bandwidth product 50kΩ || 10pF load, gain = 1 100 kHz Slew rate 50kΩ || 10pF load, gain = 1 0.25 V/ms Total harmonic distortion fIN= 100Hz, gain = 1 –70 dB Common-mode input range AVSS + 0.7 AVDD – 0.3 V Common-mode resistor matching Internal200kΩ resistor matching 0.1 % Short-circuit current ±0.25 mA Quiescent power consumption Either RLD or pace amplifier 20 mA

WILSON CENTRAL TERMINAL (WCT) AMPLIFIER

Integrated noise BW = 150Hz See Table 5 nV/√Hz Gain bandwidth product See Table 5 kHz Slew rate See Table 5 V/s Total harmonic distortion fIN= 100Hz 90 dB Common-mode input range AVSS + 0.3 AVDD – 0.3 V Short-circuit current ±0.25 mA Quiescent power consumption See Table 5 mA

LEAD-OFF DETECT

Frequency See the Register Map section for settings 0, fDR/4 kHz Current See the Register Map section for settings 6, 12, 18, 24 nA Current accuracy ±10 % Comparator threshold accuracy ±30 mV

EXTERNAL REFERENCE

Reference input voltage

Negative input (VREFN) AVSS V Positive input (VREFP) AVSS + 2.5 V Input impedance 10 kΩ

INTERNAL REFERENCE

Output voltage

accuracy ±0.2 %

REF

Drift 25 ppm/°C Start-up time 150 ms

SYSTEM MONITORS

Analog supply reading error 2 % Digital supply reading error 2 %

Device wake up

Temperature sensor reading, voltage TA= +25°C 145 mV Temperature sensor reading, coefficient 490 mV/°C

Test Signal

Signal frequency See Register Map section for settings Hz Signal voltage See Register Map section for settings ±1, ±2 mV Accuracy ±2 %

(1)

, V

= 2.4V, external f

REF

3V supply V 5V supply V

CONFIG3.VREF_4V = 0 2.4 V CONFIG3.VREF_4V = 1 4.0 V

From power-up to DRDY low 150 ms STANDBY mode 9 ms

REF REF

= 2.048MHz, data rate = 500SPS, high resolution mode, and gain =

CLK

ADS1294, ADS1296, ADS1298

= (VREFP – VREFN) 2.5 V = (VREFP – VREFN) 4.0 V

CLK

/221, f

CLK

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RMS

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ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD =

1.8V, AVDD – AVSS = 3V

6, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLOCK

Internal oscillator clock frequency Nominal Frequency 2.048 MHz

Internal clock accuracy

Internal oscillator start-up time 20 ms Internal oscillator power consumption 120 mW External clock input frequency CLKSEL pin = 0 0.5 2.048 2.25 MHz

DIGITAL INPUT/OUTPUT (DVDD = 1.65V to 3.6V)

Logic level V

POWER-SUPPLY REQUIREMENTS

Analog supply (AVDD – AVSS) 2.7 3.0 5.25 V Digital supply (DVDD) 1.65 1.8 3.6 V AVDD – DVDD –2.1 3.6 V

SUPPLY CURRENT (RLD, WCT, and Pace Amplifiers Turned Off)

HighResolution mode

Low-Power mode

Input current (IIN) 0V < V

AVDD

DVDD

AVDD

DVDD

(1)

, V

= 2.4V, external f

REF

TA= +25°C ±0.5 % 0°C ≤ TA≤ +70°C ±2 % –40°C ≤ TA≤ +85°C (industrial grade

versions only)

IOH= –500mA DVDD – 0.4 V IOL= +500mA 0.4 V

DigitalInput

AVDD – AVSS = 3V 2.75 mA AVDD – AVSS = 5V 3.1 mA DVDD = 3.0V 0.5 mA DVDD = 1.8V 0.3 mA AVDD – AVSS = 3V 1.8 mA AVDD – AVSS = 5V 2.1 mA DVDD = 3.0V 0.5 mA DVDD = 1.8V 0.3 mA

= 2.048MHz, data rate = 500SPS, high resolution mode, and gain =

CLK

< DVDD –10 +10 mA

SBAS459D –JANUARY 2010–REVISED MAY 2010

ADS1294, ADS1296, ADS1298

±5 %

0.8DVDD DVDD + 0.1 V –0.1 0.2DVDD V

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SBAS459D –JANUARY 2010–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD =

1.8V, AVDD – AVSS = 3V 6, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER DISSIPATION (Analog Supply = 3V, RLD, WCT, and Pace Amplifiers Turned Off)

Quiescent power dissipation (ADS1298)

ADS1298

Quiescent power dissipation, per channel

POWER DISSIPATION (Analog Supply = 5V, RLD, WCT, and Pace Amplifiers Turned Off)

Quiescent power dissipation (ADS1298)

Quiescent power dissipation, per channel

TEMPERATURE

Specified temperature range 0 +70 °C Operating temperature range 0 +70 °C Specified temperature range

(industrial grade only) Operating temperature range

(industrial grade only) Storage temperature range –60 +150 °C

ADS1296

ADS1294

ADS1298

ADS1296

ADS1294

(1)

, V

= 2.4V, external f

REF

High-Resolution mode 8.8 9.5 mW Low-Power mode (250SPS) 6.0 7.0 mW Power-down 10 mW Standby mode 2 mW High-Resolution mode 1.10 mW Low-Power mode 0.75 mW High-Resolution mode 1.2 mW Low-Power mode 0.85 mW High-Resolution mode 1.30 mW Low-Power mode 0.90 mW

High-Resolution mode 17.5 mW Low-Power mode 12.5 mW Power-down 20 mW Standby mode, internal reference 4 mW High-Resolution mode 2 mW Low-Power mode 1.5 mW High-Resolution mode 2.3 mW Low-Power mode 1.6 mW High-Resolution mode 2.6 mW Low-Power mode 2 mW

= 2.048MHz, data rate = 500SPS, high resolution mode, and gain =

CLK

ADS1294, ADS1296, ADS1298

–40 +85 °C

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NOISE MEASUREMENTS

The ADS1294/6/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.

Table 1 and Table 2 summarize the noise performance of the ADS1294/6/8 in the High-Resolution (HR) mode

and Low-Power (LP) mode, respectively, with a 3V analog power supply. Table 3 and Table 4 summarize the noise performance of the ADS1294/6/8 in the HR mode and LP mode, respectively, with a 5V analog power supply. The data are representative of typical noise performance at TA= +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. Thus, the ratio between rms noise and peak-to-peak noise is approximately 10. For the lower data rates, the ratio is approximately 6.6.

Table 1 to Table 4 show measurements taken with an internal reference. The data are also representative of the

ADS1294/6/8 noise performance when using a low-noise external reference such as the REF5025.

SBAS459D –JANUARY 2010–REVISED MAY 2010

Table 1. Input-Referred Noise (mV

3V Analog Supply and 2.4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

000 32000 8398 335/3553 168/1701 112/1100 85/823 58/529 42.5/378 28.6/248 001 16000 4193 56/613 28/295 18.8/188 14.3/143 9.7/94 7.4/69 5.2/44.3 010 8000 2096 12.4/111 6.5/54 4.5/37.9 3.5/29.7 2.6/21.7 2.2/17.8 1.8/13.8 011 4000 1048 6.1/44.8 3.2/23.3 2.4/17.1 1.9/14.0 1.5/11.1 1.3/9.7 1.2/8.5 100 2000 524 4.1/27.8 2.2/15.4 1.6/11.0 1.3/9.1 1.1/7.3 1.0/6.5 0.9/6.0 101 1000 262 2.9/19.0 1.6/10.1 1.2/7.5 1.0/6.2 0.8/5.0 0.7/4.6 0.6/4.1 110 500 131 2.1/12.5 1.1/6.8 0.9/5.1 0.7/4.3 0.6/3.5 0.5/3.1 0.5/2.9

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (mV

3V Analog Supply and 2.4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

000 16000 4193 333/3481 166/1836 111/1168 84/834 56/576 42/450 28/284 001 8000 2096 56/554 28/272 19/177 14.3/133 9.7/85 7.4/64 5.0/42.4 010 4000 1048 12.5/99 6.5/51 4.5/35.0 3.4/25.9 2.4/18.8 2.0/14.5 1.5/11.3 011 2000 524 6.1/41.8 3.2/22.2 2.3/15.9 1.8/12.1 1.4/9.3 1.2/7.8 1.0/6.7 100 1000 262 4.1/26.3 2.2/14.6 1.6/9.9 1.3/8.1 1.0/6.2 0.8/5.4 0.7/4.7 101 500 131 3.0/17.9 1.6/9.8 1.1/6.8 0.9/5.7 0.7/4.2 0.6/3.6 0.5/3.4 110 250 65 2.1/11.9 1.1/6.3 0.8/4.6 0.7/4.0 0.5/3.0 0.5/2.6 0.4/2.4

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

/mVPP) in High-Resolution Mode

RMS

/mVPP) in Low-Power Mode

RMS

(1)

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Table 3. Input-Referred Noise (mV

5V Analog Supply and 4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

000 32000 8398 521/5388 260/2900 173/1946 130/1403 87/917 65/692 44/483 001 16000 4193 86/1252 43/633 29/402 22/298 15/206 11/141 7/91 010 8000 2096 17/207 9/112 6/71 4/57 3/36 3/29 2/18 011 4000 1048 6.4/48.2 3.4/25.9 2.417.7 1.9/15.4 1.5/11.2 1.3/9.6 1.1/8.2 100 2000 524 4.2/29.9 2.3/15.9 1.6/11.1 1.3/9.3 1.0/7.5 0.9/6.6 0.8/5.8 101 1000 262 2.9/18.8 1.6/10.4 1.1/7.8 0.9/6.1 0.7/4.9 0.6/4.7 0.6/3.9 110 500 131 2.0/12.8 1.1/7.2 0.8/5.2 0.7/4.0 0.5/3.3 0.5/3.3 0.4/2.7

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (mV

5V Analog Supply and 4V Reference

DR BITS OF OUTPUT –3dB

CONFIG1 DATA RATE BANDWIDTH PGA PGA PGA PGA PGA PGA PGA

000 16000 4193 526/5985 263/2953 175/1918 132/1410 88/896 66/681 44/458 001 8000 2096 88/1201 44/619 29/411 22/280 15/191 11/139 7/83 010 4000 1048 17/208 9/103 6/62 4/52 3/37 2/25 2/16 011 2000 524 6.0/41.1 3.3/23.3 2.2/15.5 1.8/12.3 1.3/9.8 1.1/7.8 0.9/6.5 100 1000 262 4.1/27.1 2.3/14.8 1.5/10.1 1.2/8.1 0.9/6.0 0.8/5.4 0.7/4.4 101 500 131 2.9/17.4 1.6/9.6 1.1/6.6 0.9/5.9 0.7/4.3 0.6/3.4 0.5/3.2 110 250 65 2.1/11.9 1.1/6.6 0.8/4.6 0.6/3.7 0.5/3.0 0.4/2.5 0.4/2.2

(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

/mVPP) in High-Resolution Mode

RMS

/mVPP) in Low-Power Mode

RMS

(1)

Table 5. Typical WCT Performance

ANY ONE ANY TWO ALL THREE

PARAMETER (A, B, or C) (A+B, A+C, or B+C) (A+B+C) UNIT

Integrated noise 540 382 312 nV

Power 53 59 65 mA –3dB BW 30 59 89 kHz Slew rate BW limited BW limited BW limited —

RMS

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IN8P

IN7P

IN6PIN5P

IN4P

IN3P

IN2PIN1P

IN8N

IN7N

IN6NIN5N

IN4N

IN3N

IN2NIN1N

RLDIN

RLDOUT

RLDINV

WCT

TESTP_

PACE_OUT1

TESTN_

PACE_OUT2

VCAP4

VREFP

AVDDAVDDRLDREF

AVSSRESV1RESV2

RESV3

VREFN

AVSSAVSSAVSSAVSS

GPIO4GPIO1

PWDN

VCAP1

AVDDAVDDAVDDDRDY

GPIO3

DAISY_IN

RESET

VCAP2

AVDD1

VCAP3DGNDDGNDGPIO2CS

START

DGND

AVSS1

CLKSEL

DVDD

DVDDDOUTSCLKCLK

DIN

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ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

PIN CONFIGURATIONS

ZXG PACKAGE

BGA-64

(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)

(1) Connect unused analog inputs IN1x to IN8x to AVDD.

NAME TERMINAL FUNCTION DESCRIPTION

(1)

IN8P

(1)

IN7P

(1)

IN6P

(1)

IN5P

(1)

IN4P

(1)

IN3P

(1)

IN2P

(1)

IN1P

(1)

IN8N

(1)

IN7N

(1)

IN6N

(1)

IN5N

(1)

IN4N

(1)

IN3N

(1)

IN2N

(1)

IN1N

1A Analog input Differential analog positive input 8 (ADS1298 only)

BGA PIN ASSIGNMENTS

1B Analog input Differential analog positive input 7 (ADS1298 only) 1C Analog input Differential analog positive input 6 (ADS1296/8 only) 1D Analog input Differential analog positive input 5 (ADS1296/8 only) 1E Analog input Differential analog positive input 4 1F Analog input Differential analog positive input 3 1G Analog input Differential analog positive input 2 1H Analog input Differential analog positive input 1 2A Analog input Differential analog negative input 8 (ADS1298 only) 2B Analog input Differential analog negative input 7 (ADS1298 only) 2C Analog input Differential analog negative input 6 (ADS1296/8 only) 2D Analog input Differential analog negative input 5 (ADS1296/8 only) 2E Analog input Differential analog negative input 4 2F Analog input Differential analog negative input 3 2G Analog input Differential analog negative input 2 2H Analog input Differential analog negative input 1

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SBAS459D –JANUARY 2010–REVISED MAY 2010

BGA PIN ASSIGNMENTS (continued)

NAME TERMINAL FUNCTION DESCRIPTION

RLDIN 3A Analog input Right leg drive input to MUX

RLDOUT 3B Analog output Right leg drive output

RLDINV 3C Analog input/output Right leg drive inverting input

WCT 3D Analog output Wilson Central Terminal output TESTP_PACE_OUT1 3E Analog input/buffer output Internal test signal/single-ended buffer output based on register settings TESTN_PACE_OUT2 3F Analog input/output Internal test signal/single-ended buffer output based on register settings

VCAP4 3G Analog output Analog bypass capacitor VREFP 3H Analog input/output Positive reference voltage

AVDD 4A Supply Analog supply AVDD 4B Supply Analog supply

RLDREF 4C Analog input Right leg drive noninverting input

AVSS 4D Supply Analog ground RESV1 4E Digital input Reserved for future use. Must tie to logic low (DGND) RESV2 4F Analog output Reserved for future use RESV3 4G Analog output Reserved for future use VREFN 4H Analog input Negative reference voltage

AVSS 5A Supply Analog ground

AVSS 5B Supply Analog ground

AVSS 5C Supply Analog ground

AVSS 5D Supply Analog ground

GPIO4 5E Digital input/output GPIO4 in normal mode, RESP_PH in respiration mode GPIO1 5F Digital input/output General purpose input/output pin PWDN 5G Digital input Power-down; active low

VCAP1 5H Analog input/output Analog bypass capacitor

AVDD 6A Supply Analog supply AVDD 6B Supply Analog supply AVDD 6C Supply Analog supply DRDY 6D Digital output Data ready; active low

GPIO3 6E Digital input/output GPIO3 in normal mode, RESP in respiration mode

DAISY_IN 6F Digital input Daisy-chain input

RESET 6G Digital input System reset; active low VCAP2 6H — Analog bypass capacitor AVDD1 7A Supply Analog supply for charge pump VCAP3 7B — Analog bypass capacitor

DGND 7C Supply Digital ground DGND 7D Supply Digital ground

GPIO2 7E Digital input/output General-purpose input/output pin

CS 7F Digital input SPI chip select; active low

START 7G Digital input Start conversion

DGND 7H Supply Digital ground

AVSS1 8A Supply Analog ground for charge pump

CLKSEL 8B Digital input Master clock select

DVDD 8C Supply Digital power supply DVDD 8D Supply Digital power supply DOUT 8E Digital output SPI data out

SCLK 8F Digital input SPI clock

CLK 8G Digital input Master clock input

DIN 8H Digital input SPI data in

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DVDD

GPIO4

GPIO3

GPIO2

DOUT

GPIO1

DAISY_IN

SCLK

START

CLK

DIN

DGND

DRDY

RESET

PWDN

IN8N

IN8P

IN7N

IN7P

IN6N

IN6P

IN5N

IN5P

IN4N

IN4P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

WCT

RLDOUT

RLDIN

RLDINV

RLDREF

AVDD

AVSS

AVDD

VCAP3

AVDD1

AVSS1

CLKSEL

DGND

DVDD

DGND

TESTP_PACE_OUT1

TESTN_PACE_OUT2

AVDD

AVSS

AVDD

AVSS

VREFP

VREFN

VCAP4

VCAP1

VCAP2

RESV1

AVSS

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ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

PAG PACKAGE

TQFP-64

(TOP VIEW)

(1) Connect unused analog inputs IN1x to IN8x to AVDD.

NAME TERMINAL FUNCTION DESCRIPTION

(1)

IN8N

(1)

IN8P

(1)

IN7N

(1)

IN7P

(1)

IN6N

(1)

IN6P

(1)

IN5N

(1)

IN5P

(1)

IN4N

(1)

IN4P

(1)

IN3N

(1)

IN3P

(1)

IN2N

(1)

IN2P

1 Analog input Differential analog negative input 8 (ADS1298 only) 2 Analog input Differential analog positive input 8 (ADS1298 only) 3 Analog input Differential analog negative input 7 (ADS1298 only) 4 Analog input Differential analog positive input 7 (ADS1298 only) 5 Analog input Differential analog negative input 6 (ADS1296/8 only) 6 Analog input Differential analog positive input 6 (ADS1296/8 only) 7 Analog input Differential analog negative input 5 (ADS1296/8 only) 8 Analog input Differential analog positive input 5 (ADS1296/8 only)

9 Analog input Differential analog negative input 4 10 Analog input Differential analog positive input 4 11 Analog input Differential analog negative input 3 12 Analog input Differential analog positive input 3 13 Analog input Differential analog negative input 2 14 Analog input Differential analog positive input 2

PAG PIN ASSIGNMENTS

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SBAS459D –JANUARY 2010–REVISED MAY 2010

PAG PIN ASSIGNMENTS (continued)

NAME TERMINAL FUNCTION DESCRIPTION

(1)

IN1N

(1)

IN1P TESTP_PACE_OUT1 17 Analog input/buffer output Internal test signal/single-ended buffer output based on register settings TESTN_PACE_OUT2 18 Analog input/output Internal test signal/single-ended buffer output based on register settings

AVDD 19 Supply Analog supply

AVSS 20 Supply Analog ground AVDD 21 Supply Analog supply AVDD 22 Supply Analog supply

AVSS 23 Supply Analog ground

VREFP 24 Analog input/output Positive reference voltage VREFN 25 Analog input Negative reference voltage VCAP4 26 Analog output Analog bypass capacitor

NC 27 — No connection

VCAP1 28 — Analog bypass capacitor

NC 29 — No connection VCAP2 30 — Analog bypass capacitor RESV1 31 Digital input Reserved for future use. Must tie to logic low (DGND)

AVSS 32 Supply Analog ground

DGND 33 Supply Digital ground

DIN 34 Digital input SPI data in

PWDN 35 Digital input Power-down; active low

RESET 36 Digital input System reset; active low

CLK 37 Digital input Master clock input

START 38 Digital input Start conversion

CS 39 Digital input SPI chip select; active low

SCLK 40 Digital input SPI clock

DAISY_IN 41 Digital input Daisy-chain input

GPIO1 42 Digital input/output General purpose input/output pin

DOUT 43 Digital output SPI data out GPIO2 44 Digital input/output General-purpose input/output pin GPIO3 45 Digital input/output GPIO3 in normal mode, RESP in respiration mode GPIO4 46 Digital input/output GPIO4 in normal mode, RESP_PH in respiration mode

DRDY 47 Digital output Data ready; active low

DVDD 48 Supply Digital power supply

DGND 49 Supply Digital ground

DVDD 50 Supply Digital power supply

DGND 51 Supply Digital ground

CLKSEL 52 Digital input Master clock select

AVSS1 53 Supply Analog ground AVDD1 54 Supply Analog supply VCAP3 55 Analog Analog bypass capacitor

AVDD 56 Supply Analog supply

AVSS 57 Supply Analog ground AVSS 58 Supply Analog ground for charge pump

AVDD 59 Supply Analog supply for charge pump

RLDREF 60 Analog input Right leg drive noninverting input

RLDINV 61 Analog input/output Right leg drive inverting input

RLDIN 62 Analog input Right leg drive input to MUX

RLDOUT 63 Analog output Right leg drive output

WCT 64 Analog output Wilson Central Terminal output

15 Analog input Differential analog negative input 1 16 Analog input Differential analog positive input 1

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SCLK

DIN

DOUT

3 8

1 2

CSSC

DIST

DIHD

DOHD

CSH

DOPD

SPWH

SPWL

SCCS

Hi-Z

CSDOZ

CSDOD

Hi-Z

SCLK

SDECODE

CLK

D ISY_INA

DOUT

SCLK

MSB

DISCK2ST

MSB

3 216

217

218

MSB

LSB

DISCK2HT

DOST

Don’tCare

LSB

219

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TIMING CHARACTERISTICS

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

Figure 1. Serial Interface Timing

Figure 2. Daisy-Chain Interface Timing

Timing Requirements For Figure 1 and Figure 2

Specifications apply from 0°C to +70°C. Load on D

PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT

CLK

CSSC

SCLK

SPWH, L

DIST

DIHD

DOHD

DOPD

CSH

CSDOD

SCCS

SDECODE

CSDOZ

DISCK2ST

DISCK2HT

Master clock period 414 514 414 514 ns CS low to first SCLK, setup time 6 17 ns SCLK period 50 66.6 ns SCLK pulse width, high and low 15 25 ns DIN valid to SCLK falling edge: setup time 10 10 ns Valid DIN after SCLK falling edge: hold time 10 11 ns SCLK falling edge to invalid DOUT: hold time 10 10 ns SCLK rising edge to DOUT valid: setup time 17 32 ns CS high pulse 2 2 t CS low to DOUT driven 10 20 ns Eighth SCLK falling edge to CS high 4 4 t Command decode time 4 4 t CS high to DOUT Hi-Z 10 20 ns DAISY_IN valid to SCLK rising edge: setup time 10 10 ns DAISY_IN valid after SCLK rising edge: hold time 10 10 ns

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= 20pF || 100kΩ.

OUT

2.7V ≤ DVDD ≤ 3.6V 1.65V ≤ DVDD ≤ 2V

CLKs

CLKs CLKs

Time(sec)

Input-ReferredNoise( V)m

1 20 103 4 5 6 7 8 9

Peak-to-PeakOver10sec=5 Vm

1600

1400

1200

1000

800

600

400

200

Input-ReferredNoise( V)m

Occurrences

-2.88

-2.35

-1.85

-1.35

-0.84

-0.34

0.17

1.17

2.18

0.67

1.68

130

125

120

115

110

105

100

Frequency(Hz)

Common-ModeRejectionRatio(dB)

100

Gain=1

DataRate=4kSPS AIN=AVDD 0.3VtoAVSS+0.3V-

Gain=2 Gain=3 Gain=4 Gain=6 Gain=8 Gain=12

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.3

4.8

InputVoltage(V)

InputLeakageCurrent(nA)

2.3

AVDD AVSS=5V PGA=1

1.81.30.8 2.8 3.3 3.8 4.3

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Temperature( C)°

LeakageCurrent(nA)

40302010 50 60 70

110

105

100

Frequency(Hz)

Power-SupplyRejectionRatio(dB)

100

DataRate=4kSPS

Gain=2

Gain=4

Gain=1

Gain=12

Gain=3

Gain=8

Gain=6

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS,

external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

INPUT-REFERRED NOISE NOISE HISTOGRAM

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS

CMRR vs FREQUENCY LEAKAGE CURRENT vs INPUT VOLTAGE

Figure 5. Figure 6.

LEAKAGE CURRENT vs TEMPERATURE PSRR vs FREQUENCY

Figure 7. Figure 8.

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105

100

Frequency(Hz)

TotalHarmonicDistortion(dB)

100

DataRate=4kSPS AIN=0.5dBFS

Gain=1

Gain=2

Gain=4

Gain=12

Gain=3

Gain=8

Gain=6

Input(NormalizedtoFull-Scale)

IntegralNonlinearity(ppm)

-0.8-1.0 1.0-0.2 0.2 0.6-0.6 0.8-0.4 0 0.4

Gain=6 Gain=8 Gain=12

Gain=1 Gain=2 Gain=3 Gain=4

-1.0

1.0

Input(NormalizedtoFull-Scale)

IntegralNonlinearity(ppm)

-0.8

AIN= 1dBFS-

T =0 CA° T =+25 CA° T =+40 CA° T =+60 CA° T =+70 CA°

-0.6 -0.4 -0.2

0.80.60.40.20

100

120

140

160

180

Frequency(Hz)

Amplitude(dBFS)

500 250100 150 200

PGAGain=1

THD= 102dB

SNR=115dB f =500SPS

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SBAS459D –JANUARY 2010–REVISED MAY 2010

TYPICAL CHARACTERISTICS (continued)

All plots at TA= +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.

THD vs FREQUENCY INL vs PGA GAIN

Figure 9. Figure 10.

ADS1294 ADS1296 ADS1298

THD FFT PLOT

INL vs TEMPERATURE (60Hz Signal)

Figure 11. Figure 12.

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800

700

600

500

400

300

200

100

PGAGain

Offset( V)m

8642 10 12

100

120

140

160

180

Frequency(kHz)

Amplitude(dBFS)

20 164 6 8

PGAGain=6

THD= 104dB

SNR=74.5dB

f =32kSPS

10 12 14

-0.53

Error(%)

NumberofBins

-0.41

-0.18

0.06

0.30

0.54

0.66

0.42

0.18

-0.06

-0.29

DataFrom31Devices,TwoLots

-0.020

ThresholdError(V)

NumberofBins

-0.020

0.010

0.020

0.030

0.020

0.010

0.006

-0.010

DataFrom31Devices,TwoLots

120

100

-2.70

ErrorinCurrentMagnitude(nA)

NumberofBins

-2.14

-1.01

0.12

1.24

2.37

2.93

1.80

0.68

-0.45

-1.57

DataFrom31Devices,TwoLots

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

TYPICAL CHARACTERISTICS (continued)

FFT PLOT OFFSET vs PGA GAIN

(60Hz Signal) (ABSOLUTE VALUE)

Figure 13. Figure 14.

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TEST SIGNAL AMPLITUDE ACCURACY LEAD-OFF COMPARATOR THRESHOLD ACCURACY

Figure 15. Figure 16.

LEAD-OFF CURRENT SOURCE ACCURACY DISTRIBUTION

Figure 17.

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OVERVIEW

The ADS1294/6/8 are low-power, multichannel, simultaneously-sampling, 24-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry.

The ADS1294/6/8 have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 250SPS to 32kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be synchronized using the START pin.

The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The device supports both hardware pace detection and software pace detection. The Wilson Central Terminal (WCT) block can be used to generate the WCT point of the standard 12-lead ECG.

SBAS459D –JANUARY 2010–REVISED MAY 2010

Product Folder Link(s): ADS1294 ADS1296 ADS1298

DRDY

CLK

CLKSEL

START

MUX

Oscillator

Power-SupplySignal

SPI

DVDD

DGND

RLD

INV

RLD

OUT

RLD

REF

Lead-OffExcitation Source

PACE

OUT1

GPIO1

GPIO4/RCLKO

GPIO3/RCLKO

RESP

PACE

OUT2

SCLK

DIN

DOUT

RLD

ADS1298Only

ADS1296and ADS1298Only

GPIO2

AVDD

AVSS

IN8P

IN8N

IN7P

IN7N

IN6P

IN6N

IN5P

IN5N

IN4P

IN4N

IN3P

IN3N

IN2P

IN2N

IN1P

IN1N

PGA1

ADC1

PGA2

PGA3

PGA4

PGA5

PGA6

PGA7

PGA8

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

EMI

Filter

TemperatureSensorInput

RLD

Amplifier

PACE

Amplifier1

PACE

Amplifier2

WCT

From

Wmuxc

From

Wmuxa

From

Wmuxb

WCT

Reference

VREFP

VREFN

Control

PWDN

RESET

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC8

AVDD1

AVSS1

TestSignal

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

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Figure 18. Functional Block Diagram

Product Folder Link(s): ADS1294 ADS1296 ADS1298

MUX[2:0]=101

TempP

MUX[2:0]= 100

MvddP

(1)

MUX[2:0]= 011

FromLoffP

MUX[2:0]= 000

MUX[2:0]= 110

MUX[2:0]= 001

ToPgaP

ToPgaN

MUX[2:0]= 001

RLDIN

MUX[2:0]= 010 RLD_MEAS

AND

MUX[2:0]= 111

VINP

VINN

MUX[2:0]= 000

FromLoffN

RLD_REF

MUX[2:0]= 010 RLD_MEAS

AND

MvddN

(1)

TempN

MUX[2:0]= 100

MUX[2:0]= 101

ADS129x

MUX

TestP

TestN

TESTP_PACE_OUT1

INT_TEST

TESTN_PACE_OUT2

INT_TEST

MUX[2:0]= 011

EMI

Filter

(AVDD+AVSS)

ADS1294 ADS1296 ADS1298

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THEORY OF OPERATION

This section contains details of the ADS1294/6/8 internal functional elements. The analog blocks are discussed first followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end.

Throughout this document, f

denotes the frequency of the signal at the CLK pin, t

CLK

signal at the CLK pin, fDRdenotes the output data rate, tDRdenotes the time period of the output data, and f denotes the frequency at which the modulator samples the input.

EMI FILTER

An RC filter at the input acts as an EMI filter on all of the channels. The –3dB filter bandwidth is approximately 3MHz.

INPUT MULTIPLEXER

The ADS1294/6/8 input multiplexers are very flexible and provide many configurable signal switching options.

Figure 19 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks,

one for each channel. TEST_PACE_OUT1, TEST_PACE_OUT2, and RLD_IN are common to all eight blocks. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration and configuration. Selection of switch settings for each channel is made by writing the appropriate values to the CHnSET[2:0] register (see the CHnSET: Individual Channel Settings section for details) and by writing the RLD_MEAS bit in the CONFIG3 register (see the CONFIG3: Configuration Register

3 subsection of the Register Map section for details). More details of the ECG-specific features of the multiplexer

are discussed in the Input Multiplexer subsection of the ECG-Specifc Functions section.

SBAS459D –JANUARY 2010–REVISED MAY 2010

denotes the period of the

CLK

MOD

(1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN)

section.

Figure 19. Input Multiplexer Block for One Channel

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Temperature( C)=°

TemperatureReading( V) 145,300 Vm - m

490 V/ Cm °

+25 C°

AVDD

AVSS

TemperatureSensorMonitor

ToMUXTempP

ToMUXTempN

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

Device Noise Measurements

Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD + AVSS)/2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system.

Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing.

Control of the test signals is accomplished through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls switching at the required frequency.

The test signals are multiplexed and transmitted out of the device at the TESTP_PACE_OUT1 and TESTN_PACE_OUT2 pins. A bit register (CONFIG2.INT_TEST = 0) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. The test signal feature cannot be used in conjunction with the external hardware pace feature (see the

External Hardware Approach subsection of the ECG-Specific Functions section for details).

Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)

When hardware pace detect is not used, the TESTP_PACE_OUT1 and TESPN_PACE_OUT2 signals can be used as a multiplexed differential input channel. These inputs can be multiplexed to any of the eight channels. The performance of the differential input signal fed through these pins is identical to the normal channel performance.

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Temperature Sensor (TempP, TempN)

The ADS1294/6/8 contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 20. The difference in current densities of the diodes yields a difference in voltage that is proportional to absolute temperature.

As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS1294/6/8 causes a higher reading than the temperature of the surrounding PCB.

The scale factor of Equation 1 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to mV.

(1)

Figure 20. Measurement of the Temperature Sensor in the Input

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ADS1298

- V to

+1/2V

REF

1/2

Common

Voltage

Single-EndedInput

ADS1298

V peak-to-peak

REF

V peak-to-peak

REF

Common

Voltage

DifferentialInput

CM+1/2V

REF

+1/2V

REF

- V

REF

1/2

Single-EndedInputs

INP

CMVoltage

CM V-

REF

1/2

CM+1/2V

REF

DifferentialInputs

INP

INN

CMVoltage

CM 1/2V

REF

-V

REF

Common-ModeVoltage(DifferentialMode)=

(INP)+(INN)

,Common-ModeVoltage(Single-EndedMode)= INN.

INN=CMVoltage

InputRange(DifferentialMode)=(AINP AINN)=V ( V )=2V .-

REF REF

- -

REF

ADS1294 ADS1296 ADS1298

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Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD + AVSS)]; for channel 3 and for channel 4, (MVDDP – MVDDN) is DVDD/4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'.

Lead-Off Excitation Signals (LoffP, LoffN)

The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.

Auxiliary Single-Ended Input

The RLD_IN pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg drive electrode falls off. However, the RLD_IN pin can be used as a multiple single-ended input channel. The signal at the RLD_IN pin can be measured with respect to the voltage at the RLD_REF pin using any of the eight channels. This measurement is done by setting the channel multiplexer setting to '010' and the RLD_MEAS bit of the CONFIG3 register to '1'.

ANALOG INPUT

The analog input to the ADS1298 is fully differential. Assuming PGA = 1, the input (INP – INN) can span between –V digital codes. There are two general methods of driving the analog input of the ADS1298: single-ended or differential, as shown in Figure 21 and Figure 22. Note that INP and INN are 180°C out-of-phase in the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + 1/2V the common-mode is given by (INP + INN)/2. Both the INP and INN inputs swing from (common-mode + 1/2V to common-mode – 1/2V differential configuration.

REF

to +V

. Refer to Table 8 for an explanation of the correlation between the analog input and the

REF

) and the (common-mode – 1/2V

REF

). For optimal performance, it is recommended that the ADS1298 be used in a

REF

SBAS459D –JANUARY 2010–REVISED MAY 2010

). When the input is differential,

REF

Figure 21. Methods of Driving the ADS1298: Single-Ended or Differential

Figure 22. Using the ADS1298 in the Single-Ended and Differential Input Modes

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PgaP

R 50kW

R 20k

(forGain=6)

R 50kW

FromMuxP

PgaN

FromMuxN

ToADC

ADS1294 ADS1296 ADS1298

SBAS459D –JANUARY 2010–REVISED MAY 2010

PGA SETTINGS AND INPUT RANGE

The PGA is a differential input/differential output amplifier, as shown in Figure 23. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel

Settings subsection of the Register Map section for details). The ADS1294/6/8 have CMOS inputs and hence

have negligible current noise. Table 6 shows the typical values of bandwidths for various gain settings. Note that

Table 6 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the

PGA.

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Figure 23. PGA Implementation

Table 6. PGA Gain versus Bandwidth

GAIN TEMPERATURE (kHz)

1 237 2 146 3 127 4 96 6 64 8 48

12 32

NOMINAL BANDWIDTH AT ROOM

The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of differential signal at input.

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AVDD 0.2- -

GainV

MAX_DIFF

>CM>AVSS+0.2+

GainV

MAX_DIFF

Max(INP INN)<-

REF

Gain

Full-ScaleRange=

±V

REF

Gain

; =

REF

Gain

100

110

120

130

140

150

NormalizedFrequency(Hz)

Power-SpectralDensity(dB)

ADS1294 ADS1296 ADS1298

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Input Common-Mode Range

The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 2:

where: V

MAX_DIFF

= maximum differential signal at the input of the PGA CM = common-mode range (2) For example:

If VDD= 3V, gain = 6, and V

MAX_DIFF

= 350mV

Then 1.25V < CM < 1.75V

Input Differential Dynamic Range

The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3.

SBAS459D –JANUARY 2010–REVISED MAY 2010

(3)

The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300mV. For higher dynamic range, a 5V supply with a reference of 4V (set by the VREF_4V bit of the CONFIG3 register) can be used to increase the differential dynamic range.

ADC ΔΣ Modulator

Each channel of the ADS1294/6/8 has a 24-bit ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of f high-resolution mode and f the ADS1294/6/8 is shaped until f

MOD

= f

/8 for the low-power mode. As in the case of any ΔΣ modulator, the noise of

CLK

/2, as shown in Figure 24. The on-chip digital decimation filters explained in

MOD

= f

CLK

/4 for

the next section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of the analog antialiasing filters that are typically needed with nyquist ADCs.

Figure 24. Modulator Noise Spectrum Up To 0.5 × f

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MOD

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