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This user's guide describes the characteristics, operation, and use of the
ADS1271EVM, both by itself and as part of the ADS1271EVM-PDK. This EVM is a
24-bit analog-to-digital converter evaluation module. A complete circuit description,
schematic diagram, and bill of materials are also included.
The following related documents are available through the Texas Instruments web site
at www.ti.com .
User's Guide
SBAU107 – November 2004
ADS1271EVM & ADS1271EVM-PDK
EVM-Compatible Device Data Sheets
Device Number
ADS1271 SBAS306
OPA350 SBOS099B
OPA1632 SBOS286
REF1004 SBVS002
REF3125 SBVS046A
SN74AVC1T45 SCES530C
SN74AVC2T45 SCES531D
SN74LVC1G125 SCES223L
SN74LVC2G66 SCES325G
SN74LVC2G157 SCES207I
TPS71550 SLVS338H
Contents
1 EVM Overview ............................................................................................................... 2
2 Analog Interface .............................................................................................................. 2
3 Digital Interface .............................................................................................................. 3
4 Power Supplies .............................................................................................................. 4
5 EVM Operation ............................................................................................................... 6
6 Kit Operation ................................................................................................................. 8
7 EVM Bill of Materials and Schematic .................................................................................... 12
Literature
List of Figures
1 ADS1271EVM Switch and Jumper Locations ............................................................................ 6
2 ADS1271EVM-PDK Block Diagram ...................................................................................... 9
3 Default Software Screen .................................................................................................. 10
List of Tables
1 Analog Interface Pinout (J1) ................................................................................................ 3
2 Auxiliary Analog Input 1 Pinout (J4) ....................................................................................... 3
3 Auxiliary Analog Input 2 Pinout (J5) ....................................................................................... 3
ADS1271EVM & ADS1271EVM-PDKSBAU107 – November 2004 1
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EVM Overview
1 EVM Overview
1.1 Features
1.2 Introduction
4 Digital Interface Pinout (J2) ................................................................................................. 4
5 Power Supply Pinout ........................................................................................................ 4
6 Reference Selection Options - S3 and S5 ................................................................................ 5
7 Buffer Amplfier Options - S1 and S2 ...................................................................................... 6
8 ADC Analog Input Options - S4 and S6 .................................................................................. 6
9 ADS1271EVM Bill of Materials ........................................................................................... 12
• Full-featured evaluation board for the ADS1271 24-bit Analog-to-Digital Converter
• Two ADS1271 converters on board illustrate use of daisy-chain mode
• On-board reference and oscillator circuits
• Modular design for use with a variety of DSP and microcontroller interface boards.
• ADS1271EVM-PDK is a complete evaluation kit, which includes a USB-based motherboard and
evaluation software for use with a personal computer running Microsoft Windows™ operating systems.
The ADS1271EVM is built in Texas Instruments' modular EVM form factor, which allows direct evaluation
of the ADS1271 performance and operating characteristics, and eases software development and system
prototyping. This EVM is compatible with the 5-6K Interface Board (SLAU104) from Texas Instruments
and additional third-party boards such as the HPA449 demonstration board from SoftBaugh, Inc.
(www.softbaugh.com ) and the Speedy33™ from Hyperception, Inc. (www.hyperception.com ).
The ADS1271EVM-PDK is a complete evaluation/demonstration kit, which includes a USB-enabled
DSP-based motherboard (the MMB0) and evaluation software for use with a PC.
2 Analog Interface
The ADS1271EVM features several analog input options. Signals can be routed directly to the converters
or can pass through the on-board buffer amplifiers (U5, U6). Signals can be applied to the board through
the standard modular EVM analog connector (J1) or brought in through the auxiliary input connectors (J4,
J5). A set of switches selects which analog connector source is used and whether the buffer amplifiers are
in the signal path. These switches enable several configurations for evaluation. Switch operation and
analog path configuration are described in Section 5.1 .
For maximum flexibility, the ADS1271EVM is designed for easy interfacing to multiple analog sources.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,
dual-row, header/socket combination at J1. This header/socket provides access to the analog input pins of
the ADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options. Table 1 through Table 3 summarize the standard and auxiliary analog pinout
configurations.
Speedy33 is a trademark of Hyperception, Inc..
Windows is a trademark of Microsoft Corp..
WinZip is a trademark of WinZip Computing, Inc..
2 ADS1271EVM & ADS1271EVM-PDK SBAU107 – November 2004
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Table 1. Analog Interface Pinout (J1)
Pin Number Signal Description
J1.1 AIN0N ADS1271 (U7) AINN
J1.2 AIN0P ADS1271 (U7) AINP
J1.3 AIN1N ADS1271 (U8) AINN
J1.4 AIN1P ADS1271 (U8) AINP
J1.5 Unused
J1.6 Unused
J1.7 Unused
J1.8 Unused
J1.15 Unused
J1.18 REF(-) External reference source low side
J1.20 REF(+) External reference source input (2.5V NOM)
J1.9-J1.19 (odd) GND Analog ground connections (except J1.15)
J1.10-J1.16 (even) Unused
Table 2. Auxiliary Analog Input 1 Pinout (J4)
Pin Number Signal Description
J4.1 AUX1P Auxiliary Signal Input 1 - Positive terminal
J4.2 AUX1N Auxiliary Signal Input 1 - Negative terminal
J4.3 AUXREF1P Auxiliary Reference Input 1 - Positive terminal
J4.4 AUXREF1N Auxiliary Reference Input 1 - Negative terminal
J4.5 GND Ground
Digital Interface
3 Digital Interface
Table 3. Auxiliary Analog Input 2 Pinout (J5)
Pin Number Signal Description
J5.1 AUX2P Auxiliary Signal Input 2 - Positive terminal
J5.2 AUX2N Auxiliary Signal Input 2 - Negative terminal
J5.3 AUXREF2P Auxiliary Reference Input 2 - Positive terminal
J5.4 AUXREF2N Auxiliary Reference Input 2 - Negative terminal
J5.5 GND Ground
The ADS1271EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J2. This header/socket provides access to the digital control and serial data pins of the
ADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector
options.
Because the ADS1271 devices are capable of daisy-chaining, this EVM has been designed to permit
stacking; up to 4 EVMs can be stacked, allowing for 8 devices to be placed in a signal chain. To
accomodate stacking of EVMs, J2 has some different connections on the top and the bottom side of the
board. Differences between top and bottom connectors are highlighted in Table 4 .
SBAU107 – November 2004 3ADS1271EVM & ADS1271EVM-PDK
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Power Supplies
Table 4. Digital Interface Pinout (J2)
Pin Number Signal Description
J2.1 SYNC Synchronization Control
J2.2 MODE0 0 = High-Speed Mode
J2.3 CLKX CLKXMODE = 1: master clock output
J2.4 DGND Digital ground
J2.5 SCLK Serial Clock
J2.6 MODE1 0 = High-Resolution Mode
J2.7 Unused.
J2.8 FSDIR Indicates FSR direction:
J2.9 Top: FSOUT FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connected
Bottom: FSR FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8
J2.10 DGND Digital ground
J2.11 Unused
J2.12 CLKRMODE 0 = Use CLKR for SPI Clock
J2.13 Top: DIN Top: Serial data input
Bottom: DOUT Bottom: Serial data output
J2.14 CLKXMODE 0 = CLKX is High Z
J2.15 Unused
J2.16 SCL I2C bus serial clock
J2.17 EXTCLK External ADC clock input
J2.18 DGND Digital ground
J2.19 OBCLKSEL Onboard Clock Select:
J2.20 SDA I2C bus data line
1 = Low-Power Mode
(In either case, only if Mode1=1)
CLKXMODE = 0: no connection
1 = Mode determined by MODE0
0 = Output (DRDY in SPI mode)
1 = Input (FSYNC mode)
1 = Use ADC Clock for SPI clock
1 = CLKX outputs ADC master clock
High to select onboard clock instead of external clock.
4 Power Supplies
J3 provides connection to the common power bus for the ADS1271EVM. Power is supplied on the pins
listed in Table 5 .
Table 5. Power Supply Pinout
Signal Pin Number Signal
+AVDD: +15V to power buffer amplifier section 1 2 –AVDD: –15V to power buffer amplifier section
+5VA 3 4 Unused
DGND 5 6 AGND
+1.8VD 7 8 Unused
+3.3VD 9 10 +5VD
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4.1 ADC Power
Power Supplies
When power is supplied to J3, J6 allows for either 3.3V or 1.8V to be applied to the digital sections of the
ADS1271. J6 also provides for a method of measuring AVDD and DVDD supply currents if the shunts on
J6.1-2, J6.3-4, J6.5-6, and J6.7-8 are removed and a current meter is connected between the appropriate
pins. See the schematic and printed circuit board silkscreen for details.
Power for the ADS1271 analog supply voltage (AVDD) comes from +5V
, which is supplied through J3.3.
A
The shunt from J6 pins 1 to 2 applies this supply to the U7 ADS1271 device, while the shunt from J6 pins
5 to 6 applies this supply to the U8 ADS1271.
The ADS1271 digital supply voltage (DVDD) is selected using J6. When a shunt is applied from J6 pins 9
to 10, +1.8VD is selected, and this power comes from J3.7. If a shunt is placed from J6 pins 11 to 12 (the
default factory setting), +3.3V
is selected, which is provided from J3.9. J6 pins 13 and 15 provide a
D
means of connecting analog and digital grounds to the EVM; these grounds come from J3.6 and J3.5,
respectively. These grounds are always connected together at the EVM.
CAUTION
Verify that all power supplies are within the safe operating limits shown on
the ADS1271 data sheet before applying power to the EVM. Note that a
shunt should only be connected between J6 pins 9 and 10 OR pins 11 and
12, but never both; doing so would short the +3.3V supply to the +1.8V
digital supply.
4.2 Stand-Alone Operation
When used as a stand-alone EVM, the analog power can be applied to J6.2 and J6.6, referenced to
J6.13. DVDD can be applied to J6.4 and J6.8, referenced to J6.15. Note that this EVM uses only a single
ground plane.
4.3 Reference Voltage
The ADS1271 requires an external voltage reference. Two switches, S3 and S5, select the source of the
reference for the two ADS1271s on the EVM. An external reference may be supplied through J1 pin 20 on
the ADS1271EVM, or through J4 and J5, the auxiliary analog input connectors. A 2.5V reference is
provided on the EVM for convenience. These different reference sources can be selected using S3 and
S5, as shown in Table 6 .
S3/S5 Position Reference Inputs
Left Onboard 2.5V reference
Middle External Reference from J1.20 (REFP) referenced to J1.18
Right S3: AUXREF1 from J4.3 referenced to J4.4
CAUTION
Verify that the external reference voltage is within the safe operating limits
shown on the ADS1271 data sheet before applying power to the EVM.
Table 6. Reference Selection Options - S3 and S5
(REFN)
S5: AUXREF2 from J5.3 referenced to J5.4
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LEFT
MIDDLE
RIGHT
EVM Operation
5 EVM Operation
The following section provides information on the analog input, digital control, and general operating
conditions of the ADS1271EVM. Refer to Figure 1 for switch and jumper locations, and the meanings of
left, middle and right for switch settings in the following discussion.
5.1 Analog Input
The analog input sources can be applied directly to J1 (top or bottom side) or through the auxiliary
connectors J4 and J5. The analog input signals can be routed directly to the two ADS1271s on the EVM,
or they can be routed through an optional buffer amplifier stage built around U5 or U6. Consult the
ADS1271 data sheet to determine the maximum analog input range. Table 7 summarizes the position of
switches S1 and S2. S4 and S6 can be used to select the routing of the ADS1271 analog inputs as shown
in Table 8 .
S1/S2 Position Analog Inputs
Top Input from J1
Middle Input from J4/J5 auxiliary inputs
Bottom No connection
S4/S6 Position Analog Inputs
Left Input from Buffer Amplifier
Middle Input from J1
Right Input from J4/J5 auxiliary inputs
Figure 1. ADS1271EVM Switch and Jumper Locations
Table 7. Buffer Amplfier Options - S1 and S2
Table 8. ADC Analog Input Options - S4 and S6
ADS1271EVM & ADS1271EVM-PDK SBAU107 – November 20046
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5.1.1 Buffer Amplifiers
The buffer amplifiers on this EVM are OPA1632s (U5, U6). These amplifiers are optimized for AC
performance and are configured as fully-differential unity gain buffers. They require ± 15V supplies, which
are provided from J3 pins 1 and 2.
The OPA1632 requires a common mode voltage, which is provided on this EVM by U2 and U3. Some
users may not wish to use the buffer amplifier section and provide the ± 15V supplies. If the ± 15V supplies
are not connected, then having a voltage on the V
ratings. Thus, U2 and U3 provide a separate 2.5V reference for the buffer amplifier section rather than
using the same reference as the ADS1271, which would always be powered. For this reason, U2 and U3
power is provided through a separate regulator, U11.
5.2 Digital Control
The digital control signals can be applied directly to J2. The modular ADS1271EVM can also be
connected directly to a DSP or microcontroller interface board, such as the HPA449. For a current list of
compatible interface and/or accessory boards for the EVM or the ADS1271, see the relevant product
folder on the TI web site.
5.3 Communication Modes
The ADS1271EVM has a digital routing network which can help simulate several possible system
connections. The routing network also provides level-shifting, which allows the ADS1271 to be operated at
any supported logic level regardless of the logic level used on J2. Note that you are not required to include
this circuitry in your own designs; typically no glue logic is required to connect one or more ADS1271s to a
processor.
pins of the amplifiers would exceed their maximum
OCM
EVM Operation
5.3.1 Routing control
Routing is controlled by pins CLKRMODE, CLKXMODE, and OBCLKSEL on J2. CLKRMODE controls the
direction and connection of CLKR. When CLKRMODE is low, CLKR is an input connected only to SCLK.
When CLKRMODE is high, CLKR becomes an output connected to SCLK, and SCLK is tied to CLK. This
connection can be useful in both FSYNC and SPI modes. A pulldown on CLKRMODE makes FSYNC
mode the default setting.
When CLKXMODE is high, CLKX is an output connected to CLK. This setting is primarily useful for certain
configurations using TI's McBSP, where CLKX can be used as a reference clock input for the serial port.
When CLKXMODE is low, CLKX on J2 is unconnected. A pulldown on CLKXMODE makes this
configuration the default.
OBCLKSEL selects between one of two master clock sources. When OBCLKSEL is high, the on-board
clock is active and used for the master clock. When OBCLKSEL is low, the master clock is taken from
EXTCLK on J2, and the on-board oscillator is disabled. A pulldown on OBCLKSEL makes this setting the
default.
5.3.2 Using the ADS1271 communication modes
You can use either of the two ADS1271 interface modes with the ADS1271EVM. The interface modes are
chosen manually using switch S7, and cannot be selected electrically.
The FSR and FSOUT pins on J2 operate differently depending on the communication mode. In SPI mode,
FSR, which is on the socket on the bottom side of the board, carries the DRDY output signal from the first
ADC (U8), the second ADC (U7) DRDY line is not connected, and the FSOUT pin on the header on the
top side of the board is not connected. In FSYNC mode, the FSYNC pins of both ADCs are tied together,
and the signal on FSR is copied to the top connector on pin FSOUT.
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Kit Operation
This arrangement allows the ADS1271EVM to be stacked with other ADS1271EVMs in either mode, as
long as all boards in the stack are in the same mode.
A motherboard can sense which state the switch is in and configure itself appropriately by monitoring the
FSDIR pin on J2. This pin is high when FSOUT is active and FSR is an input, and low when FSOUT is
disconnected and FSR is an output (that is, it carries the DRDY signal).
5.4 Clock Source
5.4.1 Onboard Oscillator
The ADS1271 requires a clock. A 25MHz clock oscillator is provided on the EVM, and is selected as the
clock source for the device when OBCLKSEL (J2.19) is high.
5.4.2 External Oscillator
When OBCLKSEL (J2.19) is low, the clock source for the ADS1271 is provided from J2.17, and the
on-board clock oscillator is shut down.
6 Kit Operation
The following section provides informationon using the ADS1271EVM-PDK, including setup, program
installation, and program usage.
ADS1271EVM & ADS1271EVM-PDK8 SBAU107 – November 2004
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6.1 ADS1271EVM-PDK Block Diagram
C5507
DSP
USB
EVM Connectors
ADS1271EVM
Control and Data
Interface
MMB0
A block diagram of the ADS1271EVM-PDK is shown in Figure 2 . The evaluation kit consists of two printed
circuit boards connected together. The motherboard is designated as the MMB0, while the daughtercard is
the ADS1271EVM described previously in this manual.
Kit Operation
6.2 Quick Start
Figure 2. ADS1271EVM-PDK Block Diagram
Ensure that the ADS1271EVM is installed on the MMB0. Place the CD-ROM into your PC CD-ROM drive.
Locate the Setup program on the disk and execute it. The Setup program installs the ADS1271 evaluation
software on your PC. Follow the instructions and prompts given.
After the main program is installed, a dialog box appears with instructions for installing NI-VISA 3.1
Runtime, a self-extracting archive. Click OK to proceed. A WinZip™ dialog appears. Click Unzip, and the
archive extracts itself and automatically runs the NI-VISA 3.1 Runtime installer.
Follow the instructions in the NI-VISA 3.1 Runtime Installer. When prompted for which features to install,
do the following:
1. Click on the disk icon next to NI-VISA 3.1
2. Select, Do not install this feature.
3. Click on the disk icon next to USB.
4. Select the option which installs this feature.
5. Click Next.
Accept the license agreement, and continue the installation.
ADS1271EVM & ADS1271EVM-PDKSBAU107 – November 2004 9
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Kit Operation
When the installation completes, click Finish on the ADS1271EVM installer window. You may be prompted
to restart your computer.
When installation is complete, attach a USB cable from your PC to the MMB0. Supply power to J14 on the
MMB0, following the silkscreen markings or schematic; this will supply the ADS1271EVM power through
the J3 connector on the ADS1271EVM.
The software should automatically find the ADS1271EVM, and a screen similar to the one in Figure 3
should appear.
Figure 3. Default Software Screen
6.3 Program Description
Once the ADS1271EVM-PDK software (described in Section 6.2 ) is installed, evaluation and development
with the ADS1271 can begin.
6.3.1 Basic Usage
When the program runs, it checks to see whether an MMB0 is connected. If it is, the program downloads
the firmware to it, and runs; otherwise, it shows a dialog box telling you that it cannot find an MMB0. If you
see this, make sure the MMB0 is connected and powered on, correct this if necessary, and click Retry. If
you cannot fix the problem, click Cancel to quit.
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After the program loads the MMB0 successfully, you will see a screen similar to that shown in Figure 3 .
The top display shows an FFT of the ADC output up to the Nyquist frequency (half the sampling rate), and
certain AC analysis numbers. Below this are a number of controls and meters, and at the bottom is a set
of tabs, which show either a histogram, a picture of the incoming waveform, or the data recording controls.
To exit the program, select File -> Exit from the menu bar.
When the program starts, it is idle. You can put it in either Acquire mode or Record mode.
6.3.1.1 Acquire Mode
To put the program into Acquire mode, click the Acquire button. In Acquire mode, the ADS1271EVM
software collects data as quickly as possible from the board in 2,048-sample blocks and analyzes it. Both
AC and DC analyses are performed.
In Acquire mode, you can only view the data from one channel at a time. To choose channels, use the
Channel box.
AC analysis consists of the FFT display and THD analysis. For THD analysis to work, the input must be a
sine wave below half the Nyquist frequency, since the THD analyzer needs at least one harmonic to work
from. The THD analyzer uses an automatic tone-detection algorithm, which searches for the highest
harmonic and uses that for THD analysis. The frequency it detects is shown in the indicator marked Tone
Freq. This frequency may not be exactly what your oscillator is set for, but it should generally be very
close.
For DC analysis, the program provides DC RMS noise (standard deviation), peak amplitude, and a DC
level meter. A histogram is also provided; this is visible in the left tab. Basic DC measurements work best
when the ADC is driven by an amplifier or stable voltage source; shorting the inputs also works.
Kit Operation
6.3.1.2 Record Mode
To record data, go to the Record To File tab and do the following:
1. If Acquire is on, turn it off. You cannot start recording when Acquire is on.
2. Set the Conversion Mode and Sample Rate fields to the settings you want to record with. The channel
selector has no effect for data recording.
3. Enter a path in the Destination File field. You can use the folder icon to browse for the file with a
standard file dialog. If the file you enter cannot be opened or created, the record button will be
disabled. If the path points to an existing file, the file will be overwritten when you activate recording.
4. Enter a number of samples to convert. You can enter this in time or number of samples; the other box
will update automatically. The number of samples is limited by available memory on the MMB0.
5. Click the record button. You will see the Samples Retrieved bar graph increase. When it reaches the
number of samples you selected, recording will stop and the record button will go dark.
After this, the file you selected will contain comma-separated decimal numbers collected from the ADCs.
The samples are written two to a line, with the sample from Channel 1 first, followed by a comma, followed
by the sample from Channel 2. This kind of file can easily be imported into a spreadsheet, among other
applications.
6.3.1.3 Configuration
You can set the sample rate and conversion mode. Sample rate and conversion mode are always the
same for each ADS1271 being evaluated; you cannot set one channel to a different parameter.
The ADS1271's three conversion modes are selected from the flip-menu labelled Conversion Mode.
The ADS1271 clock is normally generated by a PLL synthesizer on the MMB0. The synthesizer cannot
synthesize all frequencies precisely; the software will come as close as it can, but in some cases the
sample rate will be slightly off.
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EVM Bill of Materials and Schematic
When you change the sample rate, you may find the value clamped or altered. The limits are different for
high-speed mode: in that mode, the maximum sampling rate is approximately 105ksps, but in the other
modes, it is approximately 52.5ksps. If you have the sampling rate set too high when you switch to
another mode, the program will automatically reduce the rate to the maximum rate allowed for that mode.
Note that the block size does not change. When you reduce the sampling rate, waveforms will appear to
go up in frequency.
7 EVM Bill of Materials and Schematic
The following table contains a complete bill of materials for the modular ADS1271EVM.
Designators Description Manufacturer Mfg. Part Number
R15, R16, R17, R18, R23, 47 Ω 1/8W 5% Chip Resistor Panasonic ERJ-3GEYJ470V
R24, R25, R26
R7, R8, R9, R10, R11, R12, 1K Ω 1/16W 1% Chip Resistor Panasonic ERJ-3EKF1001V
R13, R14
R2 10K Ω 1/10W 5% Chip Resistor Panasonic ERJ-3GEYJ103V
R1 24.9K Ω 1/16W 1% Chip Resistor Panasonic ERJ-3EKF2492V
R3, R4, R21, R22 47K Ω 1/10W 5% Chip Resistor Panasonic ERJ-3GEYJ473V
R5, R6 100K Ω 1/10W 5% Chip Resistor Panasonic ERJ-3GEYJ104V
R19, R20 470K Ω 1/10W 5% Chip Resistor Panasonic ERJ-3GEYJ474V
C20, C21, C22, C23 100pF 50V Ceramic TDK C1608C0G1H101JT
C6, C7, C8, C9, C24, C25 1nF 50V Ceramic TDK C1608C0G1H102JT
C28 0.01µF 50V Ceramic TDK C1608X7R1H103KT
C26, C27, C30, C31 0.1µF 50V Ceramic TDK C1608X7R1H104KT
C1, C3, C4, C5, C29 1µF 16V Ceramic TDK C1608X7R1C105KT
C13, C14, C15, C16, C18, 10µF 6.3V Ceramic TDK C2012X5R0J106MT
C19 Chip Capacitor, ± 20%, X5R
C10, C11, C12, C17 10µF 25V Ceramic TDK C3225X7R1E106MT
C2 100µF 10V Low ESR Kemet T520D107M010ASE055
U1 Precision Voltage Reference Texas Instruments REF1004I-2.5
U2, U3 Precision Voltage Reference Texas Instruments REF3125AIDBZ
U4 Precision Operational Amplifier Texas Instruments OPA350UA
U5, U6 Fully Differential Amplifier Texas Instruments OPA1632DGN
U7, U8 Precision Delta-Sigma ADC Texas Instruments ADS1271IPW
U9, U10 Dual Analog Switch Texas Instruments SN74LVC2G66DCT
U11 LDO Voltage Regulator, Texas Instruments TPS1550DCK
U12 Single, 2-Line to 1 Data Selec- Texas Instruments SN74LVC2G157DCT
U13 3.3V Oscillator CTS CB3LV-5I-27-M0000
U15, U16 Dual Split Rail Level Shifter Trans- Texas Instruments SN74AVC2T45DCT
U17, U18 Split Rail Level Shifter Transceiver Texas Instruments SN74AVC1T45DBV
Table 9. ADS1271EVM Bill of Materials
Chip Capacitor, ± 5%, C0G
Chip Capacitor, ± 5%, C0G
Chip Capacitor, ± 5%, X7R
Chip Capacitor, ± 10%, X7R
Chip Capacitor, ± 10%, X7R
Chip Capacitor, ± 20%, X5R
Tantalum Capacitor, ± 20%
High Input Voltage
tor/Multiplexer
ceiver
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Designators Description Manufacturer Mfg. Part Number
U19 Dual Split Rail Level Shifter Trans- Texas Instruments SN74AVCH2T45DCT
U20 Tri-State Buffer Texas Instruments SN74LVC1G125DBV
J1A, J2T 20-pin SMT Plug Samtec TSM-110-01-L-DV-P
J1B, J2B 20-pin SMT Socket Samtec SSW-110-22-F-D-VS-K
J3A 10-pin SMT Plug Samtec TSM-105-01-L-DV-P
J3B 10-pin SMT Socket Samtec SSW-105-22-F-D-VS-K
J4, J5 Terminal Strip, 5 pin (5x1), Right Samtec TSW-105-08-L-S-RA
J6 Terminal Strip, 16-pin (8x2) Samtec TSW-108-07-L-D
J7 Terminal Strip, 4-pin (2x2) Samtec TSW-102-07-L-D
S1, S2, S3, S4, S5, S6 Dual Pole 3 Position Switch E-Switch EG2305A
S7 SPDT Switch Tyco-Alcoswitch SLS121PC
TP1 Miniature Test Point Terminal Keystone Electronics 5000
7.1 ADS1271EVM Schematic
The schematic diagram is provided as a reference.
EVM Bill of Materials and Schematic
Table 9. ADS1271EVM Bill of Materials (continued)
ceiver
ADS1271EVM PCB Texas Instruments 6466987
Angle
Header Shorting Block Samtec SNT-100-BK-T
ADS1271EVM & ADS1271EVM-PDKSBAU107 – November 2004 13
4
1
3
FMTSEL
J7
1 2
3 4
A12A2
GND
VCCA
JPR-2X2
VCCB8B17B26DIR
U15
SN74AVC2T45DCT
5
FORMAT
MODE0 MODE
CLK
FMTSEL
1
U16
DVDD
3
A12A2
VCCA
VCCB8B17B26DIR
DOUT1
FSYNC1
4
GND
5
2
3
1
A
GND
VCCA
B4DIR5VCCB
SN74AVC2T45DCT
U17
6
DVDD
FSYNC1
FSDIR
5
4
6
B
DIR
VCCB
VCCA1GND2A
SN74AVC1T45DBV
U18
3
DVDD
SCLK
6
5
8
B17B2
DIR
VCCB
A12A2
VCCA
SN74AVC1T45DBV
GND
U19
1
4
3
DVDD +3.3VD
SYNC_1
DIN2
SCLK
DVDD
2
6
4
8
1B
2B
VCC
GND
1A
2C
2A
1C
U10
SN74AVCH2T45DCT
7
CLKRMODE
SN74LVC2G66DCT
1
3
5
FSYNC1 FSYNC2
FSDIR
CLK
1
3
EXTCLK
OBCLKSEL
CTS_CB3LV-3C-25.0000-T
R20
470K
OBCLK
4
2
6
A1B
A/B
GND
Y
Y
G
VCC
U12
DVDD
SN74LVC2G157DCT
3
5
7
8
C29
1U
DOUT1
MODE
TP1
C16
10U
ADCDVDD1
FSYNC2
CLK
12
5
6
7
13
4
ADCAVDD1
10
CLK
DVDD
MODE
FORMAT
SYNC/PDWN
DRDY/FSYNC
AINP1AINN2AGND
AVDD
VREFN15VREFP
16
100N
C26
U20
SN74LVC1G125DBV
53
DVDD
1
R3
47K
DVDD
2 4
MODE0
MODE1
U7
C15
10U
CLK
DIN2
DIN1
C19
12
14
8
9
11
DIN
SCLK
DOUT
DGND
3
100P
C21
C24 1N
5
6
7
MODE
FORMAT
SYNC/PDWN
VREFN15VREFP
8
10
11
SCLK
DRDY/FSYNC
AINP1AINN2AGND
13
CLK
DVDD
AVDD
ADS1271PW
U8
4
16
100N
C14
10U
C27
C25 1N
100P
ADCAVDD2
C20
10U
14
9
DIN
DOUT
C23
C22
ADCDVDD2
DGND
DVDD
ADCDVDD1
ADCDVDD2
ADCAVDD1
ADS1271PW
ADCAVDD2
3
J6
1 2
3 4
5 6
100P
100P
7 8
DVDD +5V
JPR-2X8
9 10
11 12
13 14
15 16
AGNDIN
D1V8IN
DGNDIN
-AVDD
8
2
10
4
6
-VA
VD1
-5VA
+5VD
AGND
+VA
+5VA
DGND
+1.8VD
J3
+AVDD
+3.3VD
POWERHDR
1
3
5
7
9
J3A (TOP) = SAM_TSM-105-01-L-DV-P
J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K
74
+5V
R1
+5V
+3.3VD
S3
C2
100U
AUXREF1P
REFP
OBREF
6
U4
OPA350UA
2
3
C1
1U 16V X7R
R2
10K
8
24.9K 1%
6
2
OUT
IN
GND
U2
REF3125AIDBZ
1
3
C3
1U
4
U1
S4
SW-DP3T
AUXREF1N
REFN
1K
R10
C6
AIN0P
47
R15
C10
10U
2
5
+AVDD
3
-
VOCM
+
1N C0G
U5
8
R7
1K
R5
REF1004I-2.5
SW-DP3T
S5
AIN0N
AUX1P
AUX1N
AUXREF2P
REFP
C13
10U
S6
SW-DP3T
AUXREF2N
AMPOUT2P
REFN
AIN1P
SW-DP3T
AMPOUT2N
AIN1N
AUX2P
AUX2N
C18
10U
2
R16 47
C11
10U
4
6
-AVDD
+
-
R11
C7
1N C0G
OPA1632
C12
R12
1K
+AVDD
1K
C8
1N C0G
U6
1
R18 47
R17 47
10U
3
8
C17
2
5
-
VOCM
+
10U
4
6
-AVDD
+
C9
OPA1632
1
OUT
IN
GND
U3
REF3125AIDBZ
1
R14
1N C0G
3
1K
C5
1U
5
OUT
R8
1K
100K
R9
1K
R13
1K
R6
100K
IN4GND
U11
TPS71550DCK
2
C4
1U
+AVDD
S1
AIN0P
SW-DP3T
AIN0N
S2
AIN1P
SW-DP3T
AIN1N
+5V
AIN0PAIN0N
AN0+2AN1+4AN2+6AN3+8AN4+10AN5+12AN6+14AN7+
AN0-1AN1-3AN2-5AN3-7AGND9AGND11AGND
J1
REFN
REFP
20
18
16
REF-
REF+
AGND17AGND
VCOM
ANALOGHDR
15
19
13
AUXREF1P
AUXREF1N
AUX1P
AUX1N
12345
J4
D
HEADER-5
C
AUX2P
12345
J5
AUX2N
AUXREF2P
AUXREF2N
HEADER-5
AIN1N AIN1P
B
FCC Warnings
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency
energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules,
which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which case the user at his own expense will be required to
take whatever measures may be required to correct this interference.
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY
and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of
required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically
found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User's Guide, the kit may be returned within 30 days
from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER
TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant
or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user's responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE Liable to the other FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.
Please read the EVM User's Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User's Guide prior to
handling the product. This notice contains important safety information about temperatures and voltages. For further safety
concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 1.8 V to 5 V and the output voltage range of 0 V to 5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30 ° C. The EVM is designed to
operate properly with certain components above 85 ° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2004, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
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DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
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