TEXAS INSTRUMENTS ADS1271EVM, ADS1271EVM-PDK Technical data
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This user's guide describes the characteristics, operation, and use of the
ADS1271EVM, both by itself and as part of the ADS1271EVM-PDK. This EVM is a
24-bit analog-to-digital converter evaluation module. A complete circuit description,
schematic diagram, and bill of materials are also included.
The following related documents are available through the Texas Instruments web site
at www.ti.com .
User's Guide
SBAU107 – November 2004
ADS1271EVM & ADS1271EVM-PDK
EVM-Compatible Device Data Sheets
Device Number
ADS1271 SBAS306
OPA350 SBOS099B
OPA1632 SBOS286
REF1004 SBVS002
REF3125 SBVS046A
SN74AVC1T45 SCES530C
SN74AVC2T45 SCES531D
SN74LVC1G125 SCES223L
SN74LVC2G66 SCES325G
SN74LVC2G157 SCES207I
TPS71550 SLVS338H
Contents
1 EVM Overview ............................................................................................................... 2
2 Analog Interface .............................................................................................................. 2
3 Digital Interface .............................................................................................................. 3
4 Power Supplies .............................................................................................................. 4
5 EVM Operation ............................................................................................................... 6
6 Kit Operation ................................................................................................................. 8
7 EVM Bill of Materials and Schematic .................................................................................... 12
Literature
List of Figures
1 ADS1271EVM Switch and Jumper Locations ............................................................................ 6
2 ADS1271EVM-PDK Block Diagram ...................................................................................... 9
3 Default Software Screen .................................................................................................. 10
List of Tables
1 Analog Interface Pinout (J1) ................................................................................................ 3
2 Auxiliary Analog Input 1 Pinout (J4) ....................................................................................... 3
3 Auxiliary Analog Input 2 Pinout (J5) ....................................................................................... 3
ADS1271EVM & ADS1271EVM-PDKSBAU107 – November 2004 1
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EVM Overview
1 EVM Overview
1.1 Features
1.2 Introduction
4 Digital Interface Pinout (J2) ................................................................................................. 4
5 Power Supply Pinout ........................................................................................................ 4
6 Reference Selection Options - S3 and S5 ................................................................................ 5
7 Buffer Amplfier Options - S1 and S2 ...................................................................................... 6
8 ADC Analog Input Options - S4 and S6 .................................................................................. 6
9 ADS1271EVM Bill of Materials ........................................................................................... 12
• Full-featured evaluation board for the ADS1271 24-bit Analog-to-Digital Converter
• Two ADS1271 converters on board illustrate use of daisy-chain mode
• On-board reference and oscillator circuits
• Modular design for use with a variety of DSP and microcontroller interface boards.
• ADS1271EVM-PDK is a complete evaluation kit, which includes a USB-based motherboard and
evaluation software for use with a personal computer running Microsoft Windows™ operating systems.
The ADS1271EVM is built in Texas Instruments' modular EVM form factor, which allows direct evaluation
of the ADS1271 performance and operating characteristics, and eases software development and system
prototyping. This EVM is compatible with the 5-6K Interface Board (SLAU104) from Texas Instruments
and additional third-party boards such as the HPA449 demonstration board from SoftBaugh, Inc.
(www.softbaugh.com ) and the Speedy33™ from Hyperception, Inc. (www.hyperception.com ).
The ADS1271EVM-PDK is a complete evaluation/demonstration kit, which includes a USB-enabled
DSP-based motherboard (the MMB0) and evaluation software for use with a PC.
2 Analog Interface
The ADS1271EVM features several analog input options. Signals can be routed directly to the converters
or can pass through the on-board buffer amplifiers (U5, U6). Signals can be applied to the board through
the standard modular EVM analog connector (J1) or brought in through the auxiliary input connectors (J4,
J5). A set of switches selects which analog connector source is used and whether the buffer amplifiers are
in the signal path. These switches enable several configurations for evaluation. Switch operation and
analog path configuration are described in Section 5.1 .
For maximum flexibility, the ADS1271EVM is designed for easy interfacing to multiple analog sources.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,
dual-row, header/socket combination at J1. This header/socket provides access to the analog input pins of
the ADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options. Table 1 through Table 3 summarize the standard and auxiliary analog pinout
configurations.
Speedy33 is a trademark of Hyperception, Inc..
Windows is a trademark of Microsoft Corp..
WinZip is a trademark of WinZip Computing, Inc..
2 ADS1271EVM & ADS1271EVM-PDK SBAU107 – November 2004
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Table 1. Analog Interface Pinout (J1)
Pin Number Signal Description
J1.1 AIN0N ADS1271 (U7) AINN
J1.2 AIN0P ADS1271 (U7) AINP
J1.3 AIN1N ADS1271 (U8) AINN
J1.4 AIN1P ADS1271 (U8) AINP
J1.5 Unused
J1.6 Unused
J1.7 Unused
J1.8 Unused
J1.15 Unused
J1.18 REF(-) External reference source low side
J1.20 REF(+) External reference source input (2.5V NOM)
J1.9-J1.19 (odd) GND Analog ground connections (except J1.15)
J1.10-J1.16 (even) Unused
Table 2. Auxiliary Analog Input 1 Pinout (J4)
Pin Number Signal Description
J4.1 AUX1P Auxiliary Signal Input 1 - Positive terminal
J4.2 AUX1N Auxiliary Signal Input 1 - Negative terminal
J4.3 AUXREF1P Auxiliary Reference Input 1 - Positive terminal
J4.4 AUXREF1N Auxiliary Reference Input 1 - Negative terminal
J4.5 GND Ground
Digital Interface
3 Digital Interface
Table 3. Auxiliary Analog Input 2 Pinout (J5)
Pin Number Signal Description
J5.1 AUX2P Auxiliary Signal Input 2 - Positive terminal
J5.2 AUX2N Auxiliary Signal Input 2 - Negative terminal
J5.3 AUXREF2P Auxiliary Reference Input 2 - Positive terminal
J5.4 AUXREF2N Auxiliary Reference Input 2 - Negative terminal
J5.5 GND Ground
The ADS1271EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J2. This header/socket provides access to the digital control and serial data pins of the
ADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector
options.
Because the ADS1271 devices are capable of daisy-chaining, this EVM has been designed to permit
stacking; up to 4 EVMs can be stacked, allowing for 8 devices to be placed in a signal chain. To
accomodate stacking of EVMs, J2 has some different connections on the top and the bottom side of the
board. Differences between top and bottom connectors are highlighted in Table 4 .
SBAU107 – November 2004 3ADS1271EVM & ADS1271EVM-PDK
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Power Supplies
Table 4. Digital Interface Pinout (J2)
Pin Number Signal Description
J2.1 SYNC Synchronization Control
J2.2 MODE0 0 = High-Speed Mode
J2.3 CLKX CLKXMODE = 1: master clock output
J2.4 DGND Digital ground
J2.5 SCLK Serial Clock
J2.6 MODE1 0 = High-Resolution Mode
J2.7 Unused.
J2.8 FSDIR Indicates FSR direction:
J2.9 Top: FSOUT FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connected
Bottom: FSR FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8
J2.10 DGND Digital ground
J2.11 Unused
J2.12 CLKRMODE 0 = Use CLKR for SPI Clock
J2.13 Top: DIN Top: Serial data input
Bottom: DOUT Bottom: Serial data output
J2.14 CLKXMODE 0 = CLKX is High Z
J2.15 Unused
J2.16 SCL I2C bus serial clock
J2.17 EXTCLK External ADC clock input
J2.18 DGND Digital ground
J2.19 OBCLKSEL Onboard Clock Select:
J2.20 SDA I2C bus data line
1 = Low-Power Mode
(In either case, only if Mode1=1)
CLKXMODE = 0: no connection
1 = Mode determined by MODE0
0 = Output (DRDY in SPI mode)
1 = Input (FSYNC mode)
1 = Use ADC Clock for SPI clock
1 = CLKX outputs ADC master clock
High to select onboard clock instead of external clock.
4 Power Supplies
J3 provides connection to the common power bus for the ADS1271EVM. Power is supplied on the pins
listed in Table 5 .
Table 5. Power Supply Pinout
Signal Pin Number Signal
+AVDD: +15V to power buffer amplifier section 1 2 –AVDD: –15V to power buffer amplifier section
+5VA 3 4 Unused
DGND 5 6 AGND
+1.8VD 7 8 Unused
+3.3VD 9 10 +5VD
ADS1271EVM & ADS1271EVM-PDK4 SBAU107 – November 2004
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4.1 ADC Power
Power Supplies
When power is supplied to J3, J6 allows for either 3.3V or 1.8V to be applied to the digital sections of the
ADS1271. J6 also provides for a method of measuring AVDD and DVDD supply currents if the shunts on
J6.1-2, J6.3-4, J6.5-6, and J6.7-8 are removed and a current meter is connected between the appropriate
pins. See the schematic and printed circuit board silkscreen for details.
Power for the ADS1271 analog supply voltage (AVDD) comes from +5V
, which is supplied through J3.3.
A
The shunt from J6 pins 1 to 2 applies this supply to the U7 ADS1271 device, while the shunt from J6 pins
5 to 6 applies this supply to the U8 ADS1271.
The ADS1271 digital supply voltage (DVDD) is selected using J6. When a shunt is applied from J6 pins 9
to 10, +1.8VD is selected, and this power comes from J3.7. If a shunt is placed from J6 pins 11 to 12 (the
default factory setting), +3.3V
is selected, which is provided from J3.9. J6 pins 13 and 15 provide a
D
means of connecting analog and digital grounds to the EVM; these grounds come from J3.6 and J3.5,
respectively. These grounds are always connected together at the EVM.
CAUTION
Verify that all power supplies are within the safe operating limits shown on
the ADS1271 data sheet before applying power to the EVM. Note that a
shunt should only be connected between J6 pins 9 and 10 OR pins 11 and
12, but never both; doing so would short the +3.3V supply to the +1.8V
digital supply.
4.2 Stand-Alone Operation
When used as a stand-alone EVM, the analog power can be applied to J6.2 and J6.6, referenced to
J6.13. DVDD can be applied to J6.4 and J6.8, referenced to J6.15. Note that this EVM uses only a single
ground plane.
4.3 Reference Voltage
The ADS1271 requires an external voltage reference. Two switches, S3 and S5, select the source of the
reference for the two ADS1271s on the EVM. An external reference may be supplied through J1 pin 20 on
the ADS1271EVM, or through J4 and J5, the auxiliary analog input connectors. A 2.5V reference is
provided on the EVM for convenience. These different reference sources can be selected using S3 and
S5, as shown in Table 6 .
S3/S5 Position Reference Inputs
Left Onboard 2.5V reference
Middle External Reference from J1.20 (REFP) referenced to J1.18
Right S3: AUXREF1 from J4.3 referenced to J4.4
CAUTION
Verify that the external reference voltage is within the safe operating limits
shown on the ADS1271 data sheet before applying power to the EVM.
Table 6. Reference Selection Options - S3 and S5
(REFN)
S5: AUXREF2 from J5.3 referenced to J5.4
ADS1271EVM & ADS1271EVM-PDKSBAU107 – November 2004 5
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