TEXAS INSTRUMENTS ADS1271 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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FEATURES

D 105kSPS Data Rate D AC Performance:

51kHz Bandwidth 109dB SNR (High-Resolution Mode)

−105dB THD

D DC Accuracy:

1.8µV/°C Offset Drift 2ppm/°C Gain Drift

D Selectable Operating Modes:

High-Speed: 105kSPS Data Rate High-Resolution: 109dB SNR Low-Power: 35mW Dissipation

D Power-Down Control D Digital Filter:

Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB

D Internal Offset Calibration On Command D Selectable SPIt or Frame Sync Serial In terface D Designed for Multichannel Systems:

Daisy-Chainable Serial Interface Easy Synchronization

D Simple Pin-Driven Control D Specified fro m −40°C to +105°C D Analog Supply: 5V D Digital Supply: 1.8V to 3.3V

APPLICATIONS

D Vibration/Modal Analysis D Acoustics D Dynamic Strain Gauges D Pressure Sensors D Test and Measurement

DESCRIPTION

The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. The ADS1271 provides a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple.

Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for DC measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. The ADS1271 combines these converters, allowing high-precision industrial measurement with excellent DC and AC specifications ensured over an extended industrial temperature range.

Three operating modes allow for optimization of speed, resolution, and power. A selectable SPI or a frame-sync serial interface provides for convenient interfacing to microcontrollers or DSPs. All operations, including internal offset calibration, are controlled directly by pins; there are no registers to program.

VREFP VREFN AVDD DVDD

SYNC/PDWN MODE

CLK DRDY/FSYNC

SCLK DOUT DIN FORMAT

AINP

AINN

∆Σ

Modulator

Digital

Filter

Control

Logic

Serial

Interface

DGNDAGND

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Input Current

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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ABSOLUTE MAXIMUM RATINGS

over opera t i n g f r e e - a i r t e m p e r a t ure range u n l e s s o t h e r w i s e n o t e d

ADS1271 UNIT

AVDD to AGND −0.3 to +6.0 V DVDD to DGND −0.3 to +3.6 V AGND to DGND −0.3 to +0.3 V

100, Momentary mA

10, Continuous mA Analog Input to AGND −0.3 to AVDD + 0 .3 V Digital Input or Output to DGND −0.3 to DVDD + 0.3 V Maximum Junction Tem perature +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C Lead Temperature (soldering, 10s) +300 °C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only , an d functional operation of the device at these or any other conditions beyond those specified is not implied.

(1)

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more susceptible t o damage because very small parametric changes could cause the device not to meet its published specifications.

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Differential input

impedance

DATA

Data rate (f

DATA

)

Offset error

Noise Power-supply

Power-supply f = 60Hz

Signal-to-noise ratio

(SNR)

(2)

Stop band Group delay

Group delay Settling time (latency)

Settling time (latency)

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

PARAMETER TEST CONDITIONS MIN TYP MAX

Analog Inputs

Full-scale input voltage (FSR) Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 V Common-mode input voltage VCM = (AINP + AINN)/2 2.5 V

DC Performance

Resolution No missing codes 24 Bits

Data rate (f

Integral nonlinearity (INL) Differential input, VCM = 2.5V ± 0.0006 ± 0.0015 % of FSR

Offset drift 1.8 µV/_C Gain error 0.1 0.5 % Gain error drift 2 ppm/°C

Noise

Common-mode rejection fCM = 60Hz 90 100 dB

rejection

AC Performance

(2)

(SNR) (unweighted)

Total harmonic distortion (THD) Spurious free dynamic range −108 dB Passband ripple ±0.005 dB Passband 0.453 f

−3dB Bandwidth 0.49 f Stop band attenuation 100 dB

Stop band

(1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signals.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

)

(1)

High-Speed mode 16.4 kΩ High-Resolution mode 16.4 kΩ Low-Power mode 32.8 kΩ

High-Speed mode 105,469 SPS High-Resolution mode 52,734 SPS Low-Power mode 52,734 SPS

High-Speed mode Without calibration 0.150 1 mV

High-Speed mode Shorted input 9.0 20 µV, rms High-Resolution mode 6.5 µV, rms Low-Power mode 9.0 µV, rms

AVDD DVDD

High-Speed mode 99 106 dB High-Resolution mode 109 dB Low-Power mode 106 dB

(3)

High-Speed mode 0.547 f High-Resolution mode 0.547 f Low-Power mode 0.547 f High-Speed and

Low-Power modes High-Resolution mode 39/f High-Speed and

Low-Power modes High-Resolution mode Complete settling 78/f

REF

VIN = (AINP – AINN) ±V

With calibration On the level of the noise

VIN = 1kHz, −0.5dBFS −105 −95 dB

Complete settling 76/f

= 27MHz, and V

CLK

DATA DATA DATA

= +2.5V , unless otherwise noted.

REF

ADS1271

REF

80 dB 80 dB

DATA DATA

63.453 f

127.453 f

63.453 f

38/f

DATA DATA DATA DATA

DATA

UNITS

Hz Hz

Hz Hz Hz

s s s s

(1)

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Reference Input

impedance

Serial clock rate

SCLK

Frame-Sync format

AVDD current Power-Down mode

DVDD current Power-Down mode

Power dissipation

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

PARAMETER

Voltage Reference Inputs

Reference input Voltage (V Negative reference input (VREFN) AGND − 0.1 VREFP − 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V

Digital Input/Output

Input leakage Master clock rate (f

Serial clock rate (f

SCLK

Power Supply

AVDD 4.75 5 5.25 V DVDD 1.65 3.6 V

AVDD current

DVDD current

Power dissipation

Temperature Range

Specified −40 +105 _C Operating −40 +105 _C Storage −60 +150 _C (1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signals.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

(4)

CLK

(5)

)

) V

REF

High-Speed mode 4.2 kΩ High-Resolution mode 4.2 kΩ Low-Power mode 8.4 kΩ

) 1 27 MHz

SPI format 24 f

Frame-Sync format

High-Speed mode 17 25 mA High-Resolution mode 17 25 mA Low-Power mode 6.3 9.5 mA

High-Speed mode 3.5 6 mA High-Resolution mode 2.5 5 mA Low-Power mode 1.8 3.5 mA

High-Speed mode 92 136 mW High-Resolution mode 90 134 mW Low-Power mode 35 54 mW

REF

= VREFP – VREFN 0.5 2.5 2.65 V

REF

IOH = 5mA 0.8 DVDD DVDD V IOL = 5mA DGND 0.2 DVDD V 0 < VIN

DIGITAL

High-Speed mode 64 f High-Resolution mode 128 f Low-Power mode 64 f

T ≤ 105°C 1 70 µA T ≤ 85°C 1 10 µA

T ≤ 105°C, DVDD = 3.3V 1 70 µA T ≤ 85°C, DVDD = 3.3V 1 20 µA

< DVDD ±10 µA

= 27MHz, and V

CLK

= +2.5V , unless otherwise noted.

REF

ADS1271

MAXTYPMINTEST CONDITIONS

0.7 DVDD DVDD V DGND 0.3 DVDD V

64 f

128 f

64 f

CLK DATA DATA DATA

DATA DATA DATA DATA

UNITS

MHz MHz MHz MHz

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MODE5Digital Input

PIN ASSIGNMENTS

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TSSOP (PW) PACKAGE

(TOP VIEW)

AINP

AINN AGND AVDD

MODE

FORMAT

SYNC/PDWN

DIN

1 2 3 4

ADS1271

5 6 7 8

VREFP

VREFN

DGND

DVDD

CLK

SCLK

DRDY/FSYNC

DOUT

Terminal Functions

NAME NO. FUNCTION DESCRIPTION

AINP 1 Analog Input Positive analog input AINN 2 Analog Input Negative analog input AGND 3 Analog Input Analog ground AVDD 4 Analog Input Analog supply MODE 5 Digital Input MODE = 0: High-Speed mode

MODE = float: High-Resolution mode MODE = 1: Low-Power mode

FORMAT 6 Digital Input FORMAT = 0: SPI

FORMAT = 1: Frame-Sync SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low DIN 8 Digital Input Data input for daisy-chain operation DOUT 9 Digital Output Data output DRDY/FSYNC 10 Digital

Input/Output SCLK 11 Digital Input Serial clock for data retrieval CLK 12 Digital Input Master clock DVDD 13 Digital Input Digital supply DGND 14 Digital Input Digital ground VREFN 15 Analog Input Negative reference input VREFP 16 Analog Input Positive reference input

If FORMAT = 0 (SPI), then pin 10 = DRDY output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input



CONV

DATA

CONV

Conversion period (1/f

DATA

)

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TIMING CHARACTERISTICS: SPI FORMAT

CLK

DRDY

SCLK

DDO

DOUT

DIN

Bit 23 (MSB) Bit 22 Bit 21

TIMING REQUIREMENTS: SPI FORMAT

For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

(1)

DDO

(1)

SPW

DOHD

DOPD

DIST

DIHD

(1)

Load on DRDY and DOUT = 20pF.

CLK period (1/f

) 37 1000 ns

CLK

CLK positive or negative pulse width 15 ns

High-Speed mode 256 CLK periods

Conversion period (1/f

High-Resolution mode 512 CLK periods

)

Low-Power mode 512 CLK periods Falling edge of CLK to falling edge of DRDY 8 ns Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 ns Valid DOUT to falling edge of DRDY 0 ns Falling edge of SCLK to rising edge of DRDY 8 ns SCLK period t SCLK positive or negative pulse width 12 ns

(1)

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(1)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

SPW

CPW

•••

CPW

DIST

CONV

DOHD

DIHD

SPW

DOPD

CLK

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FRAME

DATA

FRAME

Frame period (1/f

DATA

)

be continuously running)

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

CPW

•••

CPW

SPW

DIST

FRAME

FPW

DOHD

DIHD

SPW

DOPD

CLK

FSYNC

SCLK

DOUT

DIN

FPW

SPW

DDO

Bit 23(MSB) Bit 22 Bit 21

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

FPW

SPW

DOHD

DOPD

DDO

DIST

DIHD

(1)

The ADS1271 automatically detects either frame period.

(2)

Load on DOUT = 20pF.

CLK period (1/f

) 37 1000 ns

CLK

CLK positive or negative pulse width 15 ns Rising edge of CLK to falling edge of SCLK −2 8 ns

High-Speed mode 256 CLK periods

Frame period (1/f

High-Resolution mode 256 or 512

)

Low-Power mode 256 or 512

(1) (1)

FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns Rising edge of SCLK to rising edge of FSYNC 5 ns

SCLK period (SCLK must

High-Resolution mode τ

FRAME

Low-Power mode τ

High-Speed mode τ

SCLK positive or negative pulse width 0.4τ

(2)

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(2)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns

(2)

Valid DOUT to falling edge of FSYNC 0 ns

SCLK

/64 τ

FRAME

/128 τ

/64 τ

FRAME

0.6τ

SCLK

New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

CLK periods CLK periods

FRAME FRAME FRAME

periods periods periods

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OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

= 2.5V , unless otherwise noted.

REF

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High−Speed Mode

= 1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 1

High−Speed Mode

−

Shorted Input

2,097,152 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

10k 100k

High−Speed Mode

=1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

420k

High−Speed Mode Shorted Input

360k

2,097,152 Points

300k

240k

180k

120k

Number of Occurrences

60k

−50−45−40−35−30−25−20−15−

Frequency (Hz)

Figure 2

−

Output (µV)

10k 100k

101520253035404550

Figure 3

High−Resolution Mode

=1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 5

10k 100k

High−Resolution Mode

= 1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Figure 4

10k 100k

Frequency (Hz)

Figure 6

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OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISEH ISTOGRAM

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

REF



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

= 2.5V , unless otherwise noted.

High−Resolution Mode

−

Shorted Input 1,048,576 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 7

Low−Power Mode

=1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

10k 100k

210k

High−ResolutionMode Shorted Input

180k

1,048,576 Points

150k

120k

90k

60k

Number ofOccurrences

30k

−30−28−26−24−22−20−18−16−14−12−

Low−Power Mode

=1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

−8−6−4−

Output (µV)

02468

Figure 8

Frequency (Hz)

1012141618202224262830

10k 100k

Figure 9

Low−Power Mode

−

Shorted Input

1,048,576 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 11

10k 100k

200k

Low−Power Mode

180k

Shorted Input 1,048,576 Points

160k 140k 120k 100k

80k 60k

Number of Occurrences

40k 20k

−50−45−40−35−30−25−20−15−

Figure 10

−

Output (µV)

Figure 12

101520253035404550



TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

= 2.5V , unless otherwise noted.

REF

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High−Speed Mode

=−0.5dBFS

−

100

−

120

10 100 1k

High−Resolution Mode

=−0.5dBFS

−

100

−

120

10 100 1k

vs FREQUENCY

THD+N

THD

Frequency (Hz)

Figure 13

vs FREQUENCY

THD+N

THD

Frequency (Hz)

Figure 15

10k 100k

High−Speed Mode

=1kHz

−

100

−

120

−

140

−

120−100

High−Resolution Mode

=1kHz

−

100

−

120

−

140

−

120−100

vs INPUT LEVEL

THD+N

THD

−

Input Amplitude (dBFS)

−

Figure 14

vs INPUT LEVEL

THD+N

THD

−

Input Amplitude (dBFS)

−

Figure 16

−

20 0

−

20 0

Low−Power Mode

=−0.5dBFS

−

100

−

120

10 100 1k

vs FREQUENCY

THD+N

THD

Frequency (Hz)

10k 100k

−

100

−

120

−

140

−

120−100

Low−Power Mode

=1kHz

Figure 17

vs INPUT LEVEL

THD+N

THD

−

Input Amplitude (dBFS)

−

Figure 18

−

20 0

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ABSOLUTE OFFSET DRIFT HISTOGRAM

GAIN DRIFT HISTOGRAM

OFFSETPOWER−ON WARMUP

GAIN ERROR POWER−ON WARMUP

UNCALIBRATED OFFSET HISTOGRAM

GAIN ERRORHISTOGRAM

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

REF



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

= 2.5V , unless otherwise noted.

30 Units, Basedon 20_CIntervals

Occurrences (%)

1 3 5 7 9 111315171921

Absolute Offset Drift (µV/_C)

Figure 19

40 30

−

Normalized Offset (

−

0102030405060

Response

Band

Time After Power−On (s)

High−SpeedMode DVDD = 3.3V

30 Units, Based on 20_C Intervals

Occurrences (%)

6.0−5.5−5.0−4.5−4.0−3.5−3.0−2.5−2.0−1.5−1.0−0.5

−

Gain Drift (ppm/_C)

0.5

1.0

1.5

2.0

2.5

3.0

Figure 20

8 6 4 2 0

−

Normalized Gain Error (ppm)

−

0102030405060

Response

Band

Time AfterPower−On (s)

High−Speed Mode DVDD = 3.3V

3.5

4.0

Figure 21

High−Speed Mode 30 Units

Units (%)

500−450−400−350−300−250−200−150−100

−

Uncalibrated Offset (µV)

Figure 23

−

Figure 22

High− Speed Mode 30 Units

Units (%)

100

150

200

250

300

2350−2300−2250−2200−2150−2100−2050−2000−1950−1900−1850−1800−1750−1700−1650−1600

−

Gain Error(ppm)

Figure 24



REFERENCE INPUT DIFFERENTIAL IMPEDANCE

Reference Input Impedance (

)

REFERENCE INPUT DIFFERENTIAL IMPEDANCE

ANALOG INPUT DIFFERENTIAL IMPEDANCE

Analog Input Impedance (

)

ANALOG INPUT DIFFERENTIAL IMPEDANCE

Analog InputImpedance (

)

INTEGRAL NONLINEARITY vs TEMPERATURE

LINEARITY ERROR vs INPUT LEVEL

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

= 2.5V , unless otherwise noted.

REF

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Ω

4280

High−Speed and

4260

High−Resolution Modes

4240 4220 4200 4180 4160 4140 4120 4100

−40−

16550 16500 16450 16400 16350 16300 16250 16200 16150

−40−

vs TEMPERATURE

20 0 20 40 60 80 100

Temperature (_C)

Figure 25

vs TEMPERATURE

High−Speed and High−Resolution Modes

20 0 20 40 60 80 100

Temperature (_C)

Figure 27

120 125

)

Ω

Reference Input Impedance (

Ω

8900

8800

8700

8600

8500

8400

8300

8200

−40−

33200

33000

32800

32600

32400

32200

32000

−40−

vs TEMPERATURE

Low−Power Mode

20 0 20 40 60 80 100

Temperature (_C)

Figure 26

vs TEMPERATURE

Low−Power Mode

20 0 20 40 60 80 100

Temperature (_C)

Figure 28

120125

120 125

INL (ppm)

−40−

High−Resolution

High−Speed

Low−Power

20 0 20 40 60 80 100

Temperature (_C)

120125

Figure 29

High−Speed Mode

8 6 4 2 0

−

Linearity Error (ppm)

−

2.5−2.0 2.0

T=+105_C

T=+25_C

T=−40_C

−

1.5 1.5

−

1.0 1.0

0.5 0.50 (V)

Figure 30

T=+125_C

2.5

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NOISE vs AVDD

NOISE vs DVDD

NOISE vs TEMPERATURE

NOISE vs INPUT LEVEL

AVDD CURRENTvs TEMPERATURE

DVDD CURRENT vs TEMPERATURE

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

REF



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

= 2.5V , unless otherwise noted.

20 18 16 14

12 10

RMS Noise (

6 4 2 0

4.75 4.85 5.154.95 5.05 AVDD (V)

Figure 31

RMS Noise (

−40−

High−Speed

20 0 20 40 60 80 100

Temperature (_C)

High−Speed

Low−Power

High−Resolution

Low−Power

High−Resolution

5.25

120 125

20 18 16 14

12 10

RMS Noise (

6 4 2 0

1.6 2.0 2.21.8 3.2 3.42.4 2.6 2.8 3.0

High−Speed

Low−Power

DVDD (V)

Figure 32

20 18 16 14

High−Speed

12 10

RMS Noise (

6 4 2 0

−

2.5−2.0−1.5−1.0 1.51.0

−

0.5 0.50 (V)

High−Resolution

3.6

Low−Power

High−Resolution

2.52.0

Figure 33

22 20

High−Speed and

High−Resolution

16 14 12 10

Low−Power

AVDD Current(mA)

6 4 2 0

−40−

20 0 20 40 60 80 100

Temperature (_C)

Figure 35

120 125

DVDD Current (mA)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5 0

Figure 34

−40−

20 0 20 40 60 80 100

Temperature (_C)

Figure 36

High−Speed

High−Resolution

Low−Power

120125

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

OVERVIEW

The ADS1271 is a 24-bit, delta-sigma ADC. It offers the combination of outstanding DC accuracy and superior AC performance. Figure 37 shows the block diagram for the ADS1271. The ADS1271 converter is comprised of an advanced, 6th-order, chopper-stabilized, delta-sigma modulator followed by a low-ripple, linear phase FIR filter. The modulator measures the differential input signal, V

= (AINP – AINN), against the differential reference,

= (VREFP – VREFN). The digital filter receives the

REF

modulator signal and provides a low-noise digital output. To allow tradeoffs among speed, resolution, and power, three modes of operation are supported on the ADS1271: High-Speed, High-Resolution, and Low-Power. Table 1

VREFP

VREFN

REF

AINP

AINN

∆Σ

Modulator

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summarizes the performance of each mode. In High-Speed mode, the data rate is 105kSPS; in High-Resolution mode, the SNR = 109dB; and in Low-Power mode, the power dissipation is only 35mW.

The ADS1271 is configured by simply setting the appropriate IO pins—there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1271 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in multichannel systems.

SYNC/PDWN MODE CLK

Digital

Filter

SPI

Frame−

Sync

Serial

Interface

DRDY/FSYNC SCLK DOUT DIN FORMAT

Figure 37. Block Diagram

Table 1. Operating Mode Performance Summary

MODE DATA RATE (SPS) PASSBAND (Hz) SNR (dB) NOISE (µV

High-Speed 105,469 47,777 106 9.0 92

High-Resolution 52,734 23,889 109 6.5 90

Low-Power 52,734 23,889 106 9.0 35

) POWER (mW)

RMS

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High-Resolution

Low-Power

ANALOG INPUTS (AINP, AINN)

The ADS1271 measures the differential input signal V

= (AINP – AINN) against the differential reference

= (VREFP – VREFN). The most positive measurable

REF

differential input is +V positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is −V which produces the most negative digital output code of 800000h.

While the ADS1271 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is:

−0.1V < (AINN or AINP) < AVDD +0.1V

, which produces the most

REF

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

=1/f

OFF

SAMPLE

MOD

Figure 39. S1 and S2 Switch Timing for Figure 38

Table 2. Modulator Frequency for the Different

Mode and Format Settings



If either input is taken below –0.1V or above (AVDD + 0.1), ESD protection diodes on the inputs may turn on.

The ADS1271 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 38 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is di fferent. The timing for switches S1 and S2 is shown in Figure 39. The sampling time (t the inverse of modulator sampling frequency (f

SAMPLE

MOD

) is

) and is a function of the mode, format, and frequency of CLK, as shown in Table 2. When using the Frame-Sync format with High-Resolution or Low-Power modes, the ratio between f

MOD

and f

depends on the frame period that is set by

CLK

the FSYNC input.

AGND

AVDD

AINP

9pF

INTERFACE

MODE

High-Speed SPI or Frame-Sync f

FORMAT

SPI f

Frame-Sync f

SPI f

Frame-Sync f

CLK

MOD

CLK CLK

/4 or f

CLK

/8 or f

/4 /4

CLK

The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 40. Note that the effective impedance is a function of f

AINP

Zeff = 16.4kΩ×(6.75MHz/f

AINN

MOD

)

MOD

AINN

AVDDAGND

ESD Protection

Figure 38. Equivalent Analog Input Circuitry

Figure 40. Effective Input Impedances

The ADS1271 is a very high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1271 inputs. See the Application Information section for the recommended circuits.

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Low-Power

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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VOLTAGE REFERENCE INPUTS (VREFP, VREFN)

The voltage reference for the ADS1271 ADC is the differential voltage between VREFP and VREFN: V

= (VREFP−VREFN). The reference inputs use a

REF

structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 41. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 42.

VREFP

Figure 41. Equivalent Reference Input Circuitry

VREFP VREFN

Zeff = 4.2kΩ×(6.75MHz/f

Figure 42. Effective Reference Impedance

VREFN

Protection

)

MOD

AVDDAVDD

ESD

ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.1V, and likewise do not exceed AVDD by 0.1V:

−0.1V < (VREFP or VREFN) < AVDD + 0.1V

A high-quality reference voltage wi th the appropriate drive strength is essential for achieving the b est p erformance f rom the ADS1271. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits.

CLOCK INPUT (CLK)

The ADS1271 requires an external clock signal to be applied to the CLK input pin. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 47Ω series resistor will help.

The ratio between the clock frequency and output data rate is a function of the mode and format. Table 3 shows the ratios when the SPI format is selected. Also included in this table is the typical CLK frequency and the corresponding data rate. When High-Speed mode is used, each conversion takes 256 CLK periods. When High-Resolution or Low-Power modes are selected, the conversions take 512 CLK periods.

Table 4 shows the ratios when the Frame-Sync format is selected. When using the Frame-Sync format in either High-Resolution or Low-Power mode, the f

CLK/fDATA

can be 256 or 512. The ADS1271 automatically detects which ratio is being used. Using a ratio of 512 allows the CLK frequency to be reduced by a factor of two while maintaining the same data rate. The output data rate scales with the clock frequency. See the Serial Interface section for more details on the Frame-Sync operation.

ratio

MODE SELECTION f

High-Resolution 512 27 " 52,734

MODE SELECTION f

Table 3. Clock Ratios for SPI Format

CLK/fDATA

High-Speed 256 27 " 105,469

Low-Power 512 27 " 52,734

TYPICAL f

(MHz) " CORRESPONDING DA TA RATE (SPS)

CLK

Table 4. Clock Ratios for Frame-Sync Format

CLK/fFRAME

High-Speed 256 27 " 105,469

256 13.5 " 52,734 512 27 " 52,734 256 13.5 " 52,734 512 27 " 52,734

TYPICAL f

(MHz) " CORRESPONDING DA TA RATE (SPS)

CLK

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

MODE SELECTION (MODE)

The ADS1271 supports three modes of operation: High-Speed, High-Resolution, and Low-Power. The mode selection is determined by the status of the digital input MODE pin, as shown in Table 5. A high impedance, or floating, condition allows the MODE pin to support a third state. The ADS1271 constantly monitors the status of the MODE pin during operation and responds to a change in status after 12,288 CLK periods. When floating the MODE pin, keep the total capacitance on the pin less than 100pF and the resistive loading greater than 10MΩ to ensure proper operation. Changing the mode clears the internal offset calibration value. If onboard offset calibration is being used, be sure to recalibrate after a mode change.

When daisy-chaining multiple ADS1271s together and operating in High-Resolution mode (MODE pin floating), the MODE pin of e ach d evice m ust be isolated from o ne another; this ensures p roper d evice operation. T he MODE p ins can b e tied together for High-Speed and Low-Power modes.

Table 5. Mode Selection

MODE PIN ST ATUS MODE SELECTION

Logic Low (DGND) High-Speed

(1)

Floating

Logic High (DVDD) Low-Power

(1)

Load on MODE: C < 100pF, R > 10MΩ

High-Resolution

When using the SPI format, DRDY is held high after a mode change occurs until settled (or valid) data is ready, as shown in Figure 43.

In Frame-Sync format, the DOUT pin is held low after a mode change occurs until settled data is ready, as shown in Figure 43. Data can be read from the device to detect when DOUT changes to logic 1, indicating valid data.

FORMAT SELECTION (FORMAT)

To help connect easily to either microcontrollers or DSPs, the ADS1271 supports two formats for the serial interface: an SPI-compatible interface and a Frame-Sync interface. The format is selected by the FORMAT pin, as shown in Table 6. It is recommended that the FORMAT pin be directly tied to the appropriate voltage. If the status of this pin changes, perform a Sync operation afterwards to ensure proper operation.

Table 6. Format Selection

FORMAT PIN STATUS SERIAL INTERFACE FORMAT

Logic Low (DGND) SPI Logic High (DVDD) Frame-Sync

SPI

Format

Frame−Sync

Format

SYMBOL

MODE

CLK

ADS1271

Mode

DRDY

DOUT

NDR

High−Speed

Time to register MODE changes

Time for new data to be ready

Figure 43. Mode Change Timing

MIN TYP MAX UNITSDESCRIPTION

12,288

Low−Power

NDR

Low−Power Mode

ValidData Ready

NDR

Low−Power Mode

ValidDataonDOUT

128

CLK periods

Conversions

)

(1/f

DATA

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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SYNCHRONIZATION

The SYNC/PDWN pin has two functions. When pulsed, it synchronizes the start of conversions and, if held low for more than 219 CLK cycles (t Power-Down mode. See the Power-Down and Offset Calibration section for more details.

The ADS1271 can be synchronized by taking SYNC

/PDWN low. This stops the conversion process and resets the internal counters used by the digital filter. Return SYNC

/PDWN high on the rising edge of CLK to begin the conversion process. Synchronization allows the conversions to be aligned with an external event; for example, the changing of an external multiplexer on the analog inputs. It can also be used to synchronize the conversions of multiple ADS1271s.

), places the ADS1271 in

SYN

CLK

SYNC/PDWN

DRDY

SYN

••••••

In the SPI format, DRDY goes high as soon as

/PDWN is taken low, as shown in Figure 44. After

SYNC SYNC

/PDWN is returned high, DRDY stays high while the digital filter is settling. Once valid data is ready for retrieval, DRDY

goes low.

In the Frame-Sync format, DOUT goes low as soon as SYNC

/PDWN is taken low, as shown in Figure 45. After SYNC

/PDWN is returned high, DOUT stays low while the digital filter is settling. Once valid data is ready for retrieval, DOUT begins to output valid data. The device detects the state of the SYNC synchronizing multiple devices, set the SYNC

/PDWN pin on the falling edge. When

/PDWN pin high on the rising edge of SCLK to ensure all devices are restarted on the same S C L K p e r i o d . I t is recommended to leave FSYNC and SCLK running during a synchronization.

NDR

SYMBOL

SYN

NDR

SYMBOL

SYN

NDR

MIN TYP MAX UNITSDESCRIPTION

Synchronize pulse width

Time for new data to be ready

1 CLK periods

128

Figure 44. Synchronization Timing for SPI format

CLK

SYNC/PDWN

FSYNC

DOUT

Synchronize pulse width

Time for new data to be ready

••••••

SYN

NDR

MIN TYP MAX UNITSDESCRIPTION

1 CLK periods

128

Valid Data

129

Conversions

)

(1/f

DATA

Conversions

)

(1/f

DATA

Figure 45. Synchronization Timing for Frame-Sync Format

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

POWER-DOWN AND OFFSET CALIBRATION

In addition to controlling synchronization, the SYNC

/PDWN pin also serves as the control for Power-Down mode and offset calibration. To enter this mode, hold the SYNC/PDWN pin low for at least 219 CLK periods. While in Power-Down mode, both the analog and digital circuitry are completely deactivated. The digital inputs are internally disabled so that is not necessary to shut down CLK and SCLK. To exit Power-Down mode, return SYNC

The ADS1271 uses a chopper-stabilized modulator to provide inherently very low offset drift. To further minimize offset, the ADS1271 automatically performs an offset self-calibration when exiting Power-Down mode. When power down completes, the offset self-calibration begins with the inputs AINP and AINN automatically disconnected from the signal source and internally shorted together. There is no need to modify the signal source applied to the analog inputs during this calibration.

/PDWN high on the rising edge of CLK.

CLK

SYNC/PDWN

DRDY

PDWN

It is critical for the reference voltage to be stable when exiting Power-Down mode; otherwise, the calibration will be corrupted.

The offset self- calib r at ion on ly removes offset errors internal to the device, not offset errors due to external sources.

NOTE: When an offset self-calibration is performed, the resulting offset value will vary each time within the peak-to-peak noise range of the converter. In High-Speed mode, this is typically 178 LSBs.

The offset calibration value is cleared whenever the device mode is changed (for example, from High-Speed mode to High-Resolution mode).

When using the SPI format, DRDY

will stay high after exiting Power-Down mode while the digital filter settles, as shown in Figure 46.

When using the Frame-Sync format, DOUT will stay low after exiting Power-Down mode while the digital filter settles, as shown in Figure 47.

••••••

OFS

Post−Calibration Data Ready

Status

Converting Sync Power Down Converting

SYMBOL

SYNC/PDWN

PDWN pulse width to enter Power−Down mode

Time for offset calibrationand filtersettling

OFS

Figure 46. Power-Down Timing for SPI format

CLK

SYNC/PDWN

FSYNC

DOUT

Status

SYMBOL

PDWN

OFS

Converting Sync Power Down Converting

SYNC/PDWN Time for offset calibration and filter settling

PDWN

pulse width to enter Power−Down mode

Offset Cal and Filter Settling

MIN TYP MAX UNITSDESCRIPTION

256

••••••

OFS

Offset Cal and Filter Settling

MIN TYP MAX UNITSDESCRIPTION

CLK periods Conversions

)

(1/f

DATA

Post−Calibration Data

CLK periods Conversions

257256

(1/f

DATA

)

Figure 47. Power-Down Timing for Frame-Sync Format

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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POWER-UP SEQUENCE

The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. Once the supplies and the voltage reference inputs have stabilized, data can be read from the device.

FREQUENCY RESPONSE

The digital f ilter s ets t he o verall f requency r esponse. T he f ilter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple a nd h igh stopband attenuation. T he oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: f

MOD/fDATA

function of the selected mode, as shown in Table 7. f CLK/2 or CLK/4, depending on the mode.

Table 7. Oversampling Ratio versus Mode

MODE OVERSAMPLING RATIO (f

High-Speed 64

High-Resolution 128

Low-Power 64

MOD/fDATA

High-Speed and Low-Power Modes

The digital filter configuration is the same in both High-Speed and Low-Power modes with the oversampling ratio set to 64. Figure 48 shows the frequency response in High-Speed and Low-Power modes

normalized to f

Figure 49 shows the passband ripple. The transition from passband to stop band is illustrated in Figure 50. The overall frequency response repeats at 64x multiples of the modulator frequency f

, as shown in Figure 51. These

MOD

image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. However, with such a wide stopband, only a simple low-order, antialias filter is typically required in front of the ADS1271 inputs to limit out-of-band noise. See Table 8 for more detail.

−

Amplitude (dB)

−

100

−

120

−

140

0 0.2 0.6 0.8 1.0

Normalized Input Frequency (f

0.4

IN/fDATA

)

Figure 48. Frequency Response for High-Speed

and Low-Power Modes

) is a

MOD

)

DATA

0.02

−

0.02

−

0.04

−

Amplitude (dB)

0.06

−

0.08

−

0.10 0 0.1 0.3 0.4 0.5 0.6

0.2

Normalized Input Frequency (f

IN/fDATA

)

Figure 49. Passband Response for High-Speed

and Low-Power Modes

−

Amplitude (dB)

−

0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (f

IN/fDATA

)

Figure 50. Transition Band Response for

High-Speed and Low-Power Modes

−

Gain (dB)

−

100

−

120

−

140

−

160

016324864

Input Frequency (f

Figure 51. Frequency Response Out to f

High-Speed and Low-Power Modes

IN/fDATA

)

for

MOD

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ANTIALIAS

High-Resolution Mode

The oversampling ratio is 128 in High-Resolution mode. Figure 52 shows the frequency response in High-Resolution mode normalized to f

. Figure 53

DATA

shows the passband ripple, and the transition from passband to stop band is illustrated in Figure 54. The overall frequency response repeats at multiples of the modulator frequency f

, (128 × f

MOD

), as shown in

DATA

Figure 55. With such an extremely wide stop band, only a simple antialias filter is typically required in front of the ADS1271 inputs to limit out-of-band noise. See T able 8 for more detail.



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

−

Amplitude (dB)

−

0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (f

IN/fDATA

)

−

Amplitude (dB)

−

100

−

120

−

140

00.25 0.751 Normalized Input Frequency (f

0.50

IN/fDATA

)

Figure 52. Frequency Response for

High-Resolution Mode

0.02

−

0.02

−

0.04

Figure 54. Transition Band Response for

High-Resolution Mode

−

Gain (dB)

−

100

−

120

−

140

−

160

0 32 64 96 128

Normalized Input Frequency (fIN/f

Figure 55. Frequency Response out to f

High-Resolution Mode

DATA

)

MOD

Table 8. Antialias Filter Order Image Rejection

for

−

Amplitude (dB)

0.06

−

0.08

−

0.10 0 0.1 0.3 0.4 0.5 0.6

0.2

Normalized Input Frequency (f

Figure 53. Passband Response for

High-Resolution Mode

IN/fDATA

IMAGE REJECTION (dB)

FIL TER ORDER

at f

−3dB

HS, LP HR

DATA

)

1 39 45

)

2 75 87 3 111 129

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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PHASE RESPONSE

The ADS1271 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.

SETTLING TIME

As with frequency and phase response, the digital filter also determines settling time. Figure 56 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X axis is given in units of conversion. Note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. The output data is fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversions for High-Resolution mode.

100

% Settling

Initial Value

Final Value

Fully Settled Data

at 76 Conversions

(78 Conversions for

High−Resolution mode)

Table 9. Ideal Output Code versus Input Signal

INPUT SIGNAL V

(AINP − AINN)

w +V

223* 1

−V

223* 1

v −V

REF

(1)

Excludes effects of noise, INL, offset and gain errors.

REF

0 000000h

REF

223* 1

IDEAL OUTPUT CODE

7FFFFFh

000001h

FFFFFFh

800000h

(1)

SERIAL INTERFACE

Data is retrieved from the ADS1271 using the serial interface. To provide easy connection to either microcontrollers or DSPs, two formats are available for the interface: SPI and Frame-Sync. The FORMA T pin selects the interface. The same pins are used for both interfaces (SCLK, DRDY

/FSYNC, DOUT and DIN), though their respective functionality depends on the particular interface selected.

SPI SERIAL INTERFACE

The SPI-compatible format is a simple read-only interface. Data ready for retrieval is indicated by the DRDY and is shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple ADS1271s. See the Daisy-Chaining section for more information.

output

02010 4030 6050 8070

Conversions (1/f

DATA

)

Figure 56. Settling Time for All Power Modes

DATA FORMAT

The ADS1271 outputs 24 bits of data in two’s complement format.

A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 9 summarizes the ideal output codes for different input signals.

SCLK (SPI Format)

The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user shifts this data in on the rising edge. Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK should be held low after data retrieval. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. To maximize the converter performance, the ratio of CLK to SCLK should be held to:

CLK

SCLK +

(

N + 0, 1,2AAA

)

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

DRDY/FSYNC

In the SPI format, this pin functions as the DRDY output. It goes low when data is ready for retrieval and then returns high on the rising edge of the first subsequent SCLK. If data is not retrieved (that is, SCLK is held low), DRDY

will pulse high just before the next conversion data is ready , a s shown in Figure 57. The new data is loaded within the ADS1271 one CLK cycle before DRDY

goes low. All data must be shifted out before this time to avoid being overwritten.

1/f

CLK

DRDY

SCLK

1/f

DATA

Figure 57. DRDY Timing with No Readback

DOUT

The conversion data is shifted out on DOUT. The MSB data is valid on DOUT when DRDY

goes low. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out.

DIN

This input is used when multiple ADS1271s are to be daisy-chained together. The DOUT pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low. See the Daisy-Chaining section for more information.

being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. Frame-Sync format requires a specific relationship between SCLK and FSYNC, determined by the mode shown in Table 10.

Table 10. SCLK Period When Using Frame-Sync

Format

MODE REQUIRED SCLK PERIOD

High-Speed τ

High-Resolution τ

Low-Power τ

FRAME

/64

/128

/64

DRDY/FSYNC

In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period. The required FSYNC periods are shown in Table 11. For High-Speed mode, the FSYNC period must be 256 CLK periods. For both High-Resolution and Low-Power modes, the FSYNC period can be either 512 or 256 CLK periods; the ADS1271 will automatically detect which is being used. If the FSYNC period is not the proper value, data readback will be corrupted. It is recommended that FSYNC be aligned with the falling edge of SCLK.

Table 11. FSYNC Period

MODE REQUIRED FSYNC PERIOD

High-Speed 256 CLK Periods

High-Resolution 256 or 512 CLK periods

Low-Power 256 or 512 CLK periods

FRAME-SYNC SERIAL INTERFACE

Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified. When using Frame-Sync format, the CLK, FSYNC and SCLK inputs must be synchronized together, as described in the following sub-sections.

SCLK (Frame-Sync Format)

The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is

DOUT

The conversion data is shifted out on DOUT. The MSB data becomes valid on DOUT on the SCLK rising edge prior to FSYNC going high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out.

DIN

This input is used when multiple ADS1271s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low.See the Daisy-Chaining section for more information.

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DAISY-CHAINING

Multiple ADS1271s can be daisy-chained together to simplify the serial interface connections. The DOUT of one ADS1271 is connected to the DIN of the next ADS1271. The first DOUT provides the output data and the last DIN in the chain is connected to ground. A common SCLK is used for all the devices in the daisy chain. Figure 58 shows an example of a daisy chain with four ADS1271s. Figure 59 shows the timing diagram when reading back in the SPI format. It takes 96 SCLKs to shift out all the data.

In SPI format, it is recommended to tie all the SYNC

/PDWN inputs together, which forces synchronization of all the devices. It is only necessary to monitor the DRDY output of one device when multiple devices are configured this way.

In Frame-Sync format, all of the devices are driven to synchronization by the FSYNC and SCLK inputs. However, to ensure synchronization to the same f recommended to tie all SYNC

The device clocks the SYNC

. To ensure exact synchronization, the SYNC/PDWN

of f

CLK

/PDWN inputs together.

/PDWN pin on the falling edge

pin should transition on the rising edge of f

cycle, it is

CLK

Since DOUT and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT creates the setup time on DIN. Minimize the skew in SCLK to avoid timing violations. See Mode Selection section for MODE pin use when daisy-chaining.

The SPI format offers the most flexibility when daisy-chaining because there is more freedom in setting the SCLK frequency. The maximum number of ADS1271s that can be daisy-chained is determined by dividing the conversion time (1/f all 24 bits (24 × 1/f

) by the time needed to read back

DATA

SCLK

Consider the case where:

= 27MHz

CLK

mode = High-Resolution (52,734SPS) format = SPI f

= 27MHz

SCLK

The maximum length of the daisy-chain is: 27MHz/(24 × 52,734SPS) = 21.3 Rounding down gives 21 as the maximum number of

ADS1271s that can be daisy-chained. Daisy-chaining also works in Frame-Sync format, but the

maximum number of devices that can be daisy-chained is less than when using the SPI format. The ratio between the frame period and SCLK period is fixed, as shown in Table 10. Using these values, the maximum number of devices is two for High-Speed and Low-Power modes, and four for High-Resolution mode.

SYNC

SCLK

ADS1271

SYNC DIN SCLK

DOUT

ADS1271

SYNC DIN SCLK

DOUT

ADS1271

SYNC DIN SCLK

DOUT

ADS1271

SYNC DIN SCLK

DRDY

DOUT

Figure 58. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s

DRDY

SCLK 1

DOUT

ADS1271

Bit 23 (MSB)

24 25 73 96

ADS1271

Bit 0 (LSB)

Bit 23 (MSB)

ADS1271

Bit 2 3 (MSB)

ADS1271 Bit 0(LSB)

Figure 59. Timing Diagram for Example in Figure 58 (SPI Format)

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APPLICATION INFORMATION

To obtain the specified performance from the ADS1271, the following layout and component guidelines should be considered.

1. Power Supplies: The device requires two power supplies for operation: DVDD and A VDD. The allowed range for DVDD is 1.65V to 3.6V, and AVDD is restricted to 4.75V to 5.25V. Best performance is achieved when DVDD = 1.8V. For both supplies, use a 10µF tantalum capacitor, bypassed with a 0.1µF ceramic capacitor, placed close to the device pins. Alternatively, a single 10µF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply source is used, the voltage ripple should be low (< 2mV). The power supplies may be sequenced in any order.

2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter.

3. Digital Inputs: It is recommended to source terminate the digital inputs to the device with 50Ω series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This helps to reduce ringing on the digital lines, which may lead to degraded ADC performance.

4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk.

5. Reference Inputs: It is recommended to use a minimum 10µF tantalum with a 0.1µF ceramic capacitor directly across the reference inputs, REFP and REFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3µV

broadband

RMS

noise. For references with noise higher than this, external reference filtering may be necessary.

6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (AC applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks.

A 1nF to 10nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground should be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the AC common-mode performance.

7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components.

Figure 60 to Figure 62 illustrate basic connections and interfaces that can be used with the ADS1271.

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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Ω

10nF

+5V

Differential

Inputs

+5V

Tie to

Either

DVDD

or GND

100pF

0.1µF

100pF

Ω

1nF

10µF

ADS1271

AINP

AINN

AGND

AVDD

MODE

FORMAT

SYNC/ PDWN

DIN

0.1µF

OPA350

1.8V to 3.3V

Ω

(1)

27MHz

VREFP

VREFN

DGND

DVDD

CLK

10µF0.1µF

10µF

100

0.1µF

Ω

Source

Ω

SCLK

DRDY/

FSYNC

DOUT

Ω

Figure 60. Basic Connection Drawing

100

Clock

+5V

Ω

0.1µF

REF3125

100µF

0.1µF

NOTE: (1) 1.8V recommended.

Ω

1000pF

(1)

+15V

REF

OCM

OPA1632

0.1µF

(1)

−

15V

49.9

Ω

AINP

Ω

AINN

1000pF

Ω

NOTE: (1) Bypass with 10µF and 0.1µF capacitors.

Figure 61. Basic Differential Signal Interface

Ω

10k

Ω

1000pF

(1)

+15V

REF

OCM

OPA1632

0.1µF

(1)

−

15V

1000pF

Ω

10k

Ω

49.9 AINP

Ω

49.9 AINN

=10×V

ODIFF

OCOMM=VREF

Ω

NOTE: (1) Bypass with 10µFand0.1µF capacitors.

Figure 62. Basic Single-Ended Signal Interface

PACKAGE OPTION ADDENDUM

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27-Dec-2004

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

ADS1271IPW ACTIVE TSSOP PW 16 94 None CU Level-2-240C-1 YEAR

ADS1271IPWR ACTIVE TSSOP PW 16 2500 None CU Level-2-240C-1 YEAR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30

0,19

4,50 4,30

PINS **

Seating Plane

0,15 0,05

DIM

6,60 6,20

0,10

0,15 NOM

0°–8°

2016

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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TEXAS INSTRUMENTS ADS1271 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual