TEXAS INSTRUMENTS ADS1271 Technical data

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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FEATURES

D 105kSPS Data Rate D AC Performance:

51kHz Bandwidth 109dB SNR (High-Resolution Mode)

−105dB THD

D DC Accuracy:

1.8µV/°C Offset Drift 2ppm/°C Gain Drift

D Selectable Operating Modes:

High-Speed: 105kSPS Data Rate High-Resolution: 109dB SNR Low-Power: 35mW Dissipation

D Power-Down Control D Digital Filter:

Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB

D Internal Offset Calibration On Command D Selectable SPIt or Frame Sync Serial In terface D Designed for Multichannel Systems:

Daisy-Chainable Serial Interface Easy Synchronization

D Simple Pin-Driven Control D Specified fro m −40°C to +105°C D Analog Supply: 5V D Digital Supply: 1.8V to 3.3V

APPLICATIONS

D Vibration/Modal Analysis D Acoustics D Dynamic Strain Gauges D Pressure Sensors D Test and Measurement

DESCRIPTION

The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. The ADS1271 provides a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple.

Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for DC measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. The ADS1271 combines these converters, allowing high-precision industrial measurement with excellent DC and AC specifications ensured over an extended industrial temperature range.

Three operating modes allow for optimization of speed, resolution, and power. A selectable SPI or a frame-sync serial interface provides for convenient interfacing to microcontrollers or DSPs. All operations, including internal offset calibration, are controlled directly by pins; there are no registers to program.

VREFP VREFN AVDD DVDD

SYNC/PDWN MODE

CLK DRDY/FSYNC

SCLK DOUT DIN FORMAT

AINP

AINN

∆Σ

Modulator

Digital

Filter

Control

Logic

Serial

Interface

DGNDAGND

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Input Current

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

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ABSOLUTE MAXIMUM RATINGS

over opera t i n g f r e e - a i r t e m p e r a t ure range u n l e s s o t h e r w i s e n o t e d

ADS1271 UNIT

AVDD to AGND −0.3 to +6.0 V DVDD to DGND −0.3 to +3.6 V AGND to DGND −0.3 to +0.3 V

100, Momentary mA

10, Continuous mA Analog Input to AGND −0.3 to AVDD + 0 .3 V Digital Input or Output to DGND −0.3 to DVDD + 0.3 V Maximum Junction Tem perature +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C Lead Temperature (soldering, 10s) +300 °C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only , an d functional operation of the device at these or any other conditions beyond those specified is not implied.

(1)

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more susceptible t o damage because very small parametric changes could cause the device not to meet its published specifications.

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Differential input

impedance

DATA

Data rate (f

DATA

)

Offset error

Noise Power-supply

Power-supply f = 60Hz

Signal-to-noise ratio

(SNR)

(2)

Stop band Group delay

Group delay Settling time (latency)

Settling time (latency)

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

PARAMETER TEST CONDITIONS MIN TYP MAX

Analog Inputs

Full-scale input voltage (FSR) Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 V Common-mode input voltage VCM = (AINP + AINN)/2 2.5 V

DC Performance

Resolution No missing codes 24 Bits

Data rate (f

Integral nonlinearity (INL) Differential input, VCM = 2.5V ± 0.0006 ± 0.0015 % of FSR

Offset drift 1.8 µV/_C Gain error 0.1 0.5 % Gain error drift 2 ppm/°C

Noise

Common-mode rejection fCM = 60Hz 90 100 dB

rejection

AC Performance

(2)

(SNR) (unweighted)

Total harmonic distortion (THD) Spurious free dynamic range −108 dB Passband ripple ±0.005 dB Passband 0.453 f

−3dB Bandwidth 0.49 f Stop band attenuation 100 dB

Stop band

(1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signals.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

)

(1)

High-Speed mode 16.4 kΩ High-Resolution mode 16.4 kΩ Low-Power mode 32.8 kΩ

High-Speed mode 105,469 SPS High-Resolution mode 52,734 SPS Low-Power mode 52,734 SPS

High-Speed mode Without calibration 0.150 1 mV

High-Speed mode Shorted input 9.0 20 µV, rms High-Resolution mode 6.5 µV, rms Low-Power mode 9.0 µV, rms

AVDD DVDD

High-Speed mode 99 106 dB High-Resolution mode 109 dB Low-Power mode 106 dB

(3)

High-Speed mode 0.547 f High-Resolution mode 0.547 f Low-Power mode 0.547 f High-Speed and

Low-Power modes High-Resolution mode 39/f High-Speed and

Low-Power modes High-Resolution mode Complete settling 78/f

REF

VIN = (AINP – AINN) ±V

With calibration On the level of the noise

VIN = 1kHz, −0.5dBFS −105 −95 dB

Complete settling 76/f

= 27MHz, and V

CLK

DATA DATA DATA

= +2.5V , unless otherwise noted.

REF

ADS1271

REF

80 dB 80 dB

DATA DATA

63.453 f

127.453 f

63.453 f

38/f

DATA DATA DATA DATA

DATA

UNITS

Hz Hz

Hz Hz Hz

s s s s

(1)

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Reference Input

impedance

Serial clock rate

SCLK

Frame-Sync format

AVDD current Power-Down mode

DVDD current Power-Down mode

Power dissipation

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

PARAMETER

Voltage Reference Inputs

Reference input Voltage (V Negative reference input (VREFN) AGND − 0.1 VREFP − 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V

Digital Input/Output

Input leakage Master clock rate (f

Serial clock rate (f

SCLK

Power Supply

AVDD 4.75 5 5.25 V DVDD 1.65 3.6 V

AVDD current

DVDD current

Power dissipation

Temperature Range

Specified −40 +105 _C Operating −40 +105 _C Storage −60 +150 _C (1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signals.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

(4)

CLK

(5)

)

) V

REF

High-Speed mode 4.2 kΩ High-Resolution mode 4.2 kΩ Low-Power mode 8.4 kΩ

) 1 27 MHz

SPI format 24 f

Frame-Sync format

High-Speed mode 17 25 mA High-Resolution mode 17 25 mA Low-Power mode 6.3 9.5 mA

High-Speed mode 3.5 6 mA High-Resolution mode 2.5 5 mA Low-Power mode 1.8 3.5 mA

High-Speed mode 92 136 mW High-Resolution mode 90 134 mW Low-Power mode 35 54 mW

REF

= VREFP – VREFN 0.5 2.5 2.65 V

REF

IOH = 5mA 0.8 DVDD DVDD V IOL = 5mA DGND 0.2 DVDD V 0 < VIN

DIGITAL

High-Speed mode 64 f High-Resolution mode 128 f Low-Power mode 64 f

T ≤ 105°C 1 70 µA T ≤ 85°C 1 10 µA

T ≤ 105°C, DVDD = 3.3V 1 70 µA T ≤ 85°C, DVDD = 3.3V 1 20 µA

< DVDD ±10 µA

= 27MHz, and V

CLK

= +2.5V , unless otherwise noted.

REF

ADS1271

MAXTYPMINTEST CONDITIONS

0.7 DVDD DVDD V DGND 0.3 DVDD V

64 f

128 f

64 f

CLK DATA DATA DATA

DATA DATA DATA DATA

UNITS

MHz MHz MHz MHz

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MODE5Digital Input

PIN ASSIGNMENTS

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TSSOP (PW) PACKAGE

(TOP VIEW)

AINP

AINN AGND AVDD

MODE

FORMAT

SYNC/PDWN

DIN

1 2 3 4

ADS1271

5 6 7 8

VREFP

VREFN

DGND

DVDD

CLK

SCLK

DRDY/FSYNC

DOUT

Terminal Functions

NAME NO. FUNCTION DESCRIPTION

AINP 1 Analog Input Positive analog input AINN 2 Analog Input Negative analog input AGND 3 Analog Input Analog ground AVDD 4 Analog Input Analog supply MODE 5 Digital Input MODE = 0: High-Speed mode

MODE = float: High-Resolution mode MODE = 1: Low-Power mode

FORMAT 6 Digital Input FORMAT = 0: SPI

FORMAT = 1: Frame-Sync SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low DIN 8 Digital Input Data input for daisy-chain operation DOUT 9 Digital Output Data output DRDY/FSYNC 10 Digital

Input/Output SCLK 11 Digital Input Serial clock for data retrieval CLK 12 Digital Input Master clock DVDD 13 Digital Input Digital supply DGND 14 Digital Input Digital ground VREFN 15 Analog Input Negative reference input VREFP 16 Analog Input Positive reference input

If FORMAT = 0 (SPI), then pin 10 = DRDY output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input

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CONV

DATA

CONV

Conversion period (1/f

DATA

)

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TIMING CHARACTERISTICS: SPI FORMAT

CLK

DRDY

SCLK

DDO

DOUT

DIN

Bit 23 (MSB) Bit 22 Bit 21

TIMING REQUIREMENTS: SPI FORMAT

For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

(1)

DDO

(1)

SPW

DOHD

DOPD

DIST

DIHD

(1)

Load on DRDY and DOUT = 20pF.

CLK period (1/f

) 37 1000 ns

CLK

CLK positive or negative pulse width 15 ns

High-Speed mode 256 CLK periods

Conversion period (1/f

High-Resolution mode 512 CLK periods

)

Low-Power mode 512 CLK periods Falling edge of CLK to falling edge of DRDY 8 ns Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 ns Valid DOUT to falling edge of DRDY 0 ns Falling edge of SCLK to rising edge of DRDY 8 ns SCLK period t SCLK positive or negative pulse width 12 ns

(1)

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(1)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

SPW

CPW

•••

CPW

DIST

CONV

DOHD

DIHD

SPW

DOPD

CLK

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FRAME

DATA

FRAME

Frame period (1/f

DATA

)

be continuously running)

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

CPW

•••

CPW

SPW

DIST

FRAME

FPW

DOHD

DIHD

SPW

DOPD

CLK

FSYNC

SCLK

DOUT

DIN

FPW

SPW

DDO

Bit 23(MSB) Bit 22 Bit 21

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

FPW

SPW

DOHD

DOPD

DDO

DIST

DIHD

(1)

The ADS1271 automatically detects either frame period.

(2)

Load on DOUT = 20pF.

CLK period (1/f

) 37 1000 ns

CLK

CLK positive or negative pulse width 15 ns Rising edge of CLK to falling edge of SCLK −2 8 ns

High-Speed mode 256 CLK periods

Frame period (1/f

High-Resolution mode 256 or 512

)

Low-Power mode 256 or 512

(1) (1)

FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns Rising edge of SCLK to rising edge of FSYNC 5 ns

SCLK period (SCLK must

High-Resolution mode τ

FRAME

Low-Power mode τ

High-Speed mode τ

SCLK positive or negative pulse width 0.4τ

(2)

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(2)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns

(2)

Valid DOUT to falling edge of FSYNC 0 ns

SCLK

/64 τ

FRAME

/128 τ

/64 τ

FRAME

0.6τ

SCLK

New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

CLK periods CLK periods

FRAME FRAME FRAME

periods periods periods

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OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

= 2.5V , unless otherwise noted.

REF

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High−Speed Mode

= 1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 1

High−Speed Mode

−

Shorted Input

2,097,152 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

10k 100k

High−Speed Mode

=1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

420k

High−Speed Mode Shorted Input

360k

2,097,152 Points

300k

240k

180k

120k

Number of Occurrences

60k

−50−45−40−35−30−25−20−15−

Frequency (Hz)

Figure 2

−

Output (µV)

10k 100k

101520253035404550

Figure 3

High−Resolution Mode

=1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 5

10k 100k

High−Resolution Mode

= 1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Figure 4

10k 100k

Frequency (Hz)

Figure 6

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OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISEH ISTOGRAM

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, and V

CLK

REF



SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

= 2.5V , unless otherwise noted.

High−Resolution Mode

−

Shorted Input 1,048,576 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 7

Low−Power Mode

=1kHz,−0.5dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

10k 100k

210k

High−ResolutionMode Shorted Input

180k

1,048,576 Points

150k

120k

90k

60k

Number ofOccurrences

30k

−30−28−26−24−22−20−18−16−14−12−

Low−Power Mode

=1kHz,−20dBFS

−

32,768 Points

−

100

−

120

−

140

−

160

10 100 1k

−8−6−4−

Output (µV)

02468

Figure 8

Frequency (Hz)

1012141618202224262830

10k 100k

Figure 9

Low−Power Mode

−

Shorted Input

1,048,576 Points

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 11

10k 100k

200k

Low−Power Mode

180k

Shorted Input 1,048,576 Points

160k 140k 120k 100k

80k 60k

Number of Occurrences

40k 20k

−50−45−40−35−30−25−20−15−

Figure 10

−

Output (µV)

Figure 12

101520253035404550

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