Texas Instruments ADS1258IRTCTG4, ADS1258 Datasheet

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ADS1258

FEATURES DESCRIPTION

APPLICATIONS

24−Bit

ADC

Digital

Filter

Internal

Monitoring

16:1

Analog

Input
MUX

1

16

AINCOM

…

ADC

IN

Extclk
In/Out

AVSS DGND

32.768kHz

AVDD DVDD

MUX
OUT

SPI

Interface

CS
DRDY
SCLK
DIN
DOUT

ControlOscillator

GPIO

START
RESET
PWDN

GPIO[7:0]V

REF

ADS1258

Analog Inputs

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

16-Channel, 24-Bit Analog-to-Digital Converter

• 24 Bits, No Missing Codes

The ADS1258 is a 16-channel (multiplexed),
low-noise, 24-bit, delta-sigma ( ∆ Σ ) analog-to-digital

• Fixed-Channel or Automatic Channel Scan

converter (ADC) that provides single-cycle settled

• Fixed-Channel Data Rate: 125kSPS

data at channel scan rates from 1.8k to 23.7k

• Auto-Scan Data Rate: 23.7kSPS/Channel

samples per second (SPS) per channel. A flexible

• Single-Conversion Settled Data input multiplexer accepts combinations of eight
differential or 16 single-ended inputs with a full-scale

• 16 Single-Ended or 8 Differential Inputs
differential range of 5V or true bipolar range of ± 2.5V

• Unipolar (+5V) or Bipolar ( ± 2.5V) Operation

when operating with a 5V reference. The fourth-order

• Low Noise: 2.8 µ V

RMS

at 1.8kSPS

delta-sigma modulator is followed by a fifth-order
sinc digital filter optimized for low-noise performance.

• 0.0003% Integral Nonlinearity

• DC Stability (typical): The differential output of the multiplexer is accessible

to allow signal conditioning prior to the input of the

0.02 µ V/ ° C Offset Drift, 0.4ppm/ ° C Gain Drift

ADC. Internal system monitor registers provide

• Open-Sensor Detection

supply voltage, temperature, reference voltage, gain,

• Conversion Control Pin

and offset data.

• Multiplexer Output for External Signal

An onboard PLL generates the system clock from a

Conditioning

32.768kHz crystal, or can be overridden by an

• On-Chip Temperature, Reference, Offset,

external clock source. A buffered system clock

Gain, and Supply Voltage Readback

output (15.7MHz) is provided to drive a
microcontroller or additional converters.

• 42mW Power Dissipation

Serial digital communication is handled via an

• Standby, Sleep, and Power-Down Modes

SPI™-compatible interface. A simple command word

• 8 General-Purpose Inputs/Outputs (GPIO)

structure controls channel configuration, data rates,

• 32.768kHz Crystal Oscillator or External Clock

digital I/O, monitor functions, etc.
Programmable sensor bias current sources can be

used to bias sensors or verify sensor integrity.

• Medical, Avionics, and Process Control

The ADS1258 operates from a unipolar +5V or

• Machine and System Monitoring
bipolar ± 2.5V analog supply and a digital supply

• Fast Scan Multi-Channel Instrumentation

compatible with interfaces ranging from 2.7V to

• Industrial Systems

5.25V. The ADS1258 is available in a QFN-48

• Test and Measurement Systems

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com .

Over operating free-air temperature range (unless otherwise noted).

(1)

ADS1258 UNIT

AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +5.5 V
Input Current 100, Momentary mA
Input Current 10, Continuous mA
Analog Input Voltage AVSS – 0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 ° C
Operating Temperature Range –40 to +105 ° C
Storage Temperature Range –60 to +150 ° C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.

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ELECTRICAL CHARACTERISTICS

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

=

15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, V

REF

= +4.096V, and VREFN = –2.5V, unless otherwise

noted.

ADS1258
PARAMETER CONDITIONS MIN TYP MAX UNIT
Analog Multiplexer Inputs

AIN0–AIN15,

Absolute Input Voltage AVSS – 100mV AVDD + 100mV V

AINCOM with respect to DGND
On-Channel Resistance 80 Ω
Crosstalk fIN= 1kHz –110 dB

SBCS[1:0] = 01 1.5

Sensor Bias (Current Source) µ A

SBCS[1:0] = 11 24

1.5 µ A:24 µ A Ratio Error 1 %

ADC Input

Full-Scale Input Voltage (V

IN

= ADCINP – ADCINN) ± 1.0 6V

REF

V
Absolute Input Voltage (ADCINP, ADCINN) AVSS – 100mV AVDD + 100mV V
Differential Input Impedance 65 k Ω

System Performance

Resolution No Missing Codes 24 Bits
Data Rate, Fixed-Channel Mode 1.953 125 kSPS
Data Rate, Auto-Scan Mode 1.805 23.739 kSPS
Integral Nonlinearity (INL)

(1)

Differential Input 0.0003 0.0010 % of FSR

(2)

Chopping Off 20

Offset Error Shorted Inputs µ V

Chopping On 1 10
Chopping Off 0.5

Offset Drift

(3)

Shorted Inputs µ V/ ° C

Chopping On 0.02 0.1
Gain Error 0.1 0.5 %
Gain Drift

(3)

0.4 2 ppm/ ° C
Noise (see Table 4 )
Common-Mode Rejection fCM= 60Hz 90 100 dB

AVDD, AVSS 70 85

Power-Supply Rejection fPS= 60Hz dB

DVDD 80 95

Voltage Reference Input

Reference Input Voltage (V

REF

= VREFP – VREFN) 0.5 4.096 AVDD – AVSS V
Negative Reference Input (VREFN) AVSS – 0.1V VREFP – 0.5 V
Positive Reference Input (VREFP) VREFN + 0.5 AVDD + 0.1V V
Reference Input Impedance 40 k Ω

System Parameters

External Reference Reading Error 1 3 %
Analog Supply Reading Error 1 3 %

Voltage TA= +25 ° C 168 mV

Temperature Sensor Reading

Coefficient 394 µ V/ ° C

Digital Input/Output

V

IH

0.7DVDD DVDD V

V

IL

DGND 0.3DVDD V

Logic Levels

V

OH

IOH= 2mA 0.8DVDD DVDD V

V

OL

IOL= 2mA DGND 0.2DVDD V

Input Leakage VIN= DVDD, GND 10 µ A

Frequency 0.1 16 MHz

Master Clock Input (CLKIO)

Duty Cycle 40 60 %

(1) Best straight line fit method.
(2) FSR = Full-scale range = 2.1 3V

REF

.

(3) Ensured by characterization.

3

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PIN CONFIGURATION

Top V iew QFN

36
35
34
33
32
31
30
29
28
27
26
25

AIN12
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
START
DRDY

AIN4

AIN5

AIN6

AIN7

MUXOUTP

MUXOUTN

ADCINP

ADCINN

AIN8

AIN9

AIN10

AIN11

CLKIO

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

SCLK

DIN

DOUT

1
2
3
4
5
6
7
8

9
10
11
12

AIN3
AIN2
AIN1

AIN0
AVSS
AVDD

PLLCAP

XTAL1
XTAL2
PWDN

RESET

CLKSEL

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 233724

ADS1258

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

=

15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, V

REF

= +4.096V, and VREFN = –2.5V, unless otherwise

noted.

ADS1258

PARAMETER CONDITIONS MIN TYP MAX UNIT

Crystal Frequency 32.768 kHz
Clock Output Frequency 15.729 MHz

Crystal Oscillator
(see Crystal Oscillator section)

Start-Up Time (Clock Output Valid) 150 mS
Clock Output Duty Cycle 40 60 %

Power Supply

DVDD 2.7 5.25 V
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V

External Clock

0.25 0.6 mA

Operation

Internal Oscillator

Operation, Clock 0.04 mA

Output Disabled

DVDD Supply Current

Internal Oscillator

Operation, Clock 1.4 mA

Output Enabled

(4)

Power-Down

(5)

1 25 µA

Converting 8.2 12 mA

Standby 5.6 mA

AVDD, AVSS Supply Current

Sleep 2.1 mA

Power-Down 2 85 µA

Converting 42 62 mW

Standby 29 mW

Power Dissipation

Sleep 11 mW

Power-Down 14 µ W

(4) CLKIO load = 20pF.
(5) No clock applied to CLKIO.

4

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ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

PIN ASSIGNMENTS

ANALOG/DIGITAL

PIN # NAME INPUT/OUTPUT DESCRIPTION

1 AIN3 Analog Input Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–)
2 AIN2 Analog Input Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+)
3 AIN1 Analog Input Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–)
4 AIN0 Analog Input Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+)

Negative Analog Power Supply: 0V for unipolar operation, –2.5V for bipolar operation.

5 AVSS Analog

(Internally connected to exposed thermal pad of QFN package.)
6 AVDD Analog Positive Analog Power Supply: +5V for unipolar operation, +2.5V for bipolar operation.
7 PLLCAP Analog PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator.
8 XTAL1 Analog 32.768kHz Crystal Oscillator Input 1; see Crystal Oscillator section.
9 XTAL2 Analog 32.768kHz Crystal Oscillator Input 2; see Crystal Oscillator section.

10 PWDN Digital Input Power-Down Input: Hold low for minimum of two f

CLK

cycles to engage low-power mode.

11 RESET Digital Input Reset Input: Hold low for minimum of two f

CLK

cycles to reset the device.

Clock Select Input: Low = Activates Crystal Oscillator, f

CLK

output on CLKIO.

12 CLKSEL Digital Input

High = Disables Crystal Oscillator, apply f

CLK

to CLKIO.
13 CLKIO Digital I/O System Clock Input/Output (See CLKSEL pin.)
14 GPIO0 Digital I/O General-Purpose Digital Input/Output 0
15 GPIO1 Digital I/O General-Purpose Digital Input/Output 1
16 GPIO2 Digital I/O General-Purpose Digital Input/Output 2
17 GPIO3 Digital I/O General-Purpose Digital Input/Output 3
18 GPIO4 Digital I/O General-Purpose Digital Input/Output 4
19 GPIO5 Digital I/O General-Purpose Digital Input/Output 5
20 GPIO6 Digital I/O General-Purpose Digital Input/Output 6
21 GPIO7 Digital I/O General-Purpose Digital Input/Output 7
22 SCLK Digital Input SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge.
23 DIN Digital Input SPI Interface Data Input: Data is input to the device.
24 DOUT Digital Output SPI Interface Data Output: Data is output from the device.
25 DRDY Digital Output Data Ready Output: Active low.
26 START Digital Input Start Conversion Input: Active high.
27 CS Digital Input SPI Interface Chip Select Input: Active low.
28 DVDD Digital Digital Power Supply: 2.7V to 5.25V
29 DGND Digital Digital Ground
30 VREFN Analog Input Reference Input Negative
31 VREFP Analog Input Reference Input Positive
32 AINCOM Analog Input Analog Input Common: Common input pin to all single-ended inputs.
33 AIN15 Analog Input Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–)
34 AIN14 Analog Input Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+)
35 AIN13 Analog Input Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–)
36 AIN12 Analog Input Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+)
37 AIN11 Analog Input Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–)
38 AIN10 Analog Input Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+)
39 AIN9 Analog Input Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–)
40 AIN8 Analog Input Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+)
41 ADCINN Analog Input ADC Differential Input (–)
42 ADCINP Analog Input ADC Differential Input (+)
43 MUXOUTN Analog Output Multiplexer Differential Output (–)
44 MUXOUTP Analog Output Multiplexer Differential Output (+)
45 AIN7 Analog Input Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–)
46 AIN6 Analog Input Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+)
47 AIN5 Analog Input Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–)
48 AIN4 Analog Input Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+)

5

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PARAMETER MEASUREMENT INFORMATION

SCLK

CS

(1)

DIN

DOUT

t

SCLK

t

CSSC

t

SPW

t

DIST

t

DIHD

t

SPW

t

CSDO

Hi-ZHi-Z

t

DOPD

t

DOHD

NOTE: (1) CS can be tiedlow.

DRDY

DOUT

t

DRDY

t

DDO

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

Figure 1. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

At TA= –40 ° C to +105 ° C and DVDD = 2.7V to 5.25V, unless otherwise noted.

SYMBOL DESCRIPTION MIN MAX UNITS

t

SCLK

SCLK Period 2 τ

CLK

(1)

t

SPW

SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 4096

(2)

τ

CLK

t

CSSC

CS Low to First SCLK: Setup Time

(3)

0.5 τ

CLK

t

DIST

Valid DIN to SCLK Rising Edge: Setup Time 10 ns

t

DIHD

Valid DIN to SCLK Rising Edge: Hold Time 5 ns

t

DOPD

SCLK Falling Edge to Valid New DOUT: Propagation Delay

(4)

20 ns

t

DOHD

SCLK Falling Edge to Old DOUT Invalid: Hold Time 0 ns

t

CSDO

CS High to DOUT Invalid (tri-state) 5 τ

CLK

(1) τ

CLK

= master clock period = 1/f

CLK

.

(2) Programmable to 256 τ

CLK

.
(3) CS can be tied low.
(4) DOUT load = 20 pF || 100k Ω to DGND.

Figure 2. DRDY Update Timing

DRDY UPDATE TIMING CHARACTERISTICS

SYMBOL DESCRIPTION TYP UNITS

t

DRDY

DRDY High Pulse Width Without Data Read 1 τ

CLK

t

DDO

Valid DOUT to DRDY Falling Edge ( CS = 0) 0.5 τ

CLK

6

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TYPICAL CHARACTERISTICS

Number of Occurrences

Offset (µV)

3000

2500

2000

1500

1000

500

0

−

50

−

45

−

40

−

35

−

30

−

25

−

20

−

15

−

10

5

0

5

10

15

20

25

30

35

40

45

50

DRATE[1:0] = 11
16384 Points

Number of Occurrences

Offset (µV)

4500
4000
3500
3000
2500
2000
1500
1000

500

0

−

35

−

30

−

25

−

20

−

15

−

10

−

5

0

5

10

15

20

25

30

35

DRATE[1:0] = 10
16384 Points

Number of Occurrences

Offset (µV)

3500

3000

2500

2000

1500

1000

500

0

−

20

−

16

−

12

−

8

−

4

0

4

8

12

16

20

DRATE[1:0] = 01
16384 Points

Number of Occurrences

Offset (µV)

2500

2000

1500

1000

500

0

−

12

−

10

−

8

−

6

−

4

−

2

0

2

4

6

8

10

12

DRATE[1:0] = 00
16384 Points

RMS Noise (

µ

V)

Input Voltage (%FS)

20

15

10

5

0

−

100−75 10075

−50−

25 50250

DRATE[1:0] = 11

DRATE[1:0] = 10

DRATE[1:0] = 01

DRATE[1:0] = 00

Number of Occurrences

RMS Noise (µV)

20

15

10

5

0

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

15.0

50 units from two production lots.
DRATE[1:0] = 11

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

= 15.729MHz (internal clock), OPA227

buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

READING HISTOGRAM READING HISTOGRAM

Figure 3. Figure 4.

READING HISTOGRAM READING HISTOGRAM

Figure 5. Figure 6.

NOISE HISTOGRAM NOISE vs INPUT VOLTAGE

Figure 7. Figure 8.

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RMS Noise (

µ

V)

V

REF

(V)

16
14
12
10

8
6
4
2
0

0.5 1.5 5.52.5 3.5 4.5

DRATE[1:0] = 11

DRATE[1:0] = 10

DRATE[1:0] = 01

DRATE[1:0] = 00

RMS Noise (

µ

V)

DVDD, AVDD−AVSS (V)

20
18
16
14
12
10

8
6
4

2.5 3.0 5.53.5 4.0 4.5 5.0

DRATE[1:0] = 11

from DVDD

from AVDD−AVSS

RMS Noise (

µ

V)

Temperature (_C)

20
18
16
14
12
10

8
6
4

−40−

20 0

20 40 60 80 100

DRATE[1:0] = 11

RMS Noise (

µ

V)

Common−Mode Input Voltage (V)

20

15

10

5

0

Offset (

µ

V)

5

0

−

5

−

10

−

15

−

3

−

2 3

−

1 0 1 2

OFFSET

CHOP = 1

OFFSET

CHOP = 0

NOISE

Number of Occurrences

Offset (µV)

200
180
160
140
120
100

80
60
40
20

0

−

10

−

8

−

6

−

4

−

2

0

2

4

6

8

10

311 units from one production lot.
CHOP = 1

Number of Occurrences

Offset Drift (µV/_C)

80

60

40

20

0

−

0.10

−

0.09

−

0.08

−

0.07

−

0.06

−

0.05

−

0.04

−

0.03

−

0.02

−

0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

50 units from two
production lots.
Based on 20_C intervals
over the range of

−

40_C to +105_C.

CHOP = 1

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

= 15.729MHz (internal clock), OPA227

buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

NOISE vs V

REF

NOISE vs SUPPLY VOLTAGE

Figure 9. Figure 10.

NOISE AND OFFSET vs

NOISE vs TEMPERATURE COMMON-MODE INPUT VOLTAGE

Figure 11. Figure 12.

OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM

Figure 13. Figure 14.

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Normalized Offset (

µ

V)

Temperature (_C)

20

0

−

20

−

40

−

60

−40−

20 1000 20 806040

CHOP = 1

CHOP = 1, No Buffer

CHOP = 0, No Buffer

50 units from two production lots.

Normalized Offset (

µ

V)

V

REF

(V)

0.5 1.0

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

5.51.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Normalized Offset (

µ

V)

Time After Power−On (s)

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

0 10 6020 30 40 50

Free−Air

Number of Occurrences

Absolute Gain Error (ppm)

80

60

40

20

0

100

300

500

700

900

1100

1300

1500

1700

1900

320 units from one production lot.

Normalized Gain Error (ppm)

Temperature (_C)

30

20

10

0

−

10

−40−

20 1000 20 806040

Number of Occurrences

Gain Drift (ppm/_C)

80

60

40

20

0

−

1.8

−

1.6

−

1.4

−

1.2

−

1.0

−

0.8

−

0.6

−

0.4

−

0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

50 units from two productionlots.
Based on 20_C intervals over the
range of−40_C to +105_C.

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

= 15.729MHz (internal clock), OPA227

buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

OFFSET vs TEMPERATURE OFFSET vs V

REF

Figure 15. Figure 16.

OFFSET POWER-ON WARMUP GAIN ERROR HISTOGRAM

Figure 17. Figure 18.

GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE

Figure 19. Figure 20.

9

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Normalized Gain Error (ppm)

V

REF

(V)

20
15
10

5
0

−

5

−

10

−

15

−

20

0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5

Normalized Gain Error (ppm)

Time After Power−On (s)

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

0 10 6020 30 40 50

Free−Air

Linearity Error (ppm)

V

REF

(V)

10

8

6

4

2

0

0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5

Linearity Error (ppm)

VIN(V)

−5−

4

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

5

−3−2−

1 0 1 2 3 4

V

REF

= 5V

TA=−40_C,−10_C, +25_C, +55_C, +85_C, +105_C

INL (ppm)

Temperature (_C)

8

6

4

2

0

−40−

20 1201000 20 806040

Level (dBFS)

Frequency (Hz)

0

−

20

−

40

−

60

−

80

−

100

−

120

−

140

−

160

−

180

1 10 100k100 1k 10k

f = 1kHz,−0.5dBFs
DRATE[1:0] = 11
65536 Points

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

= 15.729MHz (internal clock), OPA227

buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

GAIN ERROR vs V

REF

GAIN ERROR POWER-ON WARMUP

Figure 21. Figure 22.

INTEGRAL NONLINEARITY vs V

REF

INTEGRAL NONLINEARITY vs INPUT LEVEL

Figure 23. Figure 24.

INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM

Figure 25. Figure 26.

10

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Temperature Sensor Voltage (mV)

Temperature (_C)

210

200

190

180

170

160

150

140

−40−

20 12040

0 20 60 80 100

Number of Occurrences

Temperature Reading (_C)

8
7
6
5
4
3
2
1
0

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

50 units from two production lots.
TA= +25_C

Ratio (

µ

A/

µ

A)

Temperature (_C)

18

17

16

15

14

−40−

20 120100

0 20 806040

Number of Occurrences

Ratio (µA/µA)

25

20

15

10

5

0

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

50 units from two production lots.

AVDD, AVSS Current (mA)

Temperature (_C)

10

8

6

4

2

0

DVDD Current (mA)

1.0

0.8

0.6

0.4

0.2

0

−40−

20 120

0 20 40 60 80 100

AVDD, AVSS

DVDD

RMS Noise (

µ

V)

Master Clock (MHz)

20

16

12

8

4

0

Linearity Error (ppm)

20

16

12

8

4

0

0.1 1 10010

DRATE[1:0] = 11

Noise

Linearity

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

CLK

= 16MHz (external clock) or f

CLK

= 15.729MHz (internal clock), OPA227

buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM

Figure 27. Figure 28.

SENSOR BIAS CURRENT SOURCE RATIO SENSOR BIAS CURRENT SOURCE RATIO

HISTOGRAM vs TEMPERATURE

Figure 29. Figure 30.

SUPPLY CURRENT vs TEMPERATURE NOISE AND INL vs MASTER CLOCK

Figure 31. Figure 32.

11

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OVERVIEW

AIN0

AIN1
AIN2
AIN3
AIN4
AIN5

AIN6
AIN7
AIN8
AIN9

AIN10
AIN11
AIN12
AIN13
AIN14
AIN15

AINCOM

Control

Logic

VREFPVREFN

AVSS

PLLCAP XTAL1XTAL2

DRDY
PWDN
RESET
START

SPI

Interface

CS
SCLK
DIN
DOUT

Digital Filter

Clock Control

16−Channel

MUX

AVDD

Sensor

Bias

M

UXOUTP

MUX

OUTN

ADCINP GND

AD

CINN

ADC Channel Control

Supply Monitor

GPIO

G

PIO[7:0]

DVDD

Temperature

Ext Ref Monitor

Internal Ref

ADC

CLKSELCLKIO

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

provides a low-noise digital output. The ADC channel

The ADS1258 is a flexible, 24-bit, low-noise ADC

block controls the multiplexer Auto-Scan feature.

optimized for fast multi-channel, high-resolution

Channel Auto-Scan occurs at a maximum rate of

measurement systems. The converter provides a

23.7kSPS. Slower scan rates can be used with

maximum channel scan rate of 23.7kSPS, providing

corresponding increases in resolution.

a complete 16-channel scan in less than 700 µ s.

Communication is handled over an SPI-compatible

Figure 33 shows the block diagram of the ADS1258.

serial interface with a set of simple commands

The input multiplexer selects the analog input pins

providing control of the ADS1258. Onboard registers

connected to the multiplexer output pins

store the various settings for the input multiplexer,

(MUXOUTP/MUXOUTN). External signal

sensor detect bias, data rate selection, etc. Either an

conditioning can be used between the multiplexer

external 32.768kHz crystal, connected to pins XTAL1

output pins and the ADC input pins

and XTAL2, or an external clock applied to pin

(ADCINP/ADCINN) or the multiplexer output can be

CLKIO can be used as the clock source. When using

routed internally to the ADC inputs without external

the external crystal oscillator, the system clock is

circuitry. Selectable current sources within the input

available as an output for driving other devices or

multiplexer can be used to bias sensors or detect for

controllers. General-purpose digital I/Os (GPIO)

a failed sensor. On-chip system function readings

provide input and output control of eight pins.

provide readback of temperature, supply voltage,
gain, offset, and external reference.

The ADS1258 converter is comprised of a
fourth-order, delta-sigma modulator followed by a
programmable digital filter. The modulator
measures the differential input signal,
V

IN

= (ADCINP – ADCINN), against the differential

reference input, V

REF

= (VREFP – VREFN). The

digital filter receives the modulator signal and

Figure 33. ADS1258 Block Diagram

12

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MULTIPLEXER INPUTS

AVSS* 100mV tǒVREFP or VREFNǓt AVDD) 100mV

(1)

VOLTAGE REFERENCE INPUTS

ESD
Diodes

ESD
Diodes

3pF

R

eff

= 40k

Ω

(f

CLK

= 16MHz)

AVDD

AVSS

VREFP

VREFN

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

ESD diodes protect the reference inputs. To keep
A simplified diagram of the input multiplexer is these diodes from turning on, make sure the
illustrated in Figure 35 . The multiplexer connects one voltages on the reference pins do not go below
of 16 single-ended external inputs, one of eight AVSS by more than 100mV, and likewise do not
differential external inputs, or one of the on-chip exceed AVDD by 100mV, as described in
internal variables to the ADC inputs. The output of Equation 1 :
the channel multiplexer can be routed to external
pins and then to the input of the ADC. This flexibility

A high-quality reference voltage is essential for

allows for use of external signal conditioning. See

achieving the best performance from the ADS1258.

the External Multiplexer Loop section.

Noise and drift on the reference degrade overall
ESD diodes protect the analog inputs. To keep these

system performance. It is especially critical that
diodes from turning on, make sure the voltages on

special care be given to the circuitry that generates
the input pins do not go below AVSS by more than

the reference voltages and the layout when operating
100mV, and likewise do not exceed AVDD by more

in the low-noise settings (that is, with low data rates)
than 100mV:

to prevent the voltage reference from limiting

performance. See the Reference Inputs description

AVSS – 100mV < (Analog Inputs) < AVDD + 100mV.

in the Hardware Considerations segment of the
Overdriving the multiplexer inputs may affect the

Applications section.

conversions of other channels. See the Input
Overload Protection description in the Hardware

Considerations segment of the Applications section.

The converter supports two modes of channel
access through the multiplexer: the Auto-Scan mode
and the Fixed-Channel mode. These modes are
selected by the MUXMOD bit of register CONFIG0.
The Auto-Scan mode scans through the selected
channels automatically, with break-before-make
switching. The Fixed-Channel mode requires the
user to set the channel address for each channel
measured.

(VREFP, VREFN)

The voltage reference for the ADS1258 ADC is the
differential voltage between VREFP and VREFN:
V

REF

= VREFP – VREFN. The reference inputs use a
structure similar to that of the analog inputs with the
circuitry on the reference inputs shown in Figure 34 .

Figure 34. Simplified Reference Input Circuit

The load presented by the switched capacitor can be
modeled with an effective resistance (R

eff

) of 40k Ω

for f

CLK

= 16MHz. Note that the effective impedance
of the reference inputs will load an external reference
with a non-zero source impedance.

13

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ADC

AIN0

VREFN

VREFP

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AINCOM

Multiplexer

Reference/Gain Monitor

NOTE: ESD diodes not shown.

Supply Monitor

AVDD

AVSS

AVDD
AVSS

Temperature Sensor Monitor

1x 2x

8x 1x

AVDD

(AVDD−AVSS)/2

AVSS

Sensor Bias Offset Monitor

MUXOUTP

MUXOUTN

ADCINP

ADCINN

Internal
Reference

AVSS

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

Figure 35. Input Multiplexer

14

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ADC INPUTS

t

SAMPLE

ON

OFF

S

1

S

2

OFF

ON

S

1

S

1

AVSS + 1.3V

R

AIN

= R

effB

|| 2R

effA

AVSS + 1.3V

R

effA

= 190k

Ω

R

effB

= 78kΩ(f

CLK

= 16MHz)

R

effA

= 190k

Ω

ADCINN

ADCINP

CA1= 0.65pF

CB= 1.6pF

CA2= 0.65pF

ADCINN

S

2

AVSS + 1.3V

S

2

AVSS + 1.3V

ADCINP

Equivalent

Circuit

R

eff

= t

SAMPLE/CX

NOTE: ESD input diodes not shown.

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

As with the multiplexer and reference inputs, ESD
diodes protect the ADC inputs. To keep these diodes

The ADS1258 ADC inputs (ADCINP, ADCINN)

from turning on, make sure the voltages on the input

measure the input signal using internal capacitors

pins do not go below AVSS by more than 100mV,

that are continuously charged and discharged. The

and likewise do not exceed AVDD by more than

left side of Figure 37 shows a simplified schematic of

100mV.

the ADC input circuitry; the right side of Figure 37
shows the input circuitry with the capacitors and
switches replaced by an equivalent circuit. Figure 36
shows the ON/OFF timings of the switches shown in

Figure 37 . S

1

switches close during the input

sampling phase. With S

1

closed, C

A1

charges to

ADCINP, C

A2

charges to ADCINN, and C

B

charges

to (ADCINP – ADCINN). For the discharge phase, S

1

opens first and then S

2

closes. C

A1

and C

A2

discharge to approximately AVSS + 1.3V and C

B

discharges to 0V. This two-phase sample/discharge
cycle repeats with a period of t

SAMPLE

= 2/f

CLK

.

Figure 36. S1and S2Switch Timing for Figure 37

The charging of the input capacitors draws a
transient current from the source driving the
ADS1258 ADC inputs. The average value of this
current can be used to calculate an effective
impedance (R

eff

) where R

eff

= VIN/I

AVERAGE

. These

impedances scale inversely with f

CLK

. For example, if

f

CLK

is reduced by a factor of two, the impedances

will double.

Figure 37. Simplified ADC Input Structure

15

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MASTER CLOCK (f

CLK

)

50

Ω

32.768kHz

(1)

4.7pF 4.7pF

22nF

CLKSEL XTAL1 XTAL2 PLLCAP

AVSS

CLKIO

ClockOutput
(15.729MHz)

0Vto−2.5V

NOTE:(1)Parallelresonanttype,CL=12.5pF,ESR= 35kΩ(max).
Placethe crystalandloadcapacitorsas closeaspossibleto thedevicepins.

32.768kHz

Crystal Oscillator

and PLL

MUX

CLKENB

Bit

Internal Master Clock(f

CLK

)

CLKSEL

CLKIO

XTAL1 XTAL2 PLL

External Clock Input

Crystal Oscillator

50

Ω

CLKSEL XTAL1 XTAL2 PLLCAP

DVDD

CLKIO

Clock Input
(16MHz)

2.7V

to 5V

No Connection

ADS1258

SBAS297D – JUNE 2005 – REVISED NOVEMBER 2006

The ADS1258 oversamples the analog input at a
high rate. This requires a high-frequency master
clock to be supplied to the converter. As shown in

Figure 38 , the clock comes from either a crystal

oscillator or an external clock source.

Figure 39. Crystal Oscillator Connection

Table 1. System Clock Source

CLKSEL CLKENB

PIN CLOCK SOURCE BIT CLKIO FUNCTION

32.768kHz Disabled

0 0

Crystal Oscillator (internally grounded)

32.768kHz

0 1 Output (15.729MHz)

Crystal Oscillator

Figure 38. Clock Generation Block Diagram

1 External Clock Input X Input (16MHz)

The CLKSEL pin determines the source of the

Table 2. Approved Crystal Vendors

system clock, as shown in Table 1 . The CLKIO pin

VENDOR CRYSTAL PRODUCT

functions as an input or as an output. When the
CLKSEL pin is set to '1', CLKIO is configured as an

Epson C-001R

input to receive the master clock. When the CLKSEL
pin is set to '0', the crystal oscillator generates the
clock. The CLKIO pin can then be configured to
output the master clock. When the clock output is not

When using an external clock to operate the device,

needed, it can be disabled to reduce device power

apply the master clock to the CLKIO pin. For this

consumption.

mode, the CLKSEL pin is tied high. CLKIO then
becomes an input, as shown in Figure 40 .

Make sure to use a clock source clean from jitter or

An on-chip oscillator and Phase-Locked Loop (PLL)

interference. Ringing or under/overshoot should be

can be used to generate the system clock. For this

avoided. A 50 Ω resistor in series with the CLKIO pin

mode, tie the CLKSEL pin low. A 22nF PLL filter

(placed close to the source) can often help.
capacitor, connected from the PLLCAP pin to the
AVSS pin, is required. The internal clock of the PLL
can be output to the CLKIO to drive other converters
or controllers. If not used, disable the clock output to
reduce device power consumption; see Table 1 for
settings. The clock output is enabled by a register bit
setting (default is ON). Figure 39 shows the oscillator
connections. Place these components as close to the
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
The oscillator start-up time may vary, depending on
the crystal and ambient temperature. The user

Figure 40. External Clock Connection

should verify the oscillator start-up time.

16

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