TEXAS INSTRUMENTS ADS1258 Technical data

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24−Bit

ADC

Digital

Filter

Internal

Monitoring

16:1

Analog

Input
MUX

1

16

AINCOM

…

ADC

In

Extclk
In/Out

AVSS DGND

AVDD DVDD

MUX

Out

SPI

Interface

CS
DRDY
SCLK
DIN
DOU T

ControlOscillator

GPIO

START
RESET
PWDN

GPIO[7:0]V

REF

ADS1258

Analog Inputs

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SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

16-Channel, 24-Bit Analog-to-Digital Converter

FEATURES DESCRIPTION

• 24 Bits, No Missing Codes

• Fixed-Channel or Automatic Channel Scan

• Fixed-Channel Data Rate: 125kSPS

• Auto-Scan Data Rate: 23.7kSPS

• Single-Conversion Settled Data multiplexer accepts combinations of eight differential

• 16 Single-Ended or 8 Differential Inputs

• Unipolar (+5V) or Bipolar ( ± 2.5V) Operation

• Low Noise: 2.8µV

at 1.8kSPS

RMS

• 0.0003% Integral Nonlinearity

• DC Stability (typical): The differential output of the multiplexer is accessible

0.02µV/ ° C Offset Drift, 0.4ppm/ ° C Gain Drift

• Open-Sensor Detection

• Conversion Control (Pin and Commands)

• Multiplexer Output for External Signal

Conditioning

• On-Chip Temperature, Reference, Offset,

Gain, and Supply Voltage Readback

• 42mW Power Dissipation

• Standby, Sleep, and Power-Down Modes

• 8 General-Purpose Inputs/Outputs (GPIO)

• 32.768kHz Crystal Oscillator or External Clock

The ADS1258 is a 16-channel (multiplexed),
low-noise, 24-bit, delta-sigma ( ∆ Σ ) analog-to-digital
converter (ADC) that provides single-cycle settled
data at channel scan rates from 1.8k to 23.7k
samples per second (SPS). A flexible input

or 16 single-ended inputs with a full-scale differential
range of 5V or true bipolar range of ± 2.5V when
operating with a 5V reference. The fourth-order
delta-sigma modulator is followed by a fifth-order sinc
digital filter optimized for low-noise performance.

to allow signal conditioning prior to the input of the
ADC. Internal system monitor registers provide
supply voltage, temperature, reference voltage, gain,
and offset data.

An onboard PLL generates the system clock from a

32.768kHz crystal, or can be overridden by an
external clock source. A buffered system clock output
(15.7MHz) is provided to drive a microcontroller or
additional converters.

Serial digital communication is handled via an
SPI™-compatible interface. A simple command word
structure controls channel configuration, data rates,
digital I/O, monitor functions, etc.

ADS1258

APPLICATIONS

• Medical, Avionics, and Process Control

• Machine and System Monitoring

• Fast Scan Multi-Channel Instrumentation

• Industrial Process Controls

• Test and Measurement Systems

SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Programmable sensor bias current sources can be
used to bias sensors or verify sensor integrity.

The ADS1258 operates from a unipolar +5V or
bipolar ± 2.5V analog supply and a digital supply
compatible with interfaces ranging from 2.7V to

5.25V. The ADS1258 is available in a QFN-48
package.

Copyright © 2005, Texas Instruments Incorporated

www.ti.com

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted).

AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +5.5 V
Input Current 100, Momentary mA
Input Current 10, Continuous mA
Analog Input Voltage AVSS – 0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 ° C
Operating Temperature Range –40 to +105 ° C
Storage Temperature Range –60 to +150 ° C
Lead Temperature (soldering, 10s) +300 ° C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.

(1)

ADS1258 UNIT

2

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SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS

All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
OPA227 buffer between MUX outputs and ADC inputs, V

PARAMETER CONDITIONS MIN TYP MAX UNIT
Analog Multiplexer Inputs

Absolute Input Voltage AVSS – 100mV AVDD + 100mV V

AINCOM with respect to DGND
On-Channel Resistance 80 Ω
Crosstalk fIN= 1kHz –110 dB

Sensor Bias (Current Source) µA

1.5 µ A:24 µ A Ratio Error 1 %

ADC Input

Full-Scale Input Voltage (V

IN

Absolute Input Voltage (ADCINP, ADCINN) AVSS – 100mV AVDD + 100mV V
Differential Input Impedance 65 k Ω

System Performance

Resolution No Missing Codes 24 Bits
Data Rate, Fixed-Channel Mode 1.953 125 kSPS
Data Rate, Auto-Scan Mode 1.805 23.739 kSPS
Integral Nonlinearity (INL)

(1)

Offset Error Shorted Inputs µ V

Offset Drift

(3)

Gain Error 0.1 0.5 %
Gain Drift

(3)

Noise (see Table 4 )
Common-Mode Rejection fCM= 60Hz 90 100 dB

Power-Supply Rejection fPS= 60Hz dB

Voltage Reference Input

Reference Input Voltage (V

REF

Negative Reference Input (VREFN) AVSS – 0.1V VREFP – 0.5 V
Positive Reference Input (VREFP) VREFN + 0.5 AVDD + 0.1V V
Reference Input Impedance 40 k Ω

System Parameters

External Reference Reading Error 1 3 %
Analog Supply Reading Error 1 3 %
Temperature Sensor Voltage TA= +25 ° C 168 mV

Reading

Digital Input/Output

Logic Levels: V

Input Leakage VIN= DVDD, GND 10 µA

Master Clock Input (CLKIO)

AIN0–AIN15,

= ADCINP – ADCINN) ± 1.0 6V

Chopping Off 20
Chopping On 1 10
Chopping Off 0.5
Chopping On 0.02 0.1

AVDD, AVSS 70 85

DVDD 80 95

= VREFP – VREFN) 0.5 4.096 AVDD – AVSS V

Coefficient 394 µ V/ ° C

IH

V

IL

V

OH

V

OL

Frequency 0.1 16 MHz

Duty Cycle 40 60 %

= +4.096V, and VREFN = –2.5V, unless otherwise noted.

REF

ADS1258

SBCS[1:0] = 01 1.5
SBCS[1:0] = 11 24

Differential Input 0.0003 0.0010 % of FSR

Shorted Inputs µ V/ ° C

0.7DVDD DVDD V
DGND 0.3DVDD V

IOH= 2mA 0.8DVDD DVDD V
IOL= 2mA DGND 0.2DVDD V

= 16MHz (external clock),

CLK

REF

0.4 2 ppm/ ° C

ADS1258

V

(2)

(1) Best straight line fit method.
(2) FSR = Full-scale range = 2.1 3V
(3) Ensured by characterization.

.

REF

3

www.ti.com

Top View QFN

36
35
34
33
32
31
30
29
28
27
26
25

AIN12
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
START
DRDY

AIN4

AIN5

AIN6

AIN7

MUXOUTP

MUXOUTN

ADCINP

ADCINN

AIN8

AIN9

AIN10

AIN11

CLKIO

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

SCLK

DIN

DOUT

1
2
3
4
5
6
7
8

9
10
11
12

AIN3
AIN2
AIN1
AIN0

AVSS

AVDD

PLLCAP

XTAL1
XTAL2
PWDN

RESET

CLKSEL

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 233724

ADS1258

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= –40 ° C to +105 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
OPA227 buffer between MUX outputs and ADC inputs, V

PARAMETER CONDITIONS MIN TYP MAX UNIT

Crystal Frequency 32.768 kHz

Crystal Oscillator
(see Crystal Oscillator
section)

Start-Up Time (Clock Output Valid) 150 mS

Power Supply

DVDD 2.7 5.25 V
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V

DVDD Supply Current

AVDD, AVSS Supply Current

Power Dissipation

Clock Output Frequency 15.729 MHz

Clock Output Duty Cycle 40 60 %

= +4.096V, and VREFN = –2.5V, unless otherwise noted.

REF

ADS1258

External Clock

Operation

Internal Oscillator

Operation, Clock 0.04 mA

Output Disabled

Internal Oscillator

Operation, Clock 1.4 mA

Output Enabled

Power-Down

(4)

(5)

Converting 8.2 12 mA

Standby 5.6 mA

Sleep 2.1 mA

Power-Down 2 85 µA

Converting 42 62 mW

Standby 29 mW

Sleep 11 mW

Power-Down 14 µ W

= 16MHz (external clock),

CLK

0.25 0.6 mA

1 25 µA

(4) CLKIO load = 20pF.
(5) No clock applied to CLKIO.

PIN CONFIGURATION

4

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SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

PIN ASSIGNMENTS

PIN # NAME INPUT/OUTPUT DESCRIPTION

1 AIN3 Analog Input Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–)
2 AIN2 Analog Input Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+)
3 AIN1 Analog Input Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–)
4 AIN0 Analog Input Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+)

5 AVSS Analog
6 AVDD Analog Positive Analog Power Supply: +5V for unipolar operation, +2.5V for bipolar operation.

7 PLLCAP Analog PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator.
8 XTAL1 Analog 32.768kHz Crystal Oscillator Input 1; see Crystal Oscillator section.

9 XTAL2 Analog 32.768kHz Crystal Oscillator Input 2; see Crystal Oscillator section.
10 PWDN Digital Input Power-Down Input: Hold low for minimum of two f
11 RESET Digital Input Reset Input: Hold low for minimum of two f

12 CLKSEL Digital Input
13 CLKIO Digital I/O System Clock Input/Output (See CLKSEL pin.)

14 GPIO0 Digital I/O General-Purpose Digital Input/Output 0
15 GPIO1 Digital I/O General-Purpose Digital Input/Output 1
16 GPIO2 Digital I/O General-Purpose Digital Input/Output 2
17 GPIO3 Digital I/O General-Purpose Digital Input/Output 3
18 GPIO4 Digital I/O General-Purpose Digital Input/Output 4
19 GPIO5 Digital I/O General-Purpose Digital Input/Output 5
20 GPIO6 Digital I/O General-Purpose Digital Input/Output 6
21 GPIO7 Digital I/O General-Purpose Digital Input/Output 7
22 SCLK Digital Input SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge.
23 DIN Digital Input SPI Interface Data Input: Data is input to the device.
24 DOUT Digital Output SPI Interface Data Output: Data is output from the device.
25 DRDY Digital Output Data Ready Output: Active low.
26 START Digital Input Start Conversion Input: Active high.
27 CS Digital Input SPI Interface Chip Select Input: Active low.
28 DVDD Digital Digital Power Supply: 2.7V to 5.25V
29 DGND Digital Digital Ground
30 VREFN Analog Input Reference Input Negative
31 VREFP Analog Input Reference Input Positive
32 AINCOM Analog Input Analog Input Common: Common input pin to all single-ended inputs.
33 AIN15 Analog Input Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–)
34 AIN14 Analog Input Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+)
35 AIN13 Analog Input Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–)
36 AIN12 Analog Input Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+)
37 AIN11 Analog Input Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–)
38 AIN10 Analog Input Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+)
39 AIN9 Analog Input Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–)
40 AIN8 Analog Input Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+)
41 ADCINN Analog Input ADC Differential Input (–)
42 ADCINP Analog Input ADC Differential Input (+)
43 MUXOUTN Analog Output Multiplexer Differential Output (–)
44 MUXOUTP Analog Output Multiplexer Differential Output (+)
45 AIN7 Analog Input Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–)
46 AIN6 Analog Input Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+)
47 AIN5 Analog Input Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–)
48 AIN4 Analog Input Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+)

ANALOG/DIGITAL

Negative Analog Power Supply: 0V for unipolar operation, –2.5V for bipolar operation.
(Internally connected to exposed thermal pad of QFN package.)

cycles to engage low-power mode.

CLK

cycles to reset the device.

CLK

Clock Select Input: Low = Activates Crystal Oscillator, f
High = Disables Crystal Oscillator, apply f

to CLKIO.

CLK

output on CLKIO.

CLK

ADS1258

5

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SCLK

CS

(1)

DIN

DOUT

t

SCLK

t

CSSC

t

SPW

t

DIST

t

DIHD

t

SPW

t

CSDO

t

DOPD

t

DOHD

NOTE: (1) CS can be tied low.

DRDY

DOUT

t

DRDY

t

DDO

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

SYMBOL DESCRIPTION MIN MAX UNITS

t

SCLK

t

SPW

t

CSSC

t

DIST

t

DIHD

t

DOPD

t

DOHD

t

CSDO

(1) τ

CLK

(2) Programmable to 256 τ
(3) CS can be tied low.
(4) DOUT load = 20 pF || 100k Ω to DGND.

SCLK Period 2 τ
SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 4096
CS Low to First SCLK: Setup Time

(3)

0.5 τ
Valid DIN to SCLK Rising Edge: Setup Time 10 ns
Valid DIN to SCLK Rising Edge: Hold Time 5 ns
SCLK Falling Edge to Valid New DOUT: Propagation Delay

(4)

SCLK Falling Edge to Old DOUT Invalid: Hold Time 0 ns
CS High to DOUT Invalid (tri-state) 5 τ

= master clock period = 1/f

CLK

.

CLK

.

(2)

5 ns

(1)

CLK

τ

CLK
CLK

CLK

Figure 2. DRDY Update Timing

DRDY UPDATE TIMING CHARACTERISTICS

SYMBOL DESCRIPTION TYP UNITS

t

DRDY

t

DDO

6

DRDY High Pulse Width Without Data Read 1 τ
Valid DOUT to DRDY Falling Edge ( CS = 0) 0.5 τ

CLK
CLK

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TYPICAL CHARACTERISTICS

Number of Occurences

Offset (µV)

3000

2500

2000

1500

1000

500

0

−

50

−

45

−

40

−

35

−

30

−

25

−

20

−

15

−

10

505

10

15

20

25

30

35

40

45

50

DRATE[1:0] = 11
16384 Points

Number of Occurences

Offset (µV)

4500
4000
3500
3000
2500
2000
1500
1000

500

0

−

35

−

30

−

25

−

20

−

15

−

10

−

5

0

5

10

15

20

25

30

35

DRATE[1:0] = 10
16384 Points

Number of Occurences

Offset (µV)

3500

3000

2500

2000

1500

1000

500

0

−

20

−

16

−

12

−

8

−

4

0

4

8

12

16

20

DRATE[1:0] = 01
16384 Points

Number of Occurences

Offset (µV)

2500

2000

1500

1000

500

0

−

12

−

10

−

8

−

6

−

4

−

2

0

2

4

6

8

10

12

DRATE[1:0] = 00
16384 Points

RMS Noise (

µ

V)

Input Voltage (%FS)

20

15

10

5

0

−

100−75 10075

−50−

25 50250

DRATE[1:0] = 11

DRATE[1:0] = 10

DRATE[1:0] = 01

DRATE[1:0] = 00

Number of Occurences

RMS Noise (µV)

20

15

10

5

0

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

15.0

50 units from twoproduction lots.
DRATE[1:0] = 11

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f

outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

READING HISTOGRAM READING HISTOGRAM

Figure 3. Figure 4.

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

= 16MHz (external), OPA227 buffer between MUX

CLK

ADS1258

READING HISTOGRAM READING HISTOGRAM

Figure 5. Figure 6.

NOISE HISTOGRAM NOISE vs INPUT VOLTAGE

Figure 7. Figure 8.

7

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RMS Noise (

µ

V)

V

REF

(V)

16
14
12
10

8
6
4
2
0

0.5 1.5 5.52.5 3.5 4.5

DRATE[1:0] = 11

DRATE[1:0] = 10

DRATE[1:0] = 01

DRATE[1:0] = 00

RMS Noise (

µ

V)

DVDD, AVDD−AVSS (V)

20
18
16
14
12
10

8
6
4

2.5 3.0 5.53.5 4.0 4.5 5.0

DRATE[1:0] = 11

from DVDD

from AVDD−AVSS

RMS Noise (

µ

V)

Temperature (C)

20
18
16
14
12
10

8
6
4

−40−

20 0

20 40 60 80 100

DRATE[1:0] = 11

RMS Noise (

µ

V)

Common−Mode Input Voltage(V)

20

15

10

5

0

Offset (

µ

V)

5

0

−

5

−

10

−

15

−

3

−

2 3

−

1 0 1 2

OFFSET

CHOP = 1

OFFSET

CHOP = 0

NOISE

Number of Occurences

Offset (µV)

200
180
160
140
120
100

80
60
40
20

0

−

10

−

8

−

6

−

4

−

2

0

2

4

6

8

10

311 units fromone production lot.
CHOP = 1

Number of Occurences

Offset Drift (µV/C)

80

60

40

20

0

−

0.10

−

0.09

−

0.08

−

0.07

−

0.06

−

0.05

−

0.04

−

0.03

−

0.02

−

0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

50 units from two
production lots.
Based on 20C intervals
over the range of

−

40C to +105C.

CHOP = 1

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

= 16MHz (external), OPA227 buffer between MUX

CLK

NOISE vs V

REF

NOISE vs SUPPLY VOLTAGE

Figure 9. Figure 10.

NOISE AND OFFSET vs

NOISE vs TEMPERATURE COMMON-MODE INPUT VOLTAGE

8

Figure 11. Figure 12.

OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM

Figure 13. Figure 14.

www.ti.com

Normalized Offset (

µ

V)

Temperature (C)

20

0

−

20

−

40

−

60

−

40−20 100

0 20 806040

CHOP = 1

CHOP = 1, NoBuffer

CHOP = 0, No Buffer

50 Units from
2 Production Lots

Normalized Offset (

µ

V)

V

REF

(V)

0.5 1.0

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

5.51.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Normalized Offset (

µ

V)

Time After Power−On (s)

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

0 10 6020 30 40 50

Free−Air

Number of Occurences

Absolute Gain Error (ppm)

80

60

40

20

0

100

300

500

700

900

1100

1300

1500

1700

1900

320 units from one production lot.

Normalized Gain Error (ppm)

Temperature (C)

30

20

10

0

−

10

−

40−20 100

0 20 806040

Number of Occurences

Gain Drift (ppm/C)

80

60

40

20

0

−

1.8

−

1.6

−

1.4

−

1.2

−

1.0

−

0.8

−

0.6

−

0.4

−

0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

50 units from two production lots.
Based on 20C intervals over the
range of−40C to +105C.

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

= 16MHz (external), OPA227 buffer between MUX

CLK

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

OFFSET vs TEMPERATURE OFFSET vs V

Figure 15. Figure 16.

OFFSET POWER-ON WARMUP GAIN ERROR HISTOGRAM

REF

GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE

Figure 17. Figure 18.

Figure 19. Figure 20.

9

www.ti.com

Normalized Gain Error (ppm)

V

REF

(V)

20
15
10

5
0

−

5

−

10

−

15

−

20

0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5

Normalized Gain Error (ppm)

Time After Power−On (s)

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

0 10 6020 30 40 50

Free−Air

Linearity Error (ppm)

V

REF

(V)

10

8

6

4

2

0

0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5

Linearity Error (ppm)

VIN(V)

−5−

4

10

8
6
4
2
0

−

2

−

4

−

6

−

8

−

10

5

−3−2−

1 0 1 2 3 4

V

REF

= 5V

TA=−40C,−10C, +25C, +55C, +85C, +105C

INL (ppm)

Temperature (C)

8

6

4

2

0

−40−

20 120100

0 20 806040

Level (dBFS)

Frequency (Hz)

0

−

20

−

40

−

60

−

80

−

100

−

120

−

140

−

160

−

180

1 10 100k100 1k 10k

f = 1kHz,−0.5dBFs
DRATE[1:0] = 11
65536 Points

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

= 16MHz (external), OPA227 buffer between MUX

CLK

GAIN ERROR vs V

REF

Figure 21. Figure 22.

INTEGRAL NONLINEARITY vs V

GAIN ERROR POWER-ON WARMUP

REF

INTEGRAL NONLINEARITY vs INPUT LEVEL

INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM

10

Figure 23. Figure 24.

Figure 25. Figure 26.

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Temperature Sensor Voltage (mV)

Temperature (C)

210

200

190

180

170

160

150

140

−40−

20 12040

0 20 60 80 100

Number of Occurences

Temperature Reading (C)

8
7
6
5
4
3
2
1
0

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

50 units from two production lots.
TA= +25C

Ratio (

µ

A/

µ

A)

Temperature (C)

18

17

16

15

14

−40−

20 120100

0 20 806040

Number of Occurences

Ratio (µA/µA)

25

20

15

10

5

0

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

50 units from two production lots.

AVDD, AVSS Current (mA)

Temperature (C)

10

8

6

4

2

0

DVDD Current (mA)

1.0

0.8

0.6

0.4

0.2

0

−40−

20 1200 20 40 60 80 100

AVDD, AVSS

DVDD

RMS Noise (

µ

V)

Master Clock (MHz)

20

16

12

8

4

0

Linearity Error (ppm)

20

16

12

8

4

0

0.1 1 10010

DRATE[1:0] = 11

Noise

Linearity

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, f
outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.

TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM

Figure 27. Figure 28.

= 16MHz (external), OPA227 buffer between MUX

CLK

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

SENSOR BIAS CURRENT SOURCE RATIO SENSOR BIAS CURRENT SOURCE RATIO

HISTOGRAM vs TEMPERATURE

Figure 29. Figure 30.

SUPPLY CURRENT vs TEMPERATURE NOISE AND INL vs MASTER CLOCK

Figure 31. Figure 32.

11

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AIN0

AIN1
AIN2
AIN3
AIN4
AIN5

AIN6
AIN7
AIN8
AIN9

AIN10
AIN11
AIN12
AIN13
AIN14
AIN15

AINCOM

Control

Logic

VREFPVREFN

AVSS

PLLCAP XTAL1XTAL2

DRDY
PWDN
RESET
START

SPI

Interface

CS
SCLK
DIN
DOUT

Digital Filter

Clock Control

16−Channel

MUX

AVDD

Sensor

Bias

M

UXOUTP

MUX

OUTN

ADCINP GND

AD

CINN

ADC Channel Control

Supply Monitor

GPIO

G

PIO[7:0]

DVDD

Temperature

Ext Ref Monitor

Internal Ref

ADC

CLKSELCLKIO

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

The ADS1258 is a flexible, 24-bit, low-noise ADC
optimized for fast multi-channel, high-resolution
measurement systems. The converter provides a
maximum channel scan rate of 23.7kSPS, providing a
complete 16-channel scan in less than 700µs.

Figure 33 shows the block diagram of the ADS1258.

The input multiplexer selects the analog input pins
connected to the multiplexer output pins
(MUXOUTP/MUXOUTN). External signal conditioning
can be used between the multiplexer output pins and
the ADC input pins (ADCINP/ADCINN) or the
multiplexer output can be routed internally to the ADC
inputs without external circuitry. Selectable current
sources within the input multiplexer can be used to
bias sensors or detect for a failed sensor. On-chip
system function readings provide readback of
temperature, supply voltage, gain, offset, and external
reference. The ADS1258 converter is comprised of a
fourth-order, delta-sigma modulator followed by a
programmable digital filter. The modulator measures
the differential input signal V
against the differential reference input V

IN

= (ADCINP – ADCINN)

REF

OVERVIEW

(VREFP – VREFN). The digital filter receives the
modulator signal and provides a low-noise digital
output. The ADC channel block controls the
multiplexer Auto-Scan feature. Channel Auto-Scan
occurs at a maximum rate of 23.7kSPS. Slower scan
rates can be used with corresponding increases in
resolution.

Communication is handled over an SPI-compatible
serial interface with a set of simple commands
providing control of the ADS1258. Onboard registers
store the various settings for the input multiplexer,
sensor detect bias, data rate selection, etc. Either an
external 32.768kHz crystal, connected to pins XTAL1
and XTAL2, or an external clock applied to pin CLKIO
can be used as the clock source. When using the
external crystal oscillator, the system clock is
available as an output for driving other devices or
controllers. General-purpose digital I/Os (GPIO)
provide input and output control of eight pins.

=

12

Figure 33. ADS1258 Block Diagram

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AVSS 100mV VREFP or VREFN AVDD 100mV

ESD
Diodes

ESD
Diodes

3pF

R

eff

= 40k

Ω

(f

CLK

= 16MHz)

AVDD

AVSS

VREFP

VREFN

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

MULTIPLEXER INPUTS

A simplified diagram of the input multiplexer is
illustrated in Figure 35 . The multiplexer connects one
of 16 single-ended external inputs, one of eight
differential external inputs, or one of the on-chip
internal variables to the ADC inputs. The output of the
channel multiplexer can be routed to external pins
and then to the input of the ADC. This flexibility
allows for use of external signal conditioning. See the

External Multiplexer Loop section.

ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
100mV, and likewise do not exceed AVDD by more
than 100mV:

AVSS – 100mV < (Analog Inputs) < AVDD + 100mV.
The converter supports two modes of channel access

through the multiplexer: the Auto-Scan mode and the
Fixed-Channel mode. These modes are selected by
the MUXMOD bit of register CONFIG0. The
Auto-Scan mode scans through the selected
channels automatically, with break-before-make
switching. The Fixed-Channel mode requires the user
to set the channel address for each channel
measured.

ESD diodes protect the reference inputs. To keep
these diodes from turning on, make sure the voltages
on the reference pins do not go below AVSS by more
than 100mV, and likewise do not exceed AVDD by
100mV, as described in Equation 1 :

(1)

A high-quality reference voltage is essential for
achieving the best performance from the ADS1258.
Noise and drift on the reference degrade overall
system performance. It is especially critical that
special care be given to the circuitry that generates
the reference voltages and the layout when operating
in the low-noise settings (that is, with low data rates)
to prevent the voltage reference from limiting
performance. See the Reference Inputs description in
the Hardware Considerations segment of the

Applications section.

VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)

The voltage reference for the ADS1258 ADC is the
differential voltage between VREFP and VREFN:
V

= VREFP – VREFN. The reference inputs use a

REF

structure similar to that of the analog inputs with the
circuitry on the reference inputs shown in Figure 34 .
The load presented by the switched capacitor can be
modeled with an effective resistance (R
f

= 16MHz. Note that the effective impedance of

CLK

the reference inputs will load an external reference
with a non-zero source impedance.

) of 40k Ω for

eff

Figure 34. Simplified Reference Input Circuit

13

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ADC

AIN0

VREFN

VREFP

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AINCOM

Multiplexer

Reference/Gain Monitor

NOTE: ESD diodes not shown.

Supply Monitor

AVDD

AVSS

AVDD
AVSS

Temperature Sensor Monitor

1x 2x

8x 1x

AVDD

(AVDD−AVSS)/2

AVSS

Sensor Bias Offset Monitor

MUXOUTP

MUXOUTN

ADCINP

ADCINN

Internal
Reference

AVSS

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

Figure 35. Input Multiplexer

14

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t

SAMPLE

ON

OFF

S

1

S

2

OFF

ON

S

1

S

1

AVSS + 1.3V

R

AIN

= R

effB

|| 2R

effA

AVSS + 1.3V

R

effA

= 190k

Ω

R

effB

= 78kΩ(f

CLK

= 16MHz)

R

effA

= 190k

Ω

ADCINN

ADCINP

CA1= 0.65pF

CB= 1.6pF

C

A2

= 0.65pF

ADCINN

S

2

AVSS + 1.3V

S

2

AVSS + 1.3V

ADCINP

Equivalent

Circuit

R

eff

= t

SAMPLE/CX

NOTE: ESD input diodes not shown.

ADS1258

SBAS297A – JUNE 2005 – REVISED SEPTEMBER 2005

ADC INPUTS

The ADS1258 ADC inputs (ADCINP, ADCINN)
measure the input signal using internal capacitors

R

= V

eff

with f

IN/IAVERAGE

. For example, if f

CLK

two, the impedances will double.

. These impedances scale inversely

is reduced by a factor of

CLK

that are continuously charged and discharged. The As with the multiplexer and reference inputs, ESD
left side of Figure 37 shows a simplified schematic of diodes protect the ADC inputs. To keep these diodes
the ADC input circuitry; the right side of Figure 37 from turning on, make sure the voltages on the input
shows the input circuitry with the capacitors and pins do not go below AVSS by more than 100mV,
switches replaced by an equivalent circuit. Figure 36 and likewise do not exceed AVDD by more than
shows the ON/OFF timings of the switches shown in 100mV.

Figure 37 . S

sampling phase. With S
ADCINP, C
(ADCINP – ADCINN). For the discharge phase, S
opens first and then S
to approximately AVSS + 1.3V and C

switches close during the input

1

charges to ADCINN, and C

A2

2

1

closes. C

closed, C

charges to

A1

charges to

B

and C

A1

discharge

A2

discharges to

B

1

0V. This two-phase sample/discharge cycle repeats
with a period of t

SAMPLE

= 2/f

.

CLK

The charging of the input capacitors draws a transient
current from the source driving the ADS1258 ADC
inputs. The average value of this current can be used
to calculate an effective impedance (R

) where

eff

Figure 36. S1and S

Switch Timing for Figure 37

2

Figure 37. Simplified ADC Input Structure

15