TEXAS INSTRUMENTS ADS1255, ADS1256 Technical data
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
查询ADS1255供应商查询ADS1255供应商
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
FEATURES
D 24 Bits, No Missing Codes
− All Data Rates and PGA Settings
D Up to 23 Bits Noise-Free Resolution
D ±0.0010% Nonlinearity (max)
D Data Output Rates to 30kSPS
D Fast Channel Cycling
− 18.6 Bits Noise-Free (21.3 Effective Bits)
at 1.45kHz
D One-Shot Conversions with Single-Cycle
Settling
D Flexible Input Multiplexer with Sensor Detect
− Four Differential Inputs (ADS1256 only)
− Eight Single-Ended Inputs (ADS1256 only)
D Chopper-Stabilized Input Buffer
D Low-Noise PGA: 27nV Input-Referred Noise
D Self and System Calibration for All PGA
Settings
D 5V Tolerant SPI-Compatible Serial Interface
D Analog Supply: 5V
D Digital Supply: 1.8V to 3.6V
D Power Dissipation
− As Low as 38mW in Normal Mode
− 0.4mW in Standby Mode
AVDD DVDD
APPLICATIONS
D Weigh Scales
D Scientific Instrumentation
D Industrial Process Control
D Medical Equipment
D Test and Measurement
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
ADS1256 Only
AIN7
AINCOM
Mux
and
Sensor
Detect
DESCRIPTION
The ADS1255 and ADS1256 are extremely low-noise,
24-bit analog-to-digital (A/D) converters. They provide
complete high-resolution measurement solutions for the
most demanding applications.
The converter is comprised of a 4th-order, delta-sigma
(∆Σ) modulator followed by a programmable digital filter. A
flexible input multiplexer handles differential or
single-ended signals and includes circuitry to verify the
integrity of the external sensor connected to the inputs.
The selectable input buffer greatly increases the input
impedance and the low-noise programmable gain
amplifier (PGA) provides gains from 1 to 64 in binary steps.
The programmable filter allows the user to optimize
between a resolution of up to 23 bits noise-free and a data
rate of up to 30k samples per second (SPS). The
converters offer fast channel cycling for measuring
multiplexed inputs and can also perform one-shot
conversions that settle in just a single cycle.
Communication is handled over an SPI-compatible serial
interface that can operate with a 2-wire connection.
Onboard calibration supports both self and system
correction of o ffset and gain errors for all the PGA settings.
Bidirectional digital I/Os and a programmable clock output
driver are provided for general use. The ADS1255 is
packaged in an SSOP-20, and the ADS1256 in an
SSOP-28.
VREFP VREFN
Clock
Generator
1:64
Buffer
PGA
4th−Order
Modulator
General
Purpose
Digital I/O
Programmable
Digital Filter
Control
Serial
Interface
XTAL1/CLKIN
XTAL2
RESET
SYNC/PDWN
DRDY
SCLK
DIN
DOUT
CS
D3 D2 D1 D0/CLKOUTAGND
ADS1256
Only
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
!"#$! # %& '( % )(*' +, +('
'%& )'%' ) - & % #. $(& ++ ,
+(' )' + ' '(+ % )&,
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Copyright 2003−2004, Texas Instruments Incorporated
DGND
ADS1255
SSOP-20
DB
ADS1255IDB
ADS1256
SSOP-28
DB
ADS1256IDB
Input Current
l
inputs
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
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ORDERING INFORMATION
PRODUCT PACKAGE-LEAD
(1)
For the most current package and ordering information, refer to our web site at www.ti.com.
(1)
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ABSOLUTE MAXIMUM RATINGS
over operat i n g f ree-air temperature range unless otherwise noted
ADS1255, ADS1256 UNIT
AVDD to AGND −0.3 to +6 V
DVDD to DGND −0.3 to +3.6 V
AGND to DGND −0.3 to +0.3 V
100, Momentary mA
10, Continuous mA
Analog inputs to AGND −0.3 to AVDD + 0.3 V
DIN, SCLK, CS, RESET,
SYNC/PDWN,
Digita
XTAL1/CLKIN to DGND
D0/CLKOUT, D1, D2, D3
to DGND
Maximum Junction Temperature +150 °C
Operating Temperature Range −40 to +105 °C
Storage Temperature Range −60 to +150 °C
Lead Tem perature (soldering, 10s) +300 °C
(1)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
−0.3 to +6 V
−0.3 to DVDD + 0.3 V
(1)
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING NUMBER
ADS1255IDBT Tape and Reel, 250
ADS1255IDBR Tape and Reel, 1000
ADS1256IDBT Tape and Reel, 250
ADS1256IDBR Tape and Reel, 1000
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
TRANSPORT MEDIA,
QUANTITY
2
Absolute input voltage
Differential input impedance
Sensor detect current sources
Integral nonlinearity
Offset drift
Gain error
Gain drift
Negative reference input (VREFN)
Positive reference input (VREFP)
IH
V
IH
Master clock rate
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Inputs
Full-scale input voltage (AINP − AINN) ±2V
Absolute input voltage
(AIN0-7, AINCOM to AGND)
Programmable gain amplifier 1 64
Differential input impedance
Sensor detect current sources
System Performance
Resolution 24 Bit
No missing codes All data rates and PGA settings 24 Bit
Data rate (f
Offset error After calibration On the level of the noise
Common-mode rejection f
Noise See Noise Performance Tables
AVDD power-supply rejection ±5% ∆ in AVDD 60 70 dB
DVDD power-supply rejection ±10% ∆ in DVDD 100 dB
Voltage Reference Inputs
Reference input voltage (V
Voltage reference impedance f
Digital Input/Output
V
V
IL
V
OH
V
OL
Input hysteresis 0.5 V
Input leakage 0 < V
Master clock rate
) f
DATA
REF
) V
Buffer off AGND − 0.1 AVDD + 0.1 V
Buffer on AGND AVDD − 2.0 V
Buffer off, PGA = 1, 2, 4, 8, 16 150/PGA kΩ
Buffer off, PGA = 32, 64 4.7 kΩ
Buffer on, f
SDCS[1:0] = 01 0.5 µA
SDCS[1:0] = 10 2 µA
SDCS[1:0] = 11 10 µA
= 7.68MHz 2.5 30,000 SPS
CLKIN
Differential input, PGA = 1 ±0.0003 ±0.0010 %FSR
Differential input, PGA = 64 ±0.0007 %FSR
PGA = 1 ±100 nV/°C
PGA = 64 ±4 nV/°C
After calibration, PGA = 1, Buffer on ±0.005 %
After calibration, PGA = 64, Buffer on ±0.03 %
PGA = 1 ±0.8 ppm/°C
PGA = 64 ±0.8 ppm/°C
(4)
= 60Hz, f
CM
≡ VREFP − VREFN 0.5 2.5 2.6 V
REF
Buffer off AGND − 0.1 VREFP − 0.5 V
Buffer on
Buffer off VREFN + 0.5 AVDD + 0.1 V
Buffer on
= 7.68MHz 18.5 kΩ
CLKIN
DIN, SCLK, XTAL1/CLKIN,
SYNC/PDWN, CS, RESET
D0/CLKOUT, D1, D2, D3 0.8 DVDD DVDD V
IOH = 5mA 0.8 DVDD V
IOL = 5mA 0.2 DVDD V
DIGITAL INPUT
External crystal between XTAL1 and
XTAL2
External oscillator driving CLKIN 0.1 7.68 10 MHz
(6)
(6)
DATA
≤ 50Hz
DATA
< DVDD ±10 µA
= 7.68MHz, PGA = 1, and V
CLKIN
(1)
= 30kSPS
(5)
= +2.5V , unless otherwise noted.
REF
/PGA V
REF
80 MΩ
95 110 dB
AGND VREFP − 0.5 V
VREFN + 0.5 AVDD − 2.0 V
0.8 DVDD 5.25 V
DGND 0.2 DVDD V
2 7.68 10 MHz
(2)
(3)
3
AVDD current
DVDD current
Power dissipation
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
PARAMETER UNITMAXTYPMINTEST CONDITIONS
Power-Supply
AVDD 4.75 5.25 V
DVDD 1.8 3.6 V
Power-down mode 2 µA
Standby mode 20 µA
Normal mode, PGA = 1, Buffer off 7 10 mA
Normal mode, PGA = 64, Buffer off 16 22 mA
Normal mode, PGA = 1, Buffer on 13 19 mA
Normal mode, PGA = 64, Buffer on 36 50 mA
Power-down mode 2 µA
Standby mode, CLKOUT off,
DVDD current
Power dissipation
Temperature Range
Specified −40 +85 °C
Operating −40 +105 °C
Storage −60 +150 °C
(1)
See text for more information on input impedance.
(2)
SPS = samples per second.
(3)
FSR = full-scale range = 4V
(4)
fCM is the frequency of the common-mode input signal.
(5)
Placing a notch of the digital filter at 60Hz (setting f
common-mode rejection of this frequency.
(6)
The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration or
writing calibration values directly to the registers, the entire Buffer off range can be used.
REF
DVDD = 3.3V
Normal mode, CLKOUT off,
DVDD = 3.3V
Normal mode, PGA = 1, Buffer off,
DVDD = 3.3V
Standby mode, DVDD = 3.3V 0.4 mW
/PGA.
= 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve the
DATA
= 7.68MHz, PGA = 1, and V
CLKIN
= +2.5V , unless otherwise noted.
REF
95 µA
0.9 2 mA
38 57 mW
4
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ANALOG/DIGITAL
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PIN ASSIGNMENTS
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
AIN1
SYNC, PDWN
RESET
DVDD
SSOP P ACKAGE
(TOP VIEW)
1
2
3
4
5
ADS1255 ADS1256
6
7
8
9
10 11
D1
20
D0/CLKOUT
19
SCLK
18
DIN
17
DOUT
16
15
DRDY
CS
14
XTAL1/CLKIN
13
XTAL2
12
DGND
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
SYNC, PDWN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Terminal Functions
TERMINAL NO.
NAME ADS1255 ADS1256
AVDD 1 1 Analog Analog power supply
AGND 2 2 Analog Analog ground
VREFN 3 3 Analog input Negative reference input
VREFP 4 4 Analog input Positive reference input
AINCOM 5 5 Analog input Analog input common
AIN0 6 6 Analog input Analog input 0
AIN1 7 7 Analog input Analog input 1
AIN2 — 8 Analog input Analog input 2
AIN3 — 9 Analog input Analog input 3
AIN4 — 10 Analog input Analog input 4
AIN5 — 11 Analog input Analog input 5
AIN6 — 12 Analog input Analog input 6
AIN7 — 13 Analog input Analog input 7
SYNC/PDWN 8 14 Digital input
RESET 9 15 Digital input
DVDD 10 16 Digital Digital power supply
DGND 11 17 Digital Digital ground
XTAL2 12 18 Digital
XTAL1/CLKIN 13 19 Digital/Digital input
CS 14 20 Digital input
DRDY 15 21 Digital output: active low Data ready output
DOUT 16 22 Digital output Serial data output
DIN 17 23 Digital input
SCLK 18 24 Digital input
D0/CLKOUT 19 25 Digital IO
D1 20 26 Digital IO
D2 — 27 Digita l IO
D3 — 28 Digita l IO
(1)
Schmitt-Trigger digital input.
(2)
5V tolerant digital input.
(3)
Leave disconnected if external clock input is applied to XTAL1/CLKIN.
(4)
Schmitt-Trigger digital input when the digital I/O is configured as an input.
INPUT/OUTPUT
(1)(2)
: active low Synchronization / power down input
(1)(2)
: active low Reset input
(3)
(1)(2)
: active low Chip select
(1)(2)
(1)(2)
(4)
(4)
(4)
(4)
(2)
Crystal oscillator connection
Crystal oscillator connection / external clock input
Serial data input
Serial clock input
Digital I/O 0 / clock output
Digital I/O 1
Digital I/O 2
Digital I/O 3
DESCRIPTION
D3
28
D2
27
D1
26
D0/CLKOUT
25
SCLK
24
DIN
23
DOUT
22
DRDY
21
20
CS
XTAL1/CLKIN
19
XTAL2
18
DGND
17
DVDD
16
RESET
15
5
t
SCLK period
t
SCLK pulse width: high
Final SCLK falling edge of command to first SCLK
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
CS
SCLK
DIN
DOUT
t
3
t
4
t
1
t
5
Figure 1. Serial Interface Timing
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL DESCRIPTION MIN MAX UNIT
1
2H
t
2L
t
t
t
t
t
t
t
t
10
t
11
(1)
τ
CLKIN
(2)
τ
DATA
(3)
CS can be tied low.
(4)
DOUT load = 20pF 100kΩ to DGND.
SCLK pulse width: low
CS low to first SCLK: setup time
3
Valid DIN to SCLK falling edge: setup time
4
Valid DIN to SCLK falling edge: hold time
5
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
6
RREG Commands
SCLK rising edge to valid new DOUT: propagation delay
7
SCLK rising edge to DOUT invalid: hold time
8
Last SCLK falling edge to DOUT high impedance
9
NOTE: DOUT goes high impedance immediately when CS goes high
(3)
CS low after final SCLK falling edge
RREG, WREG, RDATA
RDATAC, RESET, SYNC
rising edge of next command.
RDATAC, STANDBY, SELFOCAL, SYSOCAL, SELFGCAL,
SYSGCAL, SELFCAL
= master clock period = 1/f
= output data period 1/f
DATA
CLKIN
.
.
(4)
t
2H
t
6
t
7
t
2L
t
8
t
10
t
11
t
9
4 τ
10 τ
CLKIN
DATA
200 ns
9 τ
200 ns
0 ns
50 ns
50 ns
50 τ
50 ns
0 ns
6 10 τ
0 ns
4 τ
24 τ
Wait for DRDY to go low
(1)
(2)
DATA
CLKIN
CLKIN
CLKIN
CLKIN
6
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
SCLK
t
13
t
12
t
13
t
14
t
15
Figure 2. SCLK Reset Timing
TIMING CHARACTERISTICS FOR FIGURE 2
SYMBOL DESCRIPTION MIN MAX UNIT
(1)
t
12
t
13
t
14
t
15
τ
CLKIN
SCLK reset pattern, first high pulse
SCLK reset pattern, low pulse
SCLK reset pattern, second high pulse
SCLK reset pattern, third high pulse
= master clock period = 1/f
CLKIN
.
t
16
RESET, SYNC/PDWN
300 500 τ
5 τ
550 750 τ
1050 1250 τ
CLKIN
Figure 3. RESET and SYNC/PDWN Timing
TIMING CHARACTERISTICS FOR FIGURE 3
SYMBOL DESCRIPTION MIN MAX UNIT
(1)
t
16
τ
CLKIN
RESET, SYNC/PDWN, pulse width
= master clock period = 1/f
CLKIN
.
4 τ
CLKIN
(1)
CLKIN
CLKIN
CLKIN
(1)
t
17
DRDY
Figure 4. DRDY Update Timing
TIMING CHARACTERISTICS FOR FIGURE 4
SYMBOL DESCRIPTION MIN MAX UNIT
(1)
t
17
τ
CLKIN
Conversion data invalid while being updated (DRDY shown with no data retrieval)
= master clock period = 1/f
CLKIN
.
16 τ
CLKIN
(1)
7
OFFSET DRIFT HISTOGRAM
OFFSET DRIFT HISTOGRAM
GAIN ERROR HISTOGRAM
GAIN ERROR HISTOGRAM
GAIN DRIFT HISTOGRAM
GAIN DRIFT HISTOGRAM
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
TA = +25°C, AVDD = 5V, DVDD = 1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V
= 2.5V , unless otherwise noted.
REF
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25
PGA = 1 90 Units from 3 Production Lots
20
15
10
Percent of Population
5
0
500−450−400−350−300−250−200−150−100
−
30
PGA = 1
25
20
15
10
Percent of Population
5
Offset Drift (nV/_C)
0
50
50
−
100
150
200
90 Units from 3 Production Lots
30
PGA = 64
25
20
15
10
Percent of Population
5
0
10
25
20
15
10
Percent of Population
5
−20−18−16−14−12−
PGA = 64
250
300
350
400
450
500
90 Units from 3 Production Lots
2
−8−6−4−
Offset Drift (nV/_C)
02468
90 Units from 3 Production Lots
1012141618
20
0
0.0100−0.0095−0.0090−0.0085−0.0080−0.0075−0.0070−0.0065−0.0060−0.0055−0.0050−0.0045−0.0040−0.0035−0.0030−0.0025−0.0020−0.0015−0.0010−0.0005
−
25
PGA = 1
20
15
10
Percent of Population
5
0
0
0.1
0.2
0.3
Gain Error (%)
0.4
0.5
0.6
0.7
GainDrift (ppm/_C)
90 Units from 3 Production Lots
0.8
0.9
1.0
1.1
1.2
0
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0
0.060−0.057−0.054−0.051−0.048−0.045−0.042−0.039−0.036−0.033−0.030−0.027−0.024−0.021−0.018−0.015−0.012−0.009−0.006−0.003
Percent of Population
25
20
15
10
5
0
−
PGA = 64
0
0.1
0.2
0.3
Gain Error (%)
0.4
0.5
0.6
0.7
GainDrift (ppm/_C)
90 Units from 3 Production Lots
0.8
0.9
1.0
1.1
1.2
0
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
8
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NOISE HISTOGRAM
NOISE HISTOGRAM
NOISE HISTOGRAM
NOISE HISTOGRAM
NOISE HISTOGRAM
NOISE HISTOGRAM
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, AVDD = 5V, DVDD = 1.8V, f
= 7.68MHz, PGA = 1, and V
CLKIN
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
= 2.5V , unless otherwise noted.
REF
100
PGA = 1
Data Rate = 2.5SPS
80
60
40
Percent of Population
20
0
−5−4−3−2−
25
PGA = 1
Data Rate = 1kSPS
20
15
10
Buffer= Off
256 Readings
10 1 2 3 4 5
Output Code (LSB)
Buffer = Off
4096 Readings
25
PGA = 64
Data Rate = 2.5SPS
20
15
10
Percent of Population
5
0
−20−18−16−14−12−
25
PGA = 64
Data Rate = 1kSPS
20
15
10
10
2
−8−6−4−
Output Code(LSB)
02468
Buffer = Off
256 Readings
1012141618
Buffer = Off
4096Readings
20
Percent of Population
5
0
−20−18−16−14−12−
25
PGA = 1
DataRate= 30kSPS
20
15
10
Percent of Population
5
0
100
−90−80−70−60−50−40−30−20−
−
10
2
−8−6−4−
Output Code(LSB)
10
Output Code(LSB)
02468
0
102030405060708090
1012141618
Buffer = Off
4096 Readings
20
100
Percent of Population
5
0
150−135−120−105
−
25
PGA = 64
Data Rate = 30kSPS
20
15
10
Percent of Population
5
0
600−540−480−420−360−300−240−180−120
−
−90−75−60−45−30−
Output Code(LSB)
Output Code(LSB)
15
60
−
0
0
1530456075
4096 Readings
60
120
180
240
90
105
Buffer = Off
300
360
420
120
480
135
540
150
600
9
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBEROF BITS
INTEGRAL NONLINEARITY vs INPUT SIGNAL
INL (% of FSR)
INTEGRAL NONLINEARITY vs PGA
ANALOG SUPPLY CURRENT vs TEMPERATURE
ANALOG SUPPLY CURRENT vs PGA
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, AVDD = 5V, DVDD = 1.8V, f
= 7.68MHz, PGA = 1, and V
CLKIN
= 2.5V , unless otherwise noted.
REF
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0.0006
0.0004
0.0002
−
0.0002
−
0.0004
−
0.0006
23
PGA = 1
22
21
20
ENOB(rms)
19
18
0
PGA = 1
−4−
−
5
vs INPUT VOLTAGE
Input Voltage, V
−2−
3
Input Voltage, VIN(V)
Data Rate = 1kSPS
Data Rate = 30kSPS
2.50 0.5 1.0 1.5 2.0 3.0 3.5 4.0 4.5 5.0
(V)
IN
−40_
C
+125_C
+25_C+85_C
1345210
0.0009
0.0008
0.0007
0.0006
0.0005
(% of FSR)
0.0004
INL
0.0003
0.0002
0.0001
23
PGA = 1
22
21
20
ENOB (rms)
19
18
−
−
30
50
0
2148 643216
vs TEMPERATURE
Data Rate = 1kSPS
Data Rate = 30kSPS
−
10 10 30 90 1107050
Temperature(_C)
PGA Setting
Buffer Off
Buffer On
50
45
40
35
30
25
20
15
Analog Current (mA)
10
5
0
−
−
50
−
30
10 10 30 90 1107050
Temperature(_C)
PGA = 64, Buffer On
PGA = 64, Buffer Off
PGA = 1, Buffer On
PGA = 1, Buffer Off
40
35
30
25
20
15
Analog Current (mA)
10
5
0
2148 643216
PGA Setting
Buffer On
Buffer Off
10
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
OVERVIEW
The ADS1255 and ADS1256 are very low-noise A/D
converters. The ADS1255 supports one differential or two
single-ended inputs and has two general-purpose digital
I/Os. The ADS1256 supports four differential or eight
single-ended inputs and has four general-purpose digital
I/Os. Otherwise, the two units are identical and are
referred to together in this data sheet as the ADS1255/6.
Figure 5 shows a block diagram of the ADS1256. The
input multiplexer selects which input pins are connected to
the A/D converter. Selectable current sources within the
input multiplexer can check for open- or short-circuit
conditions on the external sensor. A selectable onboard
input buffer greatly reduces the input circuitry loading by
providing up to 80MΩ of impedance. A low-noise PGA
provides a gain of 1, 2, 4, 8, 16, 32, or 64. The ADS1255/6
converter is comprised of a 4th-order, delta-sigma
modulator followed by a programmable digital filter.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
ADS1256 Only
AIN7
AINCOM
Input
Multiplexer
and
Sensor
Detect
AIN
AIN
P
Buffer
N
PGA
1:64
Σ
The modulator measures the amplified differential input
signal, V
reference, V
= (AINP – AINN), against the differential
IN
= (VREFP − VREFN). The differential
REF
reference is scaled internally by a factor of two so that the
full-scale input range is ±2V
(for PGA = 1).
REF
The digital filter receives the modulator signal and
provides a low-noise digital output. The data rate of the
filter is programmable from 2.5SPS to 30kSPS and allows
tradeoffs between resolution and speed.
Communication is done over an SPI-compatible serial
interface with a set of simple commands providing control of
the ADS1255/6. Onboard registers store t he v arious settings
for the input m ultiplexer , s ensor detect current sources, input
buffer enable, PGA setting, data rate, etc. Either an external
crystal or clock oscillator can be used to provide the clock
source. General-purpose digital I /Os p rovide static r ead/write
control of up to four pins. One of the pins can also be used
to supply a programmable clock output.
VREFP VREFN
Σ
V
REF
2
2V
REF
•
V
PGA
IN
4th−Order
Modulator
General
Purpose
Digital I/O
A/D
Converter
Programmable
Digital Filter
Clock
Generator
Control
SPI
Serial
Interface
XTAL1/CLKIN
XTAL2
RESET
SYNC/PDWN
DRDY
SCLK
DIN
DOUT
CS
D3 D2 D1 D0/CLKOUT
ADS1256
Only
Figure 5. Block Diagram
11
RATE
RATE
RATE
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
www.ti.com
NOISE PERFORMANCE
The ADS1255/6 offer outstanding noise performance that
can be optimized by adjusting the data rate or PGA setting.
As the averaging is increased by reducing the data rate,
the noise drops correspondingly. The PGA reduces the
input-referred noise when measuring lower level signals.
Table 1 through Table 6 summarize the typical noise
performance with the inputs shorted externally. In all six
tables, the following conditions apply: T = +25°C,
AVDD = 5V, DVDD = 1.8V, V
7.68MHz. Table 1 to Table 3 reflect the device input bu ffer
enabled. Table 1 shows the rms value of the input-referred
noise in volts. Table 2 shows the effective number of bits
of resolution (ENOB), using the noise data from Table 1.
ENOB is defined as:
ENOB +
lnǒFSRńRMS Noise
where FSR is the full-scale range. Table 3 shows the
noise-free bits of resolution. It is calculated with the same
formula as ENOB except the peak-to-peak noise value is
used instead of rms noise. Table 4 through Table 6 show
the same noise data, but with the input buffer disabled.
= 2.5V, and f
REF
)
ln(2
=
CLKIN
Ǔ
Table 2. Effective Number of Bits (ENOB, rms)
with Buffer On
DATA
(SPS)
2.5 25.3 24.9 24.9 24.4 23.8 23.0 22.2
5 25.0 24.8 24.5 24.0 23.3 22.7 21.8
10 24.8 24.5 24.1 23.5 22.9 22.3 21.3
15 24.6 24.2 23.8 23.2 22.5 21.8 21.0
25 24.3 24.0 23.4 23.0 22.2 21.5 20.7
30 24.2 23.8 23.3 22.8 22.1 21.5 20.5
50 23.9 23.6 23.0 22.5 21.8 21.1 20.3
60 23.8 23.4 22.9 22.4 21.7 21.0 20.2
100 23.4 23.0 22.5 22.0 21.4 20.8 19.8
500 22.3 21.9 21.5 20.9 20.3 19.6 18.7
1000 21.7 21.3 20.8 20.2 19.8 19.2 18.3
2000 21.2 20.9 20.4 19.7 19.3 18.8 17.9
3750 20.8 20.5 20.0 19.4 19.0 18.4 17.4
7500 20.4 20.1 19.6 19.0 18.5 17.9 17.0
15,000 20.1 19.7 19.3 18.7 18.2 17.7 16.7
30,000 19.8 19.5 19.1 18.5 18.0 17.4 16.5
1 2 4 8 16 32 64
PGA
Table 3. Noise-Free Resolution (bits)
with Buffer On
Table 1. Input Referred Noise (µV, rms)
with Buffer On
DATA
(SPS)
2.5 0.247 0.156 0.080 0.056 0.043 0.037 0.033
5 0.301 0.175 0.102 0.076 0.061 0.045 0.044
10 0.339 0.214 0.138 0.106 0.082 0.061 0.061
15 0.401 0.264 0.169 0.126 0.107 0.085 0.073
25 0.494 0.305 0.224 0.149 0.134 0.102 0.093
30 0.533 0.335 0.245 0.176 0.138 0.104 0.106
50 0.629 0.393 0.292 0.216 0.168 0.136 0.122
60 0.692 0.438 0.321 0.233 0.184 0.146 0.131
100 0.875 0.589 0.409 0.305 0.229 0.170 0.169
500 1.946 1.250 0.630 0.648 0.497 0.390 0.367
1000 2.931 1.891 1.325 1.070 0.689 0.512 0.486
2000 4.173 2.589 1.827 1.492 0.943 0.692 0.654
3750 5.394 3.460 2.376 1.865 1.224 0.912 0.906
7500 7.249 4.593 3.149 2.436 1.691 1.234 1.187
15,000 9.074 5.921 3.961 2.984 2.125 1.517 1.515
30,000 10.728 6.705 4.446 3.280 2.416 1.785 1.742
1 2 4 8 16 32 64
PGA
DATA
(SPS)
2.5 23.0 22.6 22.1 21.7 21.3 20.8 19.7
5 22.3 22.4 21.9 21.3 20.7 20.3 19.3
10 22.3 22.0 21.6 21.0 20.4 19.9 18.9
15 22.0 21.7 21.3 20.7 20.1 19.3 18.7
25 21.7 21.4 21.1 20.5 19.7 19.2 18.5
30 21.8 21.3 20.8 20.4 19.8 19.0 18.1
50 21.3 21.1 20.4 19.9 19.4 18.8 17.9
60 21.3 20.9 20.5 19.8 19.3 18.8 17.8
100 20.9 20.7 20.2 19.6 19.1 18.5 17.4
500 20.1 19.6 19.1 18.6 18.0 17.3 16.3
1000 19.0 18.6 18.1 17.5 17.2 16.5 15.6
2000 18.5 18.1 17.8 17.0 16.6 16.1 15.3
3750 18.1 17.8 17.3 16.6 16.2 15.7 14.7
7500 17.7 17.3 16.9 16.2 15.8 15.3 14.4
15,000 17.3 17.0 16.5 15.9 15.5 14.9 13.9
30,000 17.1 16.7 16.4 15.9 15.4 14.6 13.8
1 2 4 8 16 32 64
PGA
12
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