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SBAS184A – MARCH 2001 – REVISED SEPTEMBER 2003
24-Bit, 20kHz, Low-Power
ANALOG-TO-DIGITAL CONVERTER
ADS1251
FEATURES
● 24 BITS—NO MISSING CODES
● 19 BITS EFFECTIVE RESOLUTION UP TO
20kHz DATA RATE
● LOW NOISE: 1.5ppm
● DIFFERENTIAL INPUTS
● INL: 15ppm (max)
● EXTERNAL REFERENCE (0.5V to 5V)
● POWER-DOWN MODE
● SYNC MODE
● LOW POWER: 8mW at 20kHz
5mW at 10kHz
APPLICATIONS
● CARDIAC DIAGNOSTICS
● DIRECT THERMOCOUPLE INTERFACES
● BLOOD ANALYSIS
● INFRARED PYROMETERS
● LIQUID/GAS CHROMATOGRAPHY
● PRECISION PROCESS CONTROL
DESCRIPTION
The ADS1251 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply. The delta-sigma
architecture features wide dynamic range, and 24 bits of no
missing code performance. Effective resolution of 19 bits
(1.5ppm of rms noise) is achieved at conversion rates up to
20kHz.
The ADS1251 is designed for high-resolution measurement
applications in cardiac diagnostics, smart transmitters, industrial process control, weigh scales, chromatography, and
portable instrumentation. The converter includes a flexible,
2-wire synchronous serial interface for low-cost isolation.
The ADS1251 is a single-channel converter and is offered in
an SO-8 package. It is pin-compatible with the faster ADS1252
(41.7kHz data rate).
ADS1251
+V
IN
–V
IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
4th-Order
∆Σ
Modulator
Digital
Filter
www.ti.com
Serial
Interface
Control
V
REF
CLK
SCLK
DOUT/DRDY
+V
DD
GND
Copyright © 2001-2003, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
Analog Input: Current ............................................... ±100mA, Momentary
V
to GND ............................................................................ –0.3V to 6V
DD
V
REF
Digital Input Voltage to GND ................................... –0.3V to V
Digital Output Voltage to GND .................................–0.3V to V
Operating Temperature ...................................................... –40°C to 85°C
Lead Temperature (soldering, 10s).............................................. +300°C
Power Dissipation .......................................................................... 500mW
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
Voltage .................................... GND – 0.3V to V
Voltage to GND ............................................... –0.3V to VDD + 0.3V
(1)
±10mA, Continuous
+ 0.3V
DD
+ 0.3V
DD
+ 0.3V
DD
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
ADS1251 SO-8 D –40°C to +85°C ADS1251U ADS1251U Rails, 100
(1)
SPECIFIED
RANGE MARKING NUMBER MEDIA, QUANTITY
" """"ADS1251U/2K5 Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PRODUCT FAMILY
PRODUCT # OF INPUTS MAXIMUM DATA RATE COMMENTS
ADS1250 1 Differential 25.0kHz Includes PGA from 1 to 8
ADS1251 1 Differential 26.8kHz
ADS1252 1 Differential 41.7kHz
ADS1253 4 Differential 20.8kHz
ADS1254 4 Differential 20.8kHz Includes Separate Analog and Digital Supplies
ELECTRICAL CHARACTERISTICS
All specifications at T
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Voltage +V
Absolute Input Voltage +V
Differential Input Impedance CLK = 3.84kHz 430 MΩ
Input Capacitance 6pF
Input Leakage At +25°C550pA
DYNAMIC CHARACTERISTICS
Data Rate 20.8 kHz
Bandwidth –3dB, CLK = 8MHz 4.24 kHz
Serial Clock (SCLK) 8MHz
System Clock Input (CLK) 8MHz
ACCURACY
Integral Nonlinearity Differential Input ±0.0002 ±0.0015 % of FSR
THD 1kHz Input; 0.1dB below FS 105 dB
Noise 1.5 2.5 ppm of FSR, rms
Resolution 24 Bits
No Missing Codes 24 Bits
Common-Mode Rejection 60Hz, AC 90 98 dB
Gain Error 0.1 1 % of FSR
Offset Error ±30 ±100 ppm of FSR
Gain Sensitivity to V
Power-Supply Rejection Ratio 70 80 dB
PERFORMANCE OVER TEMPERATURE
Offset Drift 0.07 ppm/°C
Gain Drift 0.4 ppm/°C
MIN
REF
to T
, VDD = +5V, CLK = 8MHz, and V
MAX
= 4.096, unless otherwise specified.
REF
ADS1251U
– (–VIN) ±V
IN
or –VIN to GND –0.3 V
IN
CLK = 1MHz 1.7 MΩ
CLK = 8MHz 210 kΩ
to T
At T
MIN
MAX
REF
DD
1nA
1:1
V
V
2
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ADS1251
SBAS184A
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at T
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE
V
REF
Load Current 32 µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Level: V
Input (SCLK, CLK) Hysteresis 0.6 V
Data Format
POWER-SUPPLY REQUIREMENTS
Operation +4.75 +5 +5.25 VDC
Quiescent Current V
Operating Power 7.5 10 mW
Power-Down Current 0.4 1 µA
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
to T
MIN
, VDD = +5V, CLK = 8MHz, and V
MAX
= 4.096, unless otherwise specified.
REF
ADS1251U
0.5 4.096 V
IH
V
IL
V
OH
V
OL
IOH = –500µA +4.5 V
IOL = 500µA 0.4 V
+4.0 +VDD + 0.3 V
–0.3 +0.8 V
DD
Offset Binary Two’s Complement
= +5VDC 1.5 2 mA
DD
V
PIN CONFIGURATION
Top View SO
+V
–V
+V
CLK
1
IN
2
IN
ADS1251U
3
DD
4
V
8
REF
7
GND
SCLK
6
5
DOUT/DRDY
PIN DESCRIPTIONS
PIN NAME PIN DESCRIPTION
1+V
2–V
3+V
IN
IN
DD
4 CLK Digital Input: Device System Clock. The
5
DOUT/DRDY
6 SCLK Digital Input: Serial Clock. The serial clock
7 GND Input: Ground
8V
REF
Analog Input: Positive Input of the Differential Analog Input
Analog Input: Negative Input of the Differential Analog Input.
Input: Power-Supply Voltage, +5V
system clock is in the form of a CMOScompatible clock. This is a Schmitt-Trigger
input.
Digital Output: Serial Data Output/Data
Ready. This output indicates that a new
output word is available from the ADS1251
data output register. The serial data is
clocked out of the serial data output shift
register using SCLK.
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is possible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either initiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
Analog Input: Reference Voltage Input
ADS1251
SBAS184A
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3
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, CLK = 8MHz, and V
= 4.096, unless otherwise specified.
REF
2.0
1.6
1.2
0.8
RMS Noise (ppm of FS)
0.4
0
2.0
1.8
1.6
10010 10k1k 100k
RMS NOISE vs TEMPERATURE
RMS NOISE vs DATA RATE
Data Rate (Hz)
EFFECTIVE RESOLUTION vs DATA OUTPUT RATE
20.0
19.5
19.0
18.5
Effective Resolution (Bits)
18.0
19.5
19.0
EFFECTIVE RESOLUTION vs TEMPERATURE
1k100 10k 100k
Data Output Rate (Hz)
1.4
RMS Noise (ppm of FS)
1.2
1.0
–40 –20 0 20 40 60 80 100
Temperature (°C)
18
16
14
12
10
8
6
RMS Noise (µV)
4
2
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RMS NOISE vs V
V
REF
VOLTAGE
REF
Voltage (V)
18.5
Effective Resolution (Bits)
18.0
–40 –20 0 20 40 60 80 100
Temperature (°C)
14
12
10
8
6
4
RMS Noise (ppm of FS)
2
0
012345
RMS NOISE vs V
V
REF
VOLTAGE
REF
Voltage (V)
4
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ADS1251
SBAS184A
TYPICAL CHARACTERISTICS (Cont.)
40
35
30
25
20
15
10
5
0
OFFSET vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Offset (ppm of FS)
–60
–65
–70
–75
–80
–85
–90
–95
–100
POWER-SUPPLY REJECTION RATIO
vs CLK FREQUENCY
Clock Frequency (MHz)
12345678
PSRR (dB)
At TA = +25°C, VDD = +5V, CLK = 8MHz, and V
= 4.096, unless otherwise specified.
REF
2.0
1.5
1.0
0.5
RMS Noise (ppm of FS)
0
–5 –4 –3 –2 –10 1 23 4 5
INTEGRAL NONLINEARITY vs DATA OUTPUT RATE
5
4
3
RMS NOISE vs INPUT VOLTAGE
Input Voltage (V)
4.0
3.5
3.0
2.5
2.0
1.5
INL (ppm of FS)
1.0
0.5
INTEGRAL NONLINEARITY vs TEMPERATURE
0
–40 –20 0 20 40 60 80 100
Temperature (°C)
2
INL (ppm of FS)
1
0
100 1k 10k 100k
Data Output Rate (Hz)
650
625
600
575
550
Gain Error (ppm of FS)
525
500
–40 –20 0 20 40 60 80 100
ADS1251
SBAS184A
GAIN ERROR vs TEMPERATURE
Temperature (°C)
www.ti.com
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 8MHz, and V
= 4.096, unless otherwise specified.
REF
COMMON-MODE REJECTION RATIO
–60
–65
–70
–75
–80
–85
–90
CMRR at 60Hz (dB)
–95
–100
–105
12345678
1.65
1.60
1.55
1.50
Current (mA)
1.45
1.40
–40 –20 0 20 40 60 80 100
vs CLK FREQUENCY
Clock Frequency (MHz)
CURRENT vs TEMPERATURE
Temperature (°C)
COMMON-MODE REJECTION RATIO
–60
–65
–70
–75
–80
–85
CMRR (dB)
–90
–95
–100
–105
10 100 1k 10k 100k
9
8
7
6
5
4
3
2
Power Dissipation (mW)
1
0
012345 768
vs COMMON-MODE FREQUENCY
Common-Mode Signal Frequency (Hz)
POWER DISSIPATION vs CLK FREQUENCY
Clock Frequency (MHz)
V
CURRENT vs CLK FREQUENCY
35
30
25
20
15
Current (µA)
REF
V
10
5
0
0.1 1 10
6
REF
Clock Frequency (MHz)
www.ti.com
0
–20
–40
–60
–80
–100
–120
Relative Magnitude (dB)
–140
–160
01234567891011
(1kHz input at 0.1dB less than full-scale)
TYPICAL FFT
Frequency (kHz)
ADS1251
SBAS184A
THEORY OF OPERATION
The ADS1251 is a precision, high-dynamic range, 24-bit,
delta-sigma, A/D converter capable of achieving very
high-resolution digital results at high data rates. The analog
input signal is sampled at a rate determined by the frequency
of the system clock (CLK). The sampled analog input is
modulated by the delta-sigma A/D modulator, which is followed by a digital filter. A sinc
the output of the delta-sigma modulator and writes the result
into the data-output register. The DOUT/DRDY
LOW, indicating that new data is available to be read by the
external microcontroller/microprocessor. As shown in the block
diagram on the front page, the main functional blocks of the
ADS1251 are the 4th-order delta-sigma modulator, a digital
filter, control logic, and a serial interface. Each of these
functional blocks is described in the following sections.
ANALOG INPUT
The ADS1251 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 98dB, and excellent power-supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V, when the reference input voltage equals +4.096V.
The bipolar range is with respect to –V
to GND.
The differential input impedance of the analog input changes
with the ADS1251 system clock frequency (CLK). The relationship is:
Impedance (Ω) = (8MHz/CLK) • 210,000
See application note
and ADS1254 Input Circuitry
load from TI’s web site www.ti.com.
With regard to the analog-input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy. If the source
impedance of the input signal is significant, or if there is
passive filtering prior to the ADS1251, a significant portion of
the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out of
the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth of
the analog-input signal must be band-limited; the bandwidth
is a function of the system clock frequency. With a system
Understanding the ADS1251, ADS1253,
5
digital low-pass filter processes
pin is pulled
, and not with respect
IN
(SBAA086), available for down-
clock frequency of 8MHz, the data-output rate is 20.8kHz
with a –3dB frequency of 4.24kHz. The –3dB frequency
scales with the system clock frequency.
To ensure the best linearity of the ADS1251, and to maximize the elimination of even-harmonic noise errors, a fully
differential signal is recommended.
For more information about the ADS1251 input structure,
please refer to application note SBAA086 found at www.ti.com.
BIPOLAR INPUT
Each of the differential inputs of the ADS1251 must stay
between –0.3V and V
than half of V
, one input can be tied to the reference
DD
voltage, and the other input can range from 0V to
2 • V
. By using a three op amp circuit featuring a single
REF
amplifier and four external resistors, the ADS1251 can be
configured to accept bipolar inputs referenced to ground. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS1251 using the resistor values shown in
Figure 1.
10kΩ
Bipolar
Input
OPA4350
BIPOLAR INPUT R
20kΩ
±10V 2.5kΩ 5kΩ
±5V 5kΩ 10kΩ
±2.5V 10kΩ 20kΩ
FIGURE 1. Level-Shift Circuit for Bipolar Input Ranges.
. With a reference voltage at less
DD
R
1
2
REF
2.5V
+IN
–IN
OPA4350
ADS1251
V
REF
OPA4350
R
2
1
R
ADS1251
SBAS184A
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7
DELTA-SIGMA MODULATOR
The ADS1251 operates from a nominal system clock frequency of 8MHz. The modulator frequency is fixed in relation
to the system clock frequency. The system clock frequency
is divided by 6 to derive the modulator frequency (f
Therefore, with a system clock frequency of 8MHz, the
modulator frequency is 1.333MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modulator is 64, and with the modulator frequency running at
1.333MHz, the data rate is 20.8kHz. Using a slower system
clock frequency will result in a lower data output rate, as
shown in Table I.
MOD
REFERENCE INPUT
The reference input takes an average current of 32µA with a
8MHz system clock. This current will be proportional to the
system clock. A buffered reference is recommended for the
ADS1251. The recommended reference circuit is shown in
).
Figure 2.
Reference voltages higher than 4.096V will increase the full-
scale range, while the absolute internal circuit noise of the
converter remains the same. This will decrease the noise in
terms of ppm of full-scale, which increases the effective
resolution (see typical characteristic “RMS Noise vs V
Voltage”).
REF
CLK (MHz) DATA OUTPUT RATE (Hz)
(1)
8
(1)
7.372800
(1)
6.144000
(1)
6.000000
(1)
4.915200
(1)
3.686400
(1)
3.072000
(1)
2.457600
(1)
1.843200
0.921600 2400
0.460800 1200
0.384000 1000
0.192000 500
0.038400 100
0.023040 60
0.019200 50
0.011520 30
0.009600 25
0.007680 20
0.006400 16.67
0.005760 15
0.004800 12.50
0.003840 10
NOTE: (1) Standard Clock Oscillator.
20,833
19,200
16,000
15,625
12,800
9600
8000
6400
4800
TABLE I. CLK Rate versus Data Output Rate.
DIGITAL FILTER
The digital filter of the ADS1251, referred to as a Sinc5 filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as averaging the modulator
results in a weighted form and presenting this average as the
digital output. The digital output rate, or data rate, scales
directly with the system clock frequency. This allows the data
output rate to be changed over a very wide range (five orders
of magnitude) by changing the system clock frequency.
However, it is important to note that the –3dB point of the
filter is 0.2035 times the data output rate, so the data output
rate should allow for sufficient margin to prevent attenuation
of the signal of interest.
As the conversion result is essentially an average, the
data-output rate determines the location of the resulting
notches in the digital filter (see Figure 3). Note that the first
notch is located at the data output rate frequency, and
subsequent notches are located at integer multiples of the
data output rate; this allows for rejection of not only the
fundamental frequency, but also harmonic frequencies. In
this manner, the data output rate can be used to set specific
notch frequencies in the digital filter response.
For example, if the rejection of power-line frequencies is
desired, then the data output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system clock
+5V
+5V
1
REF3040
3
0.1µF
0.1µF
10kΩ
+
10µF
0.10µF
2
2
3
0.10µF
7
OPA350
4
0.1µF
To V
REF
Pin 8 of
the ADS1251
6
+
10µF
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1251.
8
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ADS1251
SBAS184A
frequency must be 19.200kHz, and this sets the data output
DOUT/DRDY
DOUT/DRDY
rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the
system CLK frequency must be 23.040kHz, and this sets the
data-output rate to 60Hz (see Table I and Figure 5). If both
50Hz and 60Hz rejection is required, then the system CLK
must be 3.840kHz; this sets the data output rate to 10Hz and
rejects both 50Hz and 60Hz (see Table I and Figure 6).
There is an additional benefit in using a lower data output
rate. It provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data output rate,
a significant signal at 75Hz may alias back into the passband
at 25Hz. This is due to the fact that rejection at 75Hz may
only be 66dB in the stopband—frequencies higher than the
first notch frequency (see Figure 4). However, setting the
data output rate to 10Hz provides 135dB rejection at 75Hz
(see Figure 6). A similar benefit is gained at frequencies near
the data output rate (see Figures 7, 8, 9, and 10). For
example, with a 50Hz data output rate, rejection at 55Hz may
only be 105dB (see Figure 7). With a 10Hz data output rate,
however, rejection at 55Hz will be 122dB (see Figure 8). If a
slower data output rate does not meet the system requirements, then the analog front-end can be designed to provide
the needed attenuation to prevent aliasing. Additionally, the
data output rate may be increased and additional digital
filtering may be done in the processor or controller.
Application note
Response of the ADS1250-54
load from TI’s web site www.ti.com provides a simple tool for
calculating the ADS1250’s frequency response for any CLK
frequency.
The digital filter is described by the following transfer function:
A Spreadsheet to Calculate the Frequency
(SBAA103) available for down-
f
f
64
–
•
MOD
–
z
5
f
5
1
)
Hf
()
Hz
()
=
=
sin
64
64 1
ππ64
•sin
or
–
1
•–
(
••
f
MOD
z
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64; therefore, it
requires 5 • 64, or 320 modulator results (or clocks) to fully
settle. As the modulator clock is derived from the system
CLK (modulator clock = CLK ÷ 6), the number of system
clocks required for the digital filter to fully settle is
5 • 64 • 6, or 1920 CLKs. This means that any significant step
change at the analog input requires five full conversions to
settle. However, if the step change at the analog input occurs
asynchronously to the DOUT/DRDY
are required to ensure full settling.
pulse, six conversions
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1251.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V; however, they should
never exceed +V
Once the ADS1251 powers up, the DOUT/DRDY
pulse LOW on the first conversion for which the data is valid
from the analog input signal.
The
modes of operation. The first mode of operation is the Data
Ready mode (
loaded into the data output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). See Figure 11 for the time domain partitioning of the
See Figure 12 for the basic timing of DOUT/DRDY
the time defined by t
functions in
DRDY
.
DD
output signal alternates between two
DRDY
) to indicate that new data has been
and DOUT function.
, t3, and t4, the DOUT/DRDY pin
DRDY
2
mode. The state of the DOUT/DRDY pin
line will
. During
ADS1251
SBAS184A
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9
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
NORMALIZED DIGITAL FILTER RESPONSE
123456789100
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
DIGITAL FILTER RESPONSE
50 100 150 200 250 3000
Frequency (Hz)
FIGURE 3. Normalized Digital Filter Response. FIGURE 4. Digital Filter Response (50Hz).
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
DIGITAL FILTER RESPONSE
50 100 150 200 250 3000
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
10 20 30 40 50 60 70 80 90 1000
DIGITAL FILTER RESPONSE
Frequency (Hz)
FIGURE 5. Digital Filter Response (60Hz). FIGURE 6. Digital Filter Response (10Hz Multiples).
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
DIGITAL FILTER RESPONSE
46 47 48 49 50 51 52 53 54 5545
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
46 47 48 49 50 51 52 53 54 5545
DIGITAL FILTER RESPONSE
Frequency (Hz)
FIGURE 7. Expanded Digital Filter Response (50Hz with a
50Hz data output rate).
10
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FIGURE 8. Expanded Digital Filter Response (50Hz with a
10Hz data output rate).
ADS1251
SBAS184A
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
DIGITAL FILTER RESPONSE
56 57 58 59 60 61 62 63 64 6555
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
Gain (dB)
–140
–160
–180
–200
56 57 58 59 60 61 62 63 64 6555
DIGITAL FILTER RESPONSE
Frequency (Hz)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz data output rate).
is HIGH prior to the internal transfer of new data to the DOR.
The result of the A/D conversion is written to the DOR from
the Most Significant Bit (MSB) to the Least Significant Bit
(LSB) in the time defined by t
DOUT/DRDY
t
, and then pulses HIGH for the time defined by t3 to indicate
2
line then pulses LOW for the time defined by
(see Figures 11 and 12). The
1
that new data is available to be read. At this point, the
function of the DOUT/DRDY
Data is shifted out on the pin after t
pin changes to DOUT mode.
. The device communi-
7
cating with the ADS1251 can provide SCLKs to the ADS1251
after the time defined by t
. The normal mode of reading data
6
from the ADS1251 is for the device reading the ADS1251 to
latch the data on the rising edge of SCLK (because data is
shifted out of the ADS1251 on the falling edge of SCLK). In
order to retrieve valid data, the entire DOR must be read
before the DOUT/DRDY
pin reverts back to
DRDY
mode.
If SCLKs are not provided to the ADS1251 during the DOUT
mode, the MSB of the DOR is present on the DOUT/DRDY
line until the time defined by t4. If an incomplete read of the
ADS1251 takes place while in DOUT mode (that is, less than
24 SCLKs were provided), the state of the last bit read is
present on the DOUT/DRDY
line until the time defined by t4.
If more than 24 SCLKs are provided during DOUT mode, the
DOUT/DRDY
line stays LOW until the time defined by t4.
FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz data output rate).
The internal data pointer for shifting data out on DOUT/DRDY
is reset on the falling edge of the time defined by t1 and t4.
This ensures that the first bit of data shifted out of the
ADS1251 after
DRDY
mode is always the MSB of new data.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding SCLK
HIGH, multiple ADS1251s can be synchronized. This is accomplished by holding SCLK HIGH for at least four, but less than 20,
consecutive
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive
pulses LOW for one CLK cycle and then is held HIGH, and the
modulator is held in a reset state. The modulator will be
released from reset and synchronization occurs on the falling
edge of SCLK. With multiple converters, the falling edge transition of SCLK must occur simultaneously on all devices. It is
important to note that prior to synchronization, the
pulse of multiple ADS1251s in the system could have a difference in timing up to one
synchronization, the SCLK must be held HIGH for at least five
DRDY
edge of SCLK occurs at t
indicates valid data.
DOUT/DRDY
DOUT/DRDY
cycles. The first
cycles (see Figure 13). After the
cycles, the
DOUT/DRDY
DOUT/DRDY
DRDY
period. Therefore, to ensure
DOUT/DRDY
. The first
14
pulse after the falling
DOUT/DRDY
pulse
pin
ADS1251
SBAS184A
www.ti.com
11
POWER-DOWN MODE
DOUT/DRDY
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1251 will enter power-down mode. This
is accomplished by holding SCLK HIGH for at least 20
consecutive DOUT/DRDY
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive DOUT/DRDY
pulses LOW for one CLK cycle and then is held HIGH, and
the modulator is held in a reset state. If SCLK is held HIGH
for an additional 16 DOUT/DRDY
enters power-down mode. The part will be released from
power-down mode on the falling edge of SCLK. It is important to note that the DOUT/DRDY
DOUT/DRDY
cycles, but power-down mode is not entered
for an additional 16 DOUT/DRDY
DOUT/DRDY
t
and indicates valid data. Subsequent DOUT/DRDY pulses
16
pulse after the falling edge of SCLK occurs at
will occur normally.
periods (see Figure 14). After the
cycles, the DOUT/DRDY pin
periods, the ADS1251
pin is held HIGH after four
periods. The first
SERIAL INTERFACE
The ADS1251 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1251 can
commence on the first detection of the DOUT/DRDY
after power up.
It is important to note that the data from the ADS1251 is a
24-bit result transmitted MSB-first in Offset Binary Two’s
Complement format, as shown in Table III.
The data must be clocked out before the ADS1251 enters
DRDY
mode to ensure reception of valid data, as described
in the
DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX)
+Full-Scale 7FFFFF
–Full-Scale 800000
TABLE III. ADS1251 Data Format (Offset Binary Two’s
section of this data sheet.
Zero 000000
Complement).
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
DRDY
DRDY
Mode
DOUT Mode DOUT Mode 348 • CLK ns
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
Conversion Cycle 384 • CLK ns
DRDY
Mode 36 • CLK ns
DOR Write Time 6 • CLK ns
DOUT/DRDY
DOUT/DRDY
DOUT/DRDY
Rising Edge of CLK to Falling Edge of
End of
End of
Falling Edge of SCLK to Data Valid (Hold Time) 5 ns
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) 30 ns
SCLK Setup Time for Synchronization or Power Down 30 ns
DOUT/DRDY
Rising Edge of SCLK Until Start of Synchronization 1537 • CLK 7679 • CLK ns
Synchronization Time 0.5 • CLK 6143.5 • CLK ns
Falling Edge of CLK (After SCLK Goes LOW) Until Start of
Rising Edge of SCLK Until Start of Power Down 7681 • CLK ns
Falling Edge of CLK (After SCLK Goes LOW) Until Start of
Falling Edge of Last
LOW Time 6 • CLK ns
HIGH Time (Prior to Data Out) 6 • CLK ns
HIGH Time (Prior to Data Ready) 24 • CLK ns
DRDY
Mode to Rising Edge of First SCLK 30 ns
DRDY
Mode to Data Valid (Propagation Delay) 30 ns
Pulse for Synchronization or Power Down 1 • CLK ns
DOUT/DRDY
DOUT/DRDY
Mode 2042.5 • CLK ns
DRDY
Mode 2318.5 • CLK ns
to Start of Power Down 6144.5 • CLK ns
DRDY
30 ns
TABLE II. Digital Timing.
pulse
H
H
H
FIGURE 11. DOUT/DRDY Partitioning.
12
DOUT/DRDY
DATA
DRDY Mode
t
4
t
1
t2t
3
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DOUT ModeDOUT Mode
DATA DATA
DRDY Mode
ADS1251
SBAS184A
DOUT/DRDY
CLK
DOUT/DRDY
SCLK
t
5
t
1
t
2
t
3
t
4
t
7
t
6
t
8
t
9
DRDY Mode
DOUT Mode
t
DRDY
MSB LSB
CLK
DOUT/DRDY
SCLK
t
3
t
4
t
12
t
2
t
11
t
13
t
14
t
DRDY
t
10
t
DRDY
4 t
DRDY
DATA
DATA
DATA
Synchronization Mode Starts Here
Synchronization Begins Here
DOUT
Mode
t
3
t
4
t
2
DOUT
Mode
CLK
DOUT/DRDY
SCLK
t
3
t
4
t
15
t
2
t
11
t
17
t
16
t
DRDY
t
10
t
DRDY
4 t
DRDY
DATA
DATA
DATA
Power-Down Occurs Here
DOUT
Mode
t
3
t
4
t
2
DOUT
Mode
t
11
Timing.
FIGURE 12.
FIGURE 13. Synchronization Mode.
FIGURE 14. Power-Down Mode.
ADS1251
SBAS184A
www.ti.com
13
ISOLATION
The serial interface of the ADS1251 provides for simple
isolation methods. The CLK signal can be local to the
ADS1251, which then only requires two signals (SCLK, and
DOUT/DRDY
) to be used for isolated data acquisition.
LAYOUT
POWER SUPPLY
The power supply must be well-regulated and low-noise. For
designs requiring very high resolution from the ADS1251,
power supply rejection will be a concern. Avoid running
digital lines under the device as they may couple noise onto
the die. High-frequency noise can capacitively couple into
the analog portion of the device and will alias back into the
passband of the digital filter, affecting the conversion result.
This clock noise will cause an offset error.
GROUNDING
The analog and digital sections of the system design should
be carefully and cleanly partitioned. Each section should
have its own ground plane with no overlap between them.
GND should be connected to the analog ground plane, as
well as all other analog grounds. Do not join the analog and
digital ground planes on the board, but instead connect the
two with a moderate signal trace. For multiple converters,
connect the two ground planes at one location as central to
all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the
two planes together. The printed circuit board can be designed to provide different analog/digital ground connections
via short jumpers. The initial prototype can be used to
establish which connection works best.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding will
change depending on the requirements and specific design
of the overall system. Achieving 24 bits of noise performance
is a great deal more difficult than achieving 12 bits of noise
performance. In general, a system can be broken up into four
different stages:
• Analog Processing
• Analog Portion of the ADS1251
• Digital Portion of the ADS1251
• Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a microcontroller, and
one clock source, one can achieve high resolution by powering all components from a common power supply. In addition, all components could share a common ground plane.
Thus, there would be no distinctions between analog power
and ground, and digital power and ground. The layout
should still include a power plane, a ground plane, and
careful decoupling. In a more extreme case, the design could
include:
• Multiple ADS1251s
• Extensive Analog Signal Processing
• One or More Microcontrollers, Digital Signal Processors,
or Microprocessors
• Many Different Clock Sources
• Interconnections to Various Other Systems
High resolution will be very difficult to achieve for this design.
The approach would be to break the system into as many
different parts as possible. For example, each ADS1251 may
have its own analog processing front end.
DECOUPLING
Good decoupling practices should be used for the ADS1251
and for all components in the design. All decoupling capacitors, and specifically the 0.1µF ceramic capacitors, should be
placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, should be used to decouple V
to GND.
DD
DEFINITION OF TERMS
An attempt has been made to use consistent terminology in
this data sheet. In that regard, the definition of each term is
provided here:
Analog-Input Differential Voltage—for an analog signal
that is fully differential, the voltage range can be compared to
that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1251 are at 2.048V, the differential
voltage is 0V. If one analog input is at 0V and the other
14
www.ti.com
ADS1251
SBAS184A
analog input is at 4.096V, then the differential voltage magnitude is 4.096V. This is the case regardless of which input
is at 0V and which is at 4.096V. The digital-output result,
however, is quite different. The analog-input differential voltage is given by the following equation:
+V
– (–VIN)
IN
A positive digital output is produced whenever the analoginput differential voltage is positive, whereas a negative
digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced
when the converter is configured with a 4.096V reference,
and the analog-input differential is 4.096V. The negative fullscale output is produced when the differential voltage is –
4.096V. In each case, the actual input voltages must remain
within the –0.3V to +V
range.
DD
Actual Analog-Input Voltage—the voltage at any one analog input relative to GND.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1251 is defined as the input which
produces the positive full-scale digital output minus the input
which produces the negative full-scale digital output. For
example, when the converter is configured with a 4.096V
reference, the differential full-scale range is:
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
LSBWeight
−
=
N
21
2
•
REF
=
N
21–
–
Full ScaleRange V
where N is the number of bits in the digital output.
Conversion Cycle—as used here, a conversion cycle refers
to the time period between DOUT/DRDY pulses.
Effective Resolution (ER)—of the ADS1251, in a particular
configuration, can be expressed in two different units:
bits rms (referenced to output) and µVrms (referenced to
input). Computed directly from the converter’s output data,
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure, which is one standard deviation. The ER
in bits can be computed as follows:
The 2 • V
figure in each calculation represents the full-
REF
scale range of the ADS1251. This means that both units are
absolute expressions of resolution—the performance in different configurations can be directly compared, regardless of
the units.
f
—frequency of the modulator and the frequency the
MOD
input is sampled.
CLKFrequency
f
=
f
—Data output rate.
DATA
MOD
f
==
DATA
f
MOD
64 384
6
CLKFrequency
Noise Reduction—for random noise, the ER can be improved with averaging. The result is the reduction in noise by
the factor √N
, where N is the number of averages, as shown
in Table IV. This can be used to achieve true 24-bit performance at a lower data rate. To achieve 24 bits of resolution,
more than 24 bits must be accumulated. A 36-bit accumulator
is required to achieve an ER of 24 bits. The following uses
V
= 4.096V, with the ADS1251 outputting data at 20kHz, a
REF
4096 point average will take 204.8ms. The benefits of averaging will be degraded if the input signal drifts during that 200ms.
N NOISE ER ER
(Number REDUCTION IN IN
of Averages) FACTOR Vrms BITS rms
1116µV 19.26
2 1.414 11.3µV 19.75
428µV 20.26
8 2.82 5.66µV 20.76
16 4 4µV 21.26
32 5.66 2.83µV 21.76
64 8 2µV 22.26
128 11.3 1.41µV 22.76
256 16 1µV 23.26
512 22.6 0.71µV 23.76
1024 32 0.5µV 24.26
2048 45.25 0.35µV 24.76
4096 64 0.25µV 25.26
TABLE IV. Averaging for Noise Reduction.
ADS1251
SBAS184A
ERinbits rms =
20 log2•
•
V
REF
Vrmsnoise
602.
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15
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