TEXAS INSTRUMENTS ADS1246, ADS1247, ADS1248 Technical data

ADS1246

ADS1247

ADS1248

Input

Mux

3rdOrder

DS

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1246

AVSS

AIN0
AIN1

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

InternalOscillator

Programmable

Digital

Filter

Serial

Interface

and

Control

CLK

Input

Mux

3rdOrder

DS

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC
AIN1/IEXC

AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7

ADS1248 Only

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

V

BIAS

GPIO

CLK

ADS1248 Only

ADS1247
ADS1248

PGA

System
Monitor

Programmable

Digital

Filter

Dual
Current
DACs

VREFMux

ADS1248 Only

V

BIAS

System
Monitor

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.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

24-Bit Analog-to-Digital Converters for Temperature Sensors

1

FEATURES DESCRIPTION

23

• 24 Bits, No Missing Codes

• Data Output Rates Up to 2kSPS

• Single-Cycle Settling for All Data Rates

• Simultaneous 50/60Hz Rejection at 20SPS

• 4 Differential/7 Single-Ended Inputs (ADS1248) single-cycle settling digital filter, and an internal

• 2 Differential/3 Single-Ended Inputs (ADS1247)

• Low-Noise PGA: 48nV at PGA = 128

• Matched Current Source DACs

• Very Low Drift Internal Voltage Reference:

10ppm/ ° C (max)

• Sensor Burnout Detection

• 4/8 General-Purpose I/Os (ADS1247/48)

• Internal Temperature Sensor

• Power Supply and V

Monitoring

REF

• Self and System Calibration

• SPI™-Compatible Serial Interface

• Unipolar (+3.3V to +5V)/Bipolar ( ± 2.5V)

Operation

• Digital Supply: +3.3V or +5V

• Operating Temperature – 40 ° C to +125 ° C

APPLICATIONS

• Temperature Measurement

– RTDs, Thermocouples, and Thermistors

• Pressure Measurement

• Industrial Process Control

The ADS1246, ADS1247, and ADS1248 are
highly-integrated, precision, 24-bit analog-to-digital
converters (ADCs). The ADS1246/7/8 feature an
onboard, low-noise, programmable gain amplifier
(PGA), a precision delta-sigma ADC with a

oscillator. The ADS1247 and ADS1248 also provide a
built-in, very low drift voltage reference with 10mA
output capacity, and two matched programmable
current digital-to-analog converters (DACs). The
ADS1246/7/8 provide a complete front-end solution
for temperature/bridge sensor applications including
thermal couples, thermistors, RTDs, and strain-gauge
applications.

An input multiplexer supports four differential inputs
for the ADS1248, two for the ADS1247, and one for
the ADS1246. In addition, the multiplexer has a
sensor burnout detect, voltage bias for
thermocouples, system monitoring, and
general-purpose digital I/Os (ADS1247 and
ADS1248). The onboard, low-noise PGA provides
selectable gains of 1 to 128. The delta-sigma
modulator and programmable digital filter settle in
only one cycle, for fast channel cycling when using
the input multiplexer, and support data rates up to
2kSPS. For data rates of 20SPS or less, both 50Hz
and 60Hz interference are rejected by the filter.

The ADS1246 is offered in a small TSSOP-16
package, the ADS1247 is available in a TSSOP-20
package, and the ADS1248 in a TSSOP-28 package.
All three devices are specified over the extended
temperature range of – 40 ° C to +105 ° C.

ADS1246
ADS1247
ADS1248

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SPI is a trademark of Motorola, Inc.
3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2008 – 2009, Texas Instruments Incorporated

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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PACKAGE/ORDERING INFORMATION

PRODUCT NUMBER OF INPUTS VOLTAGE REFERENCE SOURCES LEAD

ADS1246 or External NO TSSOP-16

ADS1247 or Internal or External YES TSSOP-20

ADS1248 or Internal or External YES TSSOP-28

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

website at www.ti.com

ABSOLUTE MAXIMUM RATINGS

1 Differential

1 Single-Ended

2 Differential

3 Single-Ended

4 Differential

7 Single-Ended

(1)

(1)

DUAL SENSOR

EXCITATION CURRENT PACKAGE-

Over operating free-air temperature range (unless otherwise noted).

PARAMETER ADS1246, ADS1247, ADS1248 UNIT

AVDD to AVSS – 0.3 to +5.5 V
AVSS to DGND – 2.8 to +0.3 V
DVDD to DGND – 0.3 to +5.5 V

Input current

Analog input voltage to AVSS AVSS – 0.3 to AVDD + 0.3 V
Digital input voltage to DGND – 0.3 to DVDD + 0.3 V
Maximum junction temperature +150 ° C
Operating temperature range – 40 to +125 ° C
Storage temperature range – 60 to +150 ° C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

100, momentary mA

10, continuous mA

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Product Folder Link(s): ADS1246 ADS1247 ADS1248

(V )(Gain)

IN

2

AVSS 0.1V+ +

AVDD 0.1V- -

(V )(Gain)

IN

2

ADS1246
ADS1247
ADS1248

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ELECTRICAL CHARACTERISTICS

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +3.3V, AVSS = DVSS = 0V, and V
otherwise noted.

ANALOG INPUTS

Full-scale input voltage
(V

IN

Common-mode input range V

Differential input current 100 pA
PGA gain settings 1, 2, 4, 8, 16, 32, 64, 128
Burnout current source 0.5, 2, or 10 µ A
Bias voltage (AVDD + AVSS)/2 V
Bias voltage output impedance 400 Ω

SYSTEM PERFORMANCE

Resolution No missing codes 24 Bits
Data rate 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 SPS
Integral nonlinearity (INL) Differential input, best fit, PGA = 1 6 15 ppm
Offset error After calibration – 15 15 µ V
Offset drift see Figure 8 to Figure 11 nV/ ° C
Gain error All PGAs, data rate = 40, 80, or 160SPS – 0.02 ± 0.005 0.02 %
Gain drift PGA = 1 see Figure 12 to Figure 15 ppm/ ° C
ADC conversion time Single-cycle settling
Noise See Table 5 to Table 8
Normal-mode rejection See Table 10

Common-mode rejection

Power-supply rejection AVDD, DVDD at dc 100 135 dB

VOLTAGE REFERENCE INPUT

Voltage reference input
(V

REF

Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V
Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V
Reference input current 30 nA

ON-CHIP VOLTAGE REFERENCE

Output voltage 2.038 2.048 2.058 V
Output current
Load regulation 50 µ V/mA

Drift

Startup time See Table 11 µ s
Quiescent current Additional AVDD current 180 µ A

(1) Do not exceed this loading on the internal voltage reference.
(2) Specified by the combination of design and final production test.

.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

REF

ADS1246, ADS1247, ADS1248

PARAMETER CONDITIONS MIN TYP MAX UNIT

± V

/PGA V

= ADCINP – ADCINN)

(2)

At dc, PGA = 1 80 90 dB
At dc, PGA = 32 90 125 dB

= V

– V

REFP

)

REFN

(1)

TA= +25 ° C to +105 ° C 2 10 ppm/ ° C
TA= – 40 ° C to +105 ° C 6 15 ppm/ ° C

0.5 (AVDD – AVSS) – 1 V

REF

= +2.048V, unless

± 10 mA

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): ADS1246 ADS1247 ADS1248

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +3.3V, AVSS = DVSS = 0V, and V
otherwise noted.

ADS1246, ADS1247, ADS1248

PARAMETER CONDITIONS MIN TYP MAX UNIT

CURRENT SOURCES (IDACS)

Output current 50, 100, 250, 500, 750, 1000, 1500 µ A
Voltage compliance All currents AVDD – 0.7 V
Initial error All currents, each IDAC – 6 ± 1.0 6 % of FS
Initial mismatch All currents, between IDACs ± 0.03 % of FS
Temperature drift Each IDAC 200 ppm/ ° C
Temperature drift matching Between IDACs 10 ppm/ ° C

SYSTEM MONITORS

Temperature
sensor reading

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

Logic levels

DIGITAL INPUT/OUTPUT (other than GPIO)

Logic levels

Input leakage DGND < VIN< DVDD ± 10 µ A
Clock input

(CLK)
Internal oscillator frequency 3.89 4.096 4.3 MHz

POWER SUPPLY

DVDD 3.234 5.25 V
AVSS – 2.5 0 V
AVDD AVSS + 3.234 AVSS + 5.25 V

DVDD current Normal mode, DVDD = 3.3V,

AVDD current Converting, AVDD = 3.3V,

Power dissipation

TEMPERATURE RANGE

Specified – 40 +105 ° C
Operating – 40 +125 ° C
Storage – 60 +150 ° C

Voltage TA= +25 ° C 112 mV
Drift 379 µ V/ ° C

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

V

OH

V

OL

Frequency 1 4.5 MHz
Duty cycle 25 75 %

IOH= 1mA 0.8AVDD V
IOL= 1mA 0.2 AVDD V

IOH= 1mA 0.8DVDD V
IOL= 1mA DGND 0.2 DVDD V

Normal mode, DVDD = 5V,
data rate = 80SPS, internal oscillator

data rate = 20SPS, internal oscillator
Sleep mode 0.2 µ A
Converting, AVDD = 5V,

data rate = 80SPS, internal oscillator

data rate = 20SPS, internal oscillator
Sleep mode 0.1 µ A
AVDD = DVDD = 5V,

data rate = 80SPS, internal oscillator
AVDD = DVDD = 3.3V,

data rate = 20SPS, internal oscillator

0.7AVDD AVDD V
AVSS 0.3AVDD V

0.7DVDD DVDD V

DGND 0.3DVDD V

230 µ A

210 µ A

350 µ A

212 µ A

2.9 mW

1.2 mW

= +2.048V, unless

REF

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Product Folder Link(s): ADS1246 ADS1247 ADS1248

DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

REFP1

REFN1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

IEXC1

IEXC2

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

AIN7/IEXC/GPIO7

AIN6/IEXC/GPIO6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS1248

ADS1246
ADS1247
ADS1248

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.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

PIN CONFIGURATIONS

PW PACKAGE

TSSOP-28

(TOP VIEW)

ADS1248 (TSSOP-28) PIN DESCRIPTIONS

NAME PIN NO. INPUT/OUTPUT DESCRIPTION

DVDD 1 Digital Digital Power Supply
DGND 2 Digital Digital Ground
CLK 3 Digital Input External Clock Input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital Input Chip Reset (active low). Returns all register values to reset values.

REFP0/GPIO0 5

REFN0/GPIO1 6
REFP1 7 Analog Input Positive External Reference 1 Input

REFN1 8 Analog Input Negative External Reference 1 Input
VREFOUT 9 Analog Output Positive Internal Reference Voltage Output

VREFCOM 10 Analog Output
AIN0/IEXC 11 Analog Input Analog Input 0, optional Excitation Current Output

AIN1/IEXC 12 Analog Input Analog Input 1, optional Excitation Current Output
AIN4/IEXC/GPIO4 13

AIN5/IEXC/GPIO5 14

AIN6/IEXC/GPIO6 15

AIN7/IEXC/GPIO7 16

AIN2/IEXC/GPIO2 17

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5

ANALOG/DIGITAL

Analog Input Positive External Reference Input 0, or
Digital In/Out General-Purpose Digital Input/Output Pin 0

Analog Input Negative External Reference 0 Input, or
Digital In/Out General-Purpose Digital Input/Output Pin 1

Negative Internal Reference Voltage Output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.

Analog Input Analog Input 4, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 4

Analog Input Analog Input 5, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 5

Analog Input Analog Input 6, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 6

Analog Input Analog Input 7, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 7

Analog Input Analog Input 2, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 2

Product Folder Link(s): ADS1246 ADS1247 ADS1248

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

ADS1248 (TSSOP-28) PIN DESCRIPTIONS (continued)

NAME PIN NO. INPUT/OUTPUT DESCRIPTION

AIN3/IEXC/GPIO3 18
IOUT2 19 Analog Output Excitation Current Output 2

IOUT1 20 Analog Output Excitation Current Output 1
AVSS 21 Analog Negative Analog Power Supply
AVDD 22 Analog Positive Analog Power Supply
START 23 Digital Input Conversion start. See text for complete description.
CS 24 Digital Input Chip Select (active low)
DRDY 25 Digital Output Data Ready (active low)

DOUT/ DRDY 26 Digital Output
DIN 27 Digital Input Serial Data Input

SCLK 28 Digital Input Serial Clock Input

ANALOG/DIGITAL

Analog Input Analog Input 3, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 3

Serial Data Out Output, or
Data Out combined with Data Ready (active low when DRDY function enabled)

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DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

ADS1247

ADS1246
ADS1247
ADS1248

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DVDD 1 Digital Digital Power Supply
DGND 2 Digital Digital Ground
CLK 3 Digital Input External Clock Input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital Input Chip Reset (active low). Returns all register values to reset values.

REFP0/GPIO0 5

REFN0/GPIO1 6
VREFOUT 7 Analog Output Positive Internal Reference Voltage Output
VREFCOM 8 Analog Output
AIN0/IEXC 9 Analog Input Analog Input 0, optional Excitation Current Output

AIN1/IEXC 10 Analog Input Analog Input 1, optional Excitation Current Output
AIN2/IEXC/GPIO2 11

AIN3/IEXC/GPIO3 12
AVSS 13 Analog Negative Analog Power Supply

AVDD 14 Analog Positive Analog Power Supply
START 15 Digital Input Conversion Start. See text for description of use.
CS 16 Digital Input Chip Select (active low)
DRDY 17 Digital Output Data Ready (active low)

DOUT/ DRDY 18 Digital Output
DIN 19 Digital Input Serial Data Input

SCLK 20 Digital Input Serial Clock Input

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.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

PW PACKAGE

TSSOP-20

(TOP VIEW)

ADS1247 (TSSOP-20) PIN DESCRIPTIONS

NAME PIN NO. INPUT/OUTPUT DESCRIPTION

ANALOG/DIGITAL

Analog Input Positive External Reference Input, or
Digital In/Out General-Purpose Digital Input/Output Pin 0

Analog Input Negative External Reference Input, or
Digital In/Out General-Purpose Digital Input/Output Pin 1

Analog Input Analog Input 2, optional Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 2

Analog Input Analog Input 3, with or without Excitation Current Output, or
Digital In/Out General-Purpose Digital Input/Output Pin 3

Product Folder Link(s): ADS1246 ADS1247 ADS1248

Negative Internal Reference Voltage Output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.

Serial Data Out Output, or
Data Out combined with Data Ready (active low when DRDY function enabled)

DVDD

DGND

CLK

RESET

REFP

REFN

AINP

AINN

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADS1246

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

PW PACKAGE

TSSOP-16

(TOP VIEW)

ADS1246 (TSSOP-16) PIN DESCRIPTIONS

NAME PIN NO. INPUT/OUTPUT DESCRIPTION

DVDD 1 Digital Digital Power Supply
DGND 2 Digital Digital Ground
CLK 3 Digital Input External Clock Input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital Input Chip Reset (active low). Returns all register values to reset values.
REFP 5 Analog Input Positive External Reference Input
REFN 6 Analog Input Negative External Reference Input
AINP 7 Analog Input Positive Analog Input
AINN 8 Analog Input Negative Analog Input
AVSS 9 Analog Negative Analog Power Supply
AVDD 10 Analog Positive Analog Power Supply
START 11 Digital Input Conversion Start. See text for description of use.
CS 12 Digital Input Chip Select (active low)
DRDY 13 Digital Output Data Ready (active low)

DOUT/ DRDY 14 Digital Output
DIN 15 Digital Input Serial Data Input

SCLK 16 Digital Input Serial Clock Input

ANALOG/DIGITAL

Serial Data Out Output, or
Data Out combined with Data Ready (active low when DRDY function enabled)

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SCLK

DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]

DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]

CS

DOUT/DRDY

(1)

DIN

t

CSSC

t

DIST

t

DIHD

t

SCLK

t

SCCS

t

CSDO

t

DOPD

t

SPWL

t

SPWH

t

DOHD

SCLK

(3)

1 2 3 87654

DRDY

t

STD

t

DTS

t

PWH

ADS1246
ADS1247
ADS1248

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TIMING DIAGRAMS

.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

Figure 1. Serial Interface Timing

Table 1. Timing Characteristics for Figure 1

(1)

SYMBOL DESCRIPTION MIN MAX UNIT

t

CSSC

t

SCCS

t

DIST

t

DIHD

t

DOPD

t

DOHD

t

SCLK

t

SPWH

t

SPWL

t

CSDO

CS low to first SCLK high (set up time) 10 ns
SCLK low to CS high (hold time) 7 t
DIN set up time 5 ns
DIN hold time 5 ns
SCLK rising edge to new data valid 30 ns
DOUT hold time 0 ns

SCLK period

500 ns

SCLK pulse width high 0.25 0.75 t
SCLK pulse width low 0.25 0.75 t
CS high to DOUT high impedance 10 ns

(1) DRDY MODE bit = 0.
(2) t

= 1/f

OSC

. The default clock frequency f

CLK

= 4.096MHz. Expect a ± 5% variation whan the internal oscillator is used.

CLK

(2)

OSC

64 conversions

SCLK
SCLK

Figure 2. SPI Interface Timing to Allow Conversion Result Loading

(3) (4)

Table 2. Timing Characteristics for Figure 2

SYMBOL DESCRIPTION MIN MAX UNIT

t

PWH

t

STD

t

DTS

(3) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during t
(4) SCLK should only be sent in multiples of eight during partial retrieval of output data.

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 9

DRDY pulse width high 3 t
SCLK low prior to DRDY low 5 t
DRDY falling edge to SCLK rising edge 30 ns

when CS is high.

STD

Product Folder Link(s): ADS1246 ADS1247 ADS1248

OSC
OSC

t

START

START

SCLK

CS

RESET

t

RESET

t

RHSC

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

Figure 3. Minimum START Pulse Width

Table 3. Timing Characteristics for Figure 3

SYMBOL DESCRIPTION MIN MAX UNIT

t

START

START pulse width high 3 t

Figure 4. Reset Pulse Width and SPI Communication After Reset

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OSC

Table 4. Timing Characteristics for Figure 4

SYMBOL DESCRIPTION MIN MAX UNIT

t

RESET

t

RHSC

(1) Applicable only when f

RESET pulse width low 4 t
RESET high to SPI communication start 0.6

= 4.096MHz and scales proportionately with f

OSC

frequency.

OSC

(1)

NOISE PERFORMANCE

Table 5. Noise in µ V, rms and ( µ V, peak-to-peak) at AVDD = DVDD = 5V, AVSS = DGND = 0V,

Using Internal Reference (2.048V)

DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128

5 1.79 (8.10) 0.76 (3.90) 0.40 (2.00) 0.23 (1.05) 0.12 (0.63) 0.08 (0.39) 0.07 (0.34) 0.06 (0.32)
10 2.46 (13.80) 1.04 (5.50) 0.56 (2.75) 0.31 (1.75) 0.14 (0.78) 0.10 (0.46) 0.09 (0.52) 0.08 (0.43)
20 3.20 (14.00) 1.53 (8.00) 0.85 (5.00) 0.45 (2.80) 0.25 (1.17) 0.16 (0.73) 0.12 (0.56) 0.11 (0.63)
40 3.30 (18.00) 1.50 (7.80) 0.86 (4.84) 0.40 (2.16) 0.30 (1.75) 0.20 (1.25) 0.17 (0.87) 0.16 (0.85)
80 4.60 (27.10) 2.23 (14.00) 1.00 (4.80) 0.64 (3.25) 0.38 (2.40) 0.29 (1.82) 0.27 (1.69) 0.23 (1.30)

160 7.00 (42.00) 3.30 (20.00) 1.52 (9.25) 0.83 (5.10) 0.55 (3.14) 0.41 (3.00) 0.35 (2.14) 0.34 (2.40)
320 10.60 (67.00) 5.60 (40.00) 2.90 (17.50) 1.47 (8.70) 0.85 (5.14) 0.59 (4.03) 0.49 (3.10) 0.48 (3.10)

640 15.80 (101.00) 8.30 (52.00) 4.20 (24.80) 2.14 (15.50) 1.23 (8.25) 0.82 (5.21) 0.67 (4.55) 0.66 (4.30)
1000 38.00 (420.00) 19.70 (190.00) 8.80 (67.50) 4.50 (40.30) 2.64 (24.80) 1.47 (14.34) 0.96 (6.23) 0.83 (5.30)
2000 40.80 (449.00) 18.40 (179.00) 9.30 (87.00) 4.80 (43.50) 2.56 (22.60) 1.63 (11.90) 1.32 (10.60) 1.23 (7.40)

OSC

ms

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EffectiveNumberofBits=

ln(FSR/Noise)

ln(2)

EffectiveNumberofBits=

ln(FSR/Noise)

ln(2)

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.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

Table 6. Effective Number of Bits, rms and (peak-to-peak) Noise Using the Internal Reference (+2.048V)

DATA PGA SETTING

RATE
(SPS) 1 2 4 8 16 32 64 128

5 21.50 (19.10) 21.60 (19.30) 21.60 (19.20) 21.40 (19.20) 21.30 (19.00) 20.90 (18.60) 20.10 (17.80) 19.20 (17.00)
10 21.00 (18.50) 21.20 (18.80) 21.10 (18.80) 21.00 (18.40) 20.90 (18.40) 20.50 (18.10) 19.70 (17.40) 18.70 (16.60)
20 20.60 (18.40) 20.60 (18.20) 20.50 (17.90) 20.40 (17.80) 20.30 (17.80) 20.00 (17.50) 19.20 (16.60) 18.20 (16.00)
40 20.50 (18.10) 20.70 (18.30) 20.50 (18.00) 20.60 (18.10) 20.10 (17.90) 19.60 (17.30) 18.90 (16.50) 17.80 (15.40)
80 20.10 (17.50) 20.10 (17.40) 20.30 (18.00) 19.90 (17.60) 19.70 (17.40) 19.20 (16.40) 18.30 (16.00) 17.40 (15.20)

160 19.40 (16.90) 19.60 (17.00) 19.60 (17.10) 19.50 (16.90) 19.40 (16.60) 18.70 (16.30) 17.80 (15.20) 16.80 (14.50)
320 18.90 (16.20) 18.80 (16.00) 18.70 (16.10) 18.70 (16.20) 18.50 (16.10) 18.00 (15.60) 17.30 (14.80) 16.40 (13.80)

640 18.30 (15.60) 18.20 (15.60) 18.20 (17.50) 18.20 (15.30) 18.00 (15.30) 17.60 (15.20) 16.70 (14.10) 15.90 (13.20)
1000 17.00 (13.50) 16.90 (13.70) 17.10 (14.20) 17.10 (13.90) 16.90 (13.80) 16.80 (13.50) 16.30 (13.60) 15.50 (12.70)
2000 16.90 (13.40) 17.10 (13.80) 17.00 (13.80) 17.00 (13.80) 16.80 (13.40) 16.50 (13.70) 15.90 (13.20) 14.90 (12.20)

(1)

Table 7. Noise in µ V, rms and ( µ V, peak-to-peak) at AVDD = DVDD = 5V, AVSS = DGND = 0V,

Using External Reference (2.5V)

DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128

5 1.22 (5.50) 0.75 (4.20) 0.41 (2.10) 0.21 (1.10) 0.11 (0.48) 0.07 (0.34) 0.06 (0.3) 0.05 (0.23)
10 1.67 (9.83) 0.89 (4.02) 0.55 (2.98) 0.30 (1.07) 0.16 (0.73) 0.09 (0.54) 0.07 (0.39) 0.07 (0.37)
20 2.55 (14.90) 1.33 (7.45) 0.77 (4.25) 0.37 (2.09) 0.20 (1.10) 0.13 (0.77) 0.11 (0.57) 0.10 (0.59)
40 3.03 (19.07) 1.46 (8.49) 0.75 (4.25) 0.41 (2.46) 0.24 (1.27) 0.15 (0.84) 0.16 (0.86) 0.15 (0.83)
80 3.95 (24.73) 2.04 (13.56) 0.88 (5.74) 0.54 (3.80) 0.33 (2.16) 0.21 (1.35) 0.21 (1.28) 0.19 (1.18)

160 5.71 (45.59) 2.80 (19.52) 1.43 (10.06) 0.74 (5.70) 0.45 (3.20) 0.29 (2.11) 0.29 (1.90) 0.28 (1.89)
320 10.41 (82.84) 5.18 (43.06) 2.97 (21.15) 1.35 (10.91) 0.76 (5.70) 0.50 (3.39) 0.41 (3.02) 0.39 (2.67)

640 14.58 (130.50) 7.52 (64.21) 4.01 (31.71) 1.68 (11.74) 1.05 (9.58) 0.70 (5.39) 0.58 (4.07) 0.54 (3.92)
1000 35.52 (481.70) 17.64 (206.40) 12.77 (102.00) 5.11 (41.60) 2.21 (25.67) 1.26 (13.53) 0.84 (8.03) 0.71 (5.48)
2000 35.42 (415.20) 17.41 (199.60) 8.76 (101.00) 4.51 (50.54) 2.43 (26.18) 1.51 (13.60) 1.18 (8.78) 1.08 (7.52)

ADS1246
ADS1247
ADS1248

(1)

Table 8. Effective Number of Bits, rms and (peak-to-peak) Noise Using External Reference (+2.5V)

DATA PGA SETTING

RATE
(SPS) 1 2 4 8 16 32 64 128

10 21.50 (19.00) 21.40 (19.20) 21.10 (18.70) 21.00 (18.30) 20.90 (18.70) 20.80 (18.10) 20.10 (17.60) 19.00 (16.70)
20 20.90 (18.40) 20.80 (18.40) 20.60 (18.20) 20.70 (18.20) 20.60 (18.10) 20.20 (17.60) 19.50 (17.10) 18.60 (16.00)
40 20.70 (18.00) 20.70 (18.20) 20.70 (18.20) 20.50 (18.00) 20.30 (17.90) 20.00 (17.50) 18.90 (16.50) 18.00 (15.50)

80 20.30 (17.60) 20.20 (17.50) 20.40 (17.70) 20.10 (17.30) 19.90 (17.10) 19.50 (16.80) 18.50 (15.90) 17.60 (15.00)
160 19.70 (16.70) 19.80 (17.00) 19.70 (16.90) 19.70 (16.70) 19.40 (16.60) 19.10 (16.20) 18.00 (15.30) 17.00 (14.30)
320 18.90 (15.90) 18.90 (15.80) 18.70 (15.90) 18.80 (15.80) 18.70 (15.70) 18.30 (15.50) 17.50 (14.70) 16.60 (13.80)
640 18.40 (15.20) 18.30 (15.20) 18.30 (15.30) 18.50 (15.70) 18.20 (15.00) 17.80 (14.80) 17.00 (14.20) 16.10 (13.30)

1000 17.10 (13.30) 17.10 (13.60) 16.60 (13.60) 16.90 (13.90) 17.10 (13.60) 16.90 (13.50) 16.50 (13.20) 15.80 (12.80)
2000 17.10 (13.60) 17.10 (13.60) 17.10 (13.60) 17.10 (13.60) 17.00 (13.50) 16.70 (13.50) 16.00 (13.10) 15.10 (12.30)

(1)

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11

5 22.00 (19.80) 21.70 (19.20) 21.60 (19.20) 21.50 (19.20) 21.40 (19.30) 21.00 (18.80) 20.30 (18.00) 19.60 (17.40)

Product Folder Link(s): ADS1246 ADS1247 ADS1248

(1)

Counts

-53

-49

-

45

-41

-37

-33

-29

-26

-

22

-18

-14

-10

-6

-3

0

4

8

12

16

19

23

27

31

35

39

43

47

1800

1600

1400

1200

1000

800

600

400

200

0

PGA=1
DataRate=20SPS
12kSamples

=13s

(LSB)

Counts

-69

-63

-58

-52

-

47

-41

-36

-30

-25

-20

-14

-9

-3

1

7

12

18

23

28

34

39

45

50

56

61

67

73

1800

1600

1400

1200

1000

800

600

400

200

0

PGA=32
DataRate=20SPS
12kSamples

=19s

(LSB)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

RMSNoise(

V)m

V (%ofFSR)

IN

-100 -80 -60 -40 -20 10020 40 60 80

PGA=32

DataRate=5SPS

4

3

2

1

0

-1

-2

-3

Temperature( C)°

Input-ReferredOffset( V)m

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=20SPS

8

6

4

2

0

-2

-4

-6

-8

Temperature( C)°

Input-ReferredOffset( V)m

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=160SPS

8

6

4

2

0

-2

-4

-6

-8

-10

-12

-14

Temperature( C)°

Input-ReferredOffset( V)m

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=640SPS

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

TYPICAL CHARACTERISTICS

At TA= +25 ° C, AVDD = DVDD = 5V, V

NOISE HISTOGRAM PLOT NOISE HISTOGRAM PLOT

Figure 5. Figure 6.

= 2.5V, and AVSS = DVSS = 0V, unless otherwise noted.

REF

www.ti.com

RMS NOISE

vs INPUT SIGNAL OFFSET vs TEMPERATURE

Figure 7. Figure 8.

OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE

12 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

Figure 9. Figure 10.

Product Folder Link(s): ADS1246 ADS1247 ADS1248

15

10

5

0

-5

-10

-15

Temperature(°C)

Input-ReferredOffset(

m

V)

-40 -20 0 20 40 60 80 100 120

PGA=32

DataRate=2kSPS

PGA=1

PGA=128

0.05

0.04

0.03

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

-0.05

Temperature( C)°

GainError(%)

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=20SPS

0.03

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

Temperature( C)°

GainError(%)

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=160SPS

0.03

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

Temperature( C)°

GainError(%)

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

DataRate=640SPS

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

Temperature( C)°

GainError(%)

-40 -20 0 20 40 60 80 100 120

PGA=32

PGA=1

PGA=128

600

550

500

450

400

350

300

250

200

150

100

DataRate(SPS)

AnalogCurrent( A)m

5 10 20 40 80 160 320 640 1000 2000

AVDD=5V

AVDD=3.3V

www.ti.com

.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

At TA= +25 ° C, AVDD = DVDD = 5V, V

OFFSET vs TEMPERATURE GAIN vs TEMPERATURE

Figure 11. Figure 12.

GAIN vs TEMPERATURE GAIN vs TEMPERATURE

TYPICAL CHARACTERISTICS (continued)

= 2.5V, and AVSS = DVSS = 0V, unless otherwise noted.

REF

ADS1246
ADS1247
ADS1248

Figure 13. Figure 14.

GAIN vs TEMPERATURE vs DATA RATE

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 15. Figure 16.

ANALOG CURRENT

Product Folder Link(s): ADS1246 ADS1247 ADS1248

290

270

250

230

210

190

170

DataRate(SPS)

DigitalCurrent( A)m

5 10 20 40 80 160 320 640 1000 2000

DVDD=3.3V

DVDD=5V

800

700

600

500

400

300

200

100

0

Temperature( C)°

AnalogCurrent( A)

m

-40 -20 0 20 40 60 80 100 120

5SPS

40SPS

320SPS

2kSPS

330

310

290

270

250

230

210

190

Temperature( C)°

DigitalCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

8

6

4

2

0

-2

-4

-6

-8

V (%ofFSR)

IN

INL(ppmofFSR)

-100 -50 0 50 100

PGA=1

DataRate=20SPS

- °40 C

- °10 C

+25 C°

+105 C°

8

6

4

2

0

-2

-4

-6

-8

-10

V (%ofFSR)

IN

INL(ppmofFSR)

-100 -50 0 50 100

PGA=32

DataRate=20SPS

- °40 C

+25 C°

+105 C°

- °10 C

8

6

4

2

0

-2

-4

-6

-8

V (%ofFSR)

IN

INL(ppmofFSR)

-100 -50 0 50 100

PGA=128

DataRate=20SPS

-40°C

+25 C°

+105 C°

-10°C

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

At TA= +25 ° C, AVDD = DVDD = 5V, V

DIGITAL CURRENT ANALOG CURRENT

vs DATA RATE vs TEMPERATURE

Figure 17. Figure 18.

TYPICAL CHARACTERISTICS (continued)

= 2.5V, and AVSS = DVSS = 0V, unless otherwise noted.

REF

www.ti.com

DIGITAL CURRENT INTEGRAL NONLINEARITY

vs TEMPERATURE vs INPUT SIGNAL

Figure 19. Figure 20.

INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY

vs INPUT SIGNAL vs INPUT SIGNAL

14 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

Figure 21. Figure 22.

Product Folder Link(s): ADS1246 ADS1247 ADS1248

8

6

4

2

0

-2

-4

-6

-8

V (%ofFSR)

IN

INL(ppmofFSR)

-100 -50 0 50 100

PGA=1

DataRate=2kSPS

- °40 C

+25 C°

+105 C°

- °10 C

650

648

646

644

642

640

638

636

634

632

630

Temperature( C)°

DataRate(SPS)

-40 -20 0 20 40 60 80 100 120

DataRate=640SPSusingInternalOscillator

130

125

120

115

110

105

100

95

90

85

80

Temperature( C)°

CMRR(dB)

-40 -20 0 20 40 60 80 100 120

PGA=1

PGA=32

PGA=128

2.050

2.049

2.048

2.047

2.046

Temperature( C)°

OutputVoltage(V)

-40 -20 0 20 40 60 80 100 120

14Units

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991

AVDD(V)

NormalizedOutputCurrent

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

750 Am

250 Am

1.5mA

500 Am

100 Am

1mA

50 Am

IDACCurrentSettings

0.004

0.003

0.002

0.001

0

-0.001

-0.002

-0.003

-0.004

Temperature( C)°

IEXC1 IEXC2(- mA)

-40 -20 0 20 40 60 80 100 120

1.5mASetting,10Units

www.ti.com

.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

At TA= +25 ° C, AVDD = DVDD = 5V, V

INTEGRAL NONLINEARITY DATA RATE

vs INPUT SIGNAL vs TEMPERATURE

Figure 23. Figure 24.

TYPICAL CHARACTERISTICS (continued)

= 2.5V, and AVSS = DVSS = 0V, unless otherwise noted.

REF

ADS1246
ADS1247
ADS1248

CMRR INTERNAL V

vs TEMPERATURE vs TEMPERATURE

Figure 25. Figure 26.

IDAC LINE REGULATION IDAC DRIFT

REF

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15

Figure 27. Figure 28.

Product Folder Link(s): ADS1246 ADS1247 ADS1248

ADS1246
ADS1247
ADS1248

SBAS426B – AUGUST 2008 – REVISED MARCH 2009 ....................................................................................................................................................

GENERAL DESCRIPTION

OVERVIEW

The ADS1246/47/48 are highly integrated, low-noise,
24-bit, delta-sigma ADCs. They include a flexible
input multiplexer, a low-noise, high input impedance
PGA, a built-in very low drift voltage reference with
10mA output capability (ADS1247/48), an internal Any analog input pin can be selected as the positive
temperature sensor, and two highly-matched current input or negative input through the MUX0 register.
sources. An SPI-compatible serial communication The ADS1246/47/48 have a true fully differential
interface is also provided. A set of simple commands mode, meaning that the input signal range can be
control the ADS1246/47/48 devices. from – 2.5V to +2.5V (when AVDD = 2.5V and AVSS

The ADS1246/47/48 provide two conversion modes:
single-conversion and continuous-conversion. In Through the input multiplexer, the ambient
single-conversion mode, the ADC converts the input temperature (internal temperature sensor), AVDD,
signal once and the conversion result (data) is stored DVDD, and external reference can all be selected for
in the data register. The data can be read any time measurement. Refer to the System Monitor section
before the next conversion. Single-conversion mode for details.
can be started by applying a pulse to the START pin
or by executing an SPI command. Upon completing
the conversion, the device goes into sleep mode to
minimize power consumption.

The ADS1246/47/48 also provide a system monitor
function that monitors the external voltage references,
analog power-supply voltage, digital power supply,
and onboard temperature. The burnout current
source can be used to detect sensor open-circuit
conditions.

The ADS1246/47/48 simultaneously reject 50Hz and GPIOs.
60Hz interference with greater than 100dB rejection
ratio for data rates up to 20SPS.

ADC INPUT AND MULTIPLEXER

The ADS1246/47/48 ADC measures the input signal
through the onboard PGA. All analog inputs are
connected to the internal AIN
through the analog multiplexer. A block diagram of
the analog input multiplexer is shown in Figure 29 .

The input multiplexer connects to eight (ADS1248),
four (ADS1247), or two (ADS1246) analog inputs that

or AIN

P

analog inputs

N

can be configured as single-ended inputs, differential
inputs, or in a combination of single-ended and
differential inputs. The multiplexer also allows the
on-chip excitation current and/or bias voltage to be
selected to a specific channel.

= – 2.5V).

On the ADS1247 and ADS1248, the analog inputs
can also be configured as general-purpose
inputs/outputs (GPIOs). See the General-Purpose

Digital I/O section for more details.

ESD diodes protect the ADC inputs. To prevent these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
100mV, and do not exceed AVDD by more than
100mV, as shown in Equation 1 . Note that the same
caution is true if the inputs are configured to be

AVSS – 100mV < (AINX) < AVDD + 100mV (1)

Settling Time for Channel Multiplexing

The ADS1246/47/48 is a true single-cycle settling,
delta-sigma converter. After the internal multiplexer
switches, the very first data are valid.

www.ti.com

16 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

Product Folder Link(s): ADS1246 ADS1247 ADS1248

(MUXCAL=001)

SystemMonitors

Temperature
Diode

VREFP

VREFN

VREFP1/4

VREFN1/4

VREFP0/4

VREFN0/4

AVDD/4

AVSS/4

DVDD/4

DVSS/4

ADS1248Only

ADS1247/48Only

VBIAS

AIN0

AIN1

VBIAS

AIN2

VBIAS

AIN3

VBIAS

AIN4

VBIAS

AIN5

VBIAS

AIN6

VBIAS

AIN7

AVDD

IDAC1

IDAC2

AVDD

VBIAS

PGA

AIN

P

AVSS

AVDD

BurnoutCurrentSource
(0.5 A,2 A,10m m mA)

BurnoutCurrentSource
(0.5 A,2 A,10m m mA)

AIN

N

To
ADC

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD AVDD

REFN1REFP1

ADC

ADS1248 Only

REFN0REFP0

REFNREFP

VREFCOMVREFOUT

ReferenceMultiplexer

Internal
Voltage

Reference

ADS1246
ADS1247
ADS1248

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.................................................................................................................................................... SBAS426B – AUGUST 2008 – REVISED MARCH 2009

Figure 29. Analog Input Multiplexer Circuit

VOLTAGE REFERENCE INPUT

The voltage reference for the ADS1246/47/48 is the
differential voltage between REFP and REFN:

V

= V

REF

– V

REFP

REFN

In the case of the ADS1246, these pins are dedicated
inputs. For the ADS1247 and ADS1248, there is a
multiplexer that selects the reference inputs, as
shown in Figure 30 . The reference input uses a buffer
to increase the input impedance.

Figure 30. Reference Input Multiplexer

As with the analog inputs, REFP0 and REFN0 can be
configured as digital I/Os on the ADS1247/48.

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): ADS1246 ADS1247 ADS1248