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ADS1245
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
Low-Power, 24-Bit
Analog-to-Digital Converter
FEATURES
D 20-Bit Effective Resolution
D High-Impedance Buffered Input
D ±2.5V Differential Input Range
D Pin-Compatible with ADS1244
D 0.0006% INL (typ), 0.0015% INL (max)
D Simple Two-Wire Serial Interface
D Simultaneous 50Hz and 60Hz Rejection
D Single Conversions with Sleep Mode
D Single-Cycle Settling
D Self-Calibration
D Well Suited for Multi-Channel Systems
D Easily Connects to the MSP430
D Current Consumption: 158µA
D Analog Supply: 2.5V to 5.25V
D Digital Supply: 1.8V to 3.6V
APPLICATIONS
D Hand-Held Instrumentation
D Portable Medical Equipment
D Industrial Process Control
D Test and Measurement Systems
DESCRIPTION
The ADS1245 is a 24-bit, delta-sigma analog-to-digital
converter (ADC). It offers excellent performance and very
low power in an MSOP-10 package and is well suited for
demanding high-resolution measurements, especially in
portable and other space- and power-constrained
systems.
The buffered input presents an impedance of 3GΩ, mini-
mizing measurement errors when using high-impedance
sources. The ADS1245 is compatible with ADS1244 and
offers a direct upgrade path for designs requiring higher input impedance.
A third-order delta-sigma (∆Σ) modulator and digital filter
form the basis of the ADC. The analog modulator has a
±2.5V differential input range. The digital filter rejects both
50Hz and 60Hz signals, completely settles in one cycle,
and outputs data at 15 samples per second (SPS).
A simple, two-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Sleep mode are handled with a few simple waveforms.
When only single conversions are needed, the ADS1245
can be shut down (Sleep mode) while idle between
measurements to dramatically reduce the overall power
dissipation. Multiple ADS1245s can be connected
together to create a synchronously sampling multichannel
measurement system. The ADS1245 is designed to easily
connect to microcontrollers, such as the MSP430.
The ADS1245 supports 2.5V to 5.25V analog supplies and
1.8V to 3.6V digital supplies. Power is typically less than
470µW in normal operation and less than 1µW during
Sleep mode.
VREFP VREFN AVDD
AINP
AINN
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
! !
Buffer
3rd−Order
Modulator
Digital
Filter
GND
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DVDD
Serial
Interface
CLK
DRDY/DOUT
SCLK
Copyright 2003, Texas Instruments Incorporated
"#$%&
ADS1245
MSOP-10
DGS
−40°C to +85°C
BHI
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
ORDERING INFORMATION
PRODUCT PACKAGE−LEAD
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE
DESIGNATOR
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
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ORDERING
NUMBER
ADS1245IDGST Tape and Reel, 250
ADS1245IDGSR Tape and Reel, 2500
TRANSPORT
MEDIA, QUANTITY
ABSOLUTE MAXIMUM RATINGS
over operat i n g f ree-air temperature range unless otherwise noted
ADS1245 UNIT
AVDD to GND −0.3 to +6 V
DVDD to GND −0.3 to +3.6 V
Input Current 100, momentary mA
Input Current 10, continuous mA
Analog Input Voltage to GND −0.5 to AVDD + 0.5 V
Analog Input Voltage to GND −0.3 to DVDD + 0.3 V
Digital Output Voltage to GND −0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range −40 to +85 °C
Storage Temperature Range −60 to +150 °C
Lead Tem perature (soldering, 10s) +300 °C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
(1)
PIN ASSIGNMENTS
DGS PACKAGE
MSOP
(TOP VIEW)
ADS1245
GND
VREFP
VREFN
AINN
AINP
1
2
3
4
5
10
9
8
7
6
CLK
SCLK
DRDY/DOUT
DVDD
AVDD
Terminal Functions
TERMINAL
NAME NO. DESCRIPTION
GND 1 Analog and digital ground
VREFP 2 Positive reference input
VREFN 3 Negative reference input
AINN 4 Negative analog input
AINP 5 Positive analog input
AVDD 6 Analog power supply, 2.5V to 5.25V
DVDD 7 Digital power supply, 1.8V to 3.6V
DRDY/DOUT 8 Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the
first rising edge of SCLK.
SCLK 9 Serial clock input: clocks out data on the
rising edge. Used to initiate calibration and
Sleep mode (see text for more details).
CLK 10 System clock input: typically 2.4576MHz
2
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Common-mode rejection
Normal-mode rejection
Logic levels
AVDD current
DVDD current
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +3V, f
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
Full-scale input voltage range AINP − AINN ±2V
Absolute input range AINP, AINN with respect to GND GND + 0.1 AVDD − 1.25 V
Differential input impedance f
System Performance
Resolution No missing codes 24 Bits
Data rate f
Integral nonlinearity (INL) Differential input signal, end point fit ±0.0006 ±0.0015 %FSR
Offset error 1 14 ppm of FSR
Offset error drift
Gain error
Gain error drift
Common-mode rejection
Input referred noise 2
Analog power-supply rejection At DC, ∆AVDD = 5% 100 dB
Digital power-supply rejection At DC, ∆AVDD = 5% 100 dB
Voltage Reference Input
Reference input voltage (V
Negative reference input (VREFN) GND − 0.1 VREFP − 0.5 V
Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V
Voltage reference impedance f
Digital Input/Output
Input leakage (CLK, SCLK) 0 < (CLK, SCLK) < DVDD ±10 µA
CLK frequency (f
CLK duty cycle 30 70 %
Power Supply
AVDD 2.7 5.25 V
DVDD 1.8 3.6 V
AVDD current
DVDD current
Total power dissipation AVDD = DVDD = 3V 0.47 mW
(1)
SPS = samples per second.
(2)
FSR = full-scale range = 4V
(3)
Recalibration can reduce these errors to the level of the noise.
(4)
Achieving specified gain error performance requires that calibration be performed with reference voltage input between (GND + 0.1V) and
(AVDD − 1.25V). See Voltage Reference Inputs section.
(5)
fCM is the frequency of the common-mode input.
(6)
f
SIG
(7)
It will not be possible to reach the digital output full-scale code when VIN > 2V
(3)
(4)
(3)
) V
REF
VIH (CLK, SCLK) 0.8 DVDD 5.25 V
VIL (CLK, SCLK) GND 0.2 DVDD V
VOH (DRDY, DOUT) IOH = 1mA DVDD − 0.4 DVDD V
VOL (DRDY, DOUT) IOL = 1mA GND DVDD + 0.4 V
) 6 MHz
CLK
.
REF
is the frequency of the input signal.
= 2.4576MHz 3 GΩ
CLK
= 2.4576MHz 15 SPS
CLK
At DC 90 100 dB
(5)
f
= 50 ± 1Hz, f
CM
fCM = 60 ± 1Hz, f
(6)
f
= 50 ± 1Hz, f
SIG
f
= 60 ± 1Hz, f
SIG
≡ VREFP − VREFN 0.5 1.25 AVDD
REF
= 2.4576MHz 1 MΩ
CLK
Sleep mode 0.1 1 µA
AVDD = 3V 152 µA
AVDD = 5V 158 250 µA
Sleep mode, CLK stopped 0.1 µA
Sleep mode, 2.4576MHZ CLK running 1.6 5 µA
DVDD = 3V 5 10 µA
CLK
= 2.4576MHz 100 dB
CLK
CLK
= 2.4576MHz 70 dB
CLK
= 2.4576MHz, and V
CLK
= 2.4576MHz 100 dB
= 2.4576MHz 60 dB
.
REF
= +1.25V , unless otherwise noted.
REF
REF
0.01 ppm of FSR/°C
0.005 0.1 %
0.5 ppm/°C
(7)
ppm of FSR,
RMS
V
(1)
V
(2)
3
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ANALOG CURRENT vs ANALOG SUPPLY
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3V, f
CLK
= 2.4576MHz, and V
= +1.25V , unless otherwise specified.
REF
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220
210
200
190
180
A)
µ
170
160
150
Current (
140
130
120
110
100
−
ANALOG CURRENT vs TEMPERATURE
AVDD = +5V, f
−
−
45
5
25 35 55 75 95
= 4.9152MHz
CLK
AVDD = +3V, f
15
Temp erature (_C)
CLK
=2.4576MHz
12
10
8
A)
µ
6
Current (
4
2
0
−
45
Figure 1
164
162
160
A)
158
µ
156
154
Current(
152
150
148
f
=4.9152Hz
CLK
f
=2.4576MHz
CLK
Analog Supply (V)
4.03.53.0 4.5 5.0 5.52.5
16
14
12
A)
10
µ
8
6
Current (
4
2
0
−
DIGITALCURRENT vs TEMPERATURE
DVDD = +3V, f
DVDD = +1.8V, f
−
−
25 35 55 75 95
15
5
Temperature (_C)
= 4.9152MHz
CLK
CLK
Figure 2
DIGITALCURRENT vs DIGITALSUPPLY
f
= 4.9152MHz
CLK
f
= 2.4576MHz
CLK
−
−
25 35 55 75 95
45
15
5
Digital Supply (V)
= 2.4576MHz
Figure 3
INTEGRAL NONLINEARITY vs ANALOG SUPPLY
= 2.4 or (( 1.8)/2 + 0.3), whichever is smaller
V
CM
30
25
20
15
10
INL (ppm of FSR)
5
0
T=+85_C
V
REF
AVDD
= 1.25; f
−
AVDD
Figure 5
4
= 2.4576MHz
OSC
T= 40_C−
T=+25_C
4.03.53.0 4.5 5.0 5.52.5
(V)
Figure 4
12.5
10.0
7.5
5.0
2.5
0
−
2.5
INL (ppm of FSR)
−
5.0
−
7.5
−
10.0
−
12.5
−
2.5
INTEGRAL NONLINEARITY vs V
T=+25_C
T=+85_C
T=−40_C
−
1.5
−
0.5 0.5 1.5 2.5
VIN(V)
IN
Figure 6
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OFFSET vs TEMPERATURE
GAIN vs TEMPERATURE
Gain (Normalized)
HISTOGRAM OF OUTPUT DATA
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3V, f
= 2.4576MHz, and V
CLK
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
= +1.25V , unless otherwise specified.
REF
"#$%&
5
4
3
2
1
0
−
1
−
2
−
3
Normalized Offset (ppm of FSR)
−
4
−
5
−
45
−
−
25 35 55 75 95
15
5
Temperat ure (_C)
Figure 7
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
Noise (ppm of FSR, RMS)
1.6
1.4
1.2
−
2.5
NOISE vs INPUT SIGNAL
−
1.5
−
0.5 0.5 1.5 2.5
VIN(V)
1.00006
1.00005
1.00004
1.00003
1.00002
1.00001
1.00000
0.99999
0.99998
0.99997
0.99996
0.99995
0.99994
3.0
2.5
2.0
1.5
1.0
Noise (ppm of FSR, RMS)
0.5
−
25 35 55 75 95
45
15
5
Temperature (_C)
−
−
Figure 8
NOISE vs TEMPERATURE
0
−
45
−
−
25 35 55 75 95
15
5
Temperature (_C)
Figure 9
COMMON−MODE REJECTION RATIO
900
800
700
600
500
400
300
Number of Occurences
200
100
0
10
−9−8−7−6−5−4−3−2−
−14−12−
1
012345678
ppmof FSR
Figure 11
9
101112
160
140
120
100
80
CMRR (dB)
60
40
20
0
Figure 10
vs FREQUENCY
1k10010 10k 100k1
Frequency (Hz)
Figure 12
5
"#$%&
ANALOGPOWER−SUPPLY REJECTION RATIO
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3V, f
CLK
= 2.4576MHz, and V
= +1.25V , unless otherwise specified.
REF
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DIGITALPOWER−SUPPLYREJECTION RATIO
140
120
100
80
60
PSRR (dB)
40
20
0
vs FREQUENCY
1k10010 10k 100k1
Frequency (Hz)
140
120
100
80
60
PSRR (dB)
40
20
0
Figure 13
vs FREQUENCY
1k10010 10k 100k1
Frequency (Hz)
Figure 14
6
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"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
OVERVIEW
The ADS1245 is a n ADC c omprised of a 3 rd-order m odulator
followed by a digital filter. The modulator measures the
differential input signal VIN = (AINP – AINN) against the
differential reference V
shows a conceptual diagram. The differential reference is
scaled internally so that the full-scale input range is ±2V
The digital filter receives the modul ator signal and provides
a low-noise digital output. The filter al so sets the frequency
response of the converter and provides 50Hz and 60Hz
rejection while settling in a single conversion cycle. A
two-wire serial interface indicates c onversion c ompletion and
provides the user with the output data.
AINP
X1
Σ
X1
AINN
Figure 15. Conceptual Diagram of the ADS1245
ANALOG INPUTS (AINP, AINN)
The input signal to be measured is applied to the input pins
AINP and AINN. The ADS1245 features a low-drift
chopper-stabilized buffer to achieve very high input
impedance. The input impedance can be modeled by
resistors, as shown in Figure 16. The impedance scales
inversely with f
is reduced by a factor of two, the impedances Zeff
of f
CLK
and ZeffB will double.
frequency . For example, if the frequency
CLK
= (VREFP – VREFN). Figure 15
REF
VREFP VREFN
Σ
V
REF
2
2V
REF
V
IN
AVDD/2
Modulator
Digital
Filter and
Serial
Interface
REF
CLK
DRDY/DOUT
SCLK
The ADS1245 accepts differential input signals, but can
also measure unipolar signals. Note that the analog inputs
(listed in the Electrical Characteristics table as Absolute
Input Range) must remain between GND + 0.1V to
AVDD − 1.25V. Exceeding this range will degrade linearity
and result in performance outside specified limits.
.
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference used by the modulator is generated
from the voltage difference between VREFP and VREFN:
V
= VREFP – VREFN. A simplified diagram of the
REF
circuitry on the reference inputs is shown in Figure 17. The
switches and capacitors can be modeled with an effective
impedance equal to:
t
SAMPLE
ǒ
A
S
1
S
2
2
AVDD
ON
OFF
ON
OFF
Ǔ
ń25pF + 1MW for f
VREFP VREFN
S
1
25pF
S
t
= 128/f
SAMPLE
+ 2.4576MHz
CLK
S
1
2
CLK
AVDD
ESD
Protection
= 3.46G
B
= 280G
A
Ω
Ω
Ω
=2.4576MHz.
f
CLK
ZeffA= 280G
AINP
Zeff
AINN
Zeff
AVDD/2
Figure 16. Effective Analog Input Impedances
Figure 17. Simplified Reference Input Circuitry
The ADS1245 is specified for operation with V
= 1.25V,
REF
resulting in a full−scale input value of ±2.5V. However, the
buffered analog inputs can accept voltages within the
range of 0.10V to 3.75V, resulting in a maximum V
of
IN
±3.65V. Input voltages can be accurately measured over
this entire range if a voltage reference of 1.825V is provided. In any case, digital output codes will clip to the full
scale value if the absolute input voltage range exceeds
2V
.
REF
7
"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
To achieve optimal gain error performance, the reference
input should be maintained within the range GND + 0.1V
to AVDD − 1.25V when performing a self-calibration. A
calibration based on a reference input outside this voltage
range will result in gain errors exceeding specified values,
but not more than 0.5%. Errors due to drift will remain
within specified limits regardless of the calibration
procedure.
For best performance, bypass the voltage reference inputs
with a 0.1µF capacitor between VREFP and VREFN.
Place the capacitor as close as possible to the pins.
ESD diodes protect the inputs. To keep these diodes from
turning on, make sure the voltages on the input pins do not
go below GND by more than 100mV, and likewise do not
exceed AVDD by 100mV.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the
ADS1245. The recommended CLK frequency is
2.4576MHz. This places the notches of the digital filter at
50Hz and 60Hz and sets the data rate at 15SPS. The CLK
frequency can be increased to speed up the data rate, but
the frequency notches will move proportionally in
frequency. CLK must be left running during normal
operation. It can be turned off during Sleep Mode to save
power, but this is not required. The CLK input can be driven
with 5V logic, regardless of the DVDD or AVDD voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be generated
from a number of sources including stand-alone crystal
oscillators and microcontrollers. The MSP430, an ultra low
power microcontroller, is especially well-suited for this
task. Using the MSP430 FLL clock generator available on
the 4xx family, it is easy to produce a 2.4576MHz clock
from a 32.768kHz crystal.
DATA READY/DATA OUTPUT (DRDY/DOUT)
The digital output pin on the ADS1245 serves two
purposes. It indicates when new data is ready by going
low. Afterwards, on the first rising edge of SCLK, the
DRDY
/DOUT pin changes function and begins outputting
the conversion data, MSB first. Data is shifted out on each
subsequent SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an additional
SCLK. It will then stay high until new data is ready. This is
useful when polling on the status of DRDY
/DOUT to
determine when to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V logic
regardless of the DVDD or AVDD voltage. There is
hysteresis built into this input, but care should still be taken
to ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason, it
is best to make sure the rise-and-fall times of SCLK are
less than 50ns.
FREQUENCY RESPONSE
The ADS1245 frequency response for fCLK = 2.4576MHz
is shown in Figure 18. The frequency response repeats at
multiples of 19.2kHz. The overall response is that of a
low-pass filter with a –3dB cutoff frequency of 13.7Hz. As
can be seen, the ADS1245 does a good job attenuating out
to 19kHz. For the best resolution, limit the input bandwidth
to below this value to keep higher frequency noise from
affecting performance. Often, a simple RC filter on the
ADS1245 analog inputs is all that is needed.
0
−
20
−
40
−
60
−
80
Gain (dB)
−
100
−
120
−
140
9.6 19.20
Frequency (kHz)
Figure 18. Frequency Response
f
= 2.4576MHz
CLK
8
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"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
To help see the response at lower frequencies, Figure 19
illustrates the response out to 180Hz. Notice that both
50Hz and 60Hz signals are rejected. This feature is very
useful for eliminating power line cycle interference during
measurements. Figure 20 shows the ADS1245 response
around these frequencies.
0
−
20
f
100
CLK
110
= 2.4576MHz
120
130
140
150
160
170
180
−
40
−
60
−
80
−
100
Gain (dB)
−
120
−
140
−
160
−
180
0
102030405060708090
Frequency (Hz)
Figure 19. Frequency Response to 180Hz
The ADS1245 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2.4576MHz to 4.9152MHz, the data rate
increases from 15sps to 30sps while the notches in the
response at 50Hz and 60Hz move out to 100Hz and
120Hz.
SETTLING TIME
The ADS1245 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving
the data when there is a change on the analog inputs.
In order to realize single-cycle settling, synchronize
changes on the analog inputs to the conversion beginning,
which is indicated by the falling edge of DRDY
example, when using a multiplexer in front of the
ADS1245, change the multiplexer inputs when
DRDY
/DOUT goes low. Increasing the time between the
conversion beginning and the change on the analog inputs
(t
) results in a settling error in the conversion data, as
DELAY
shown in Figure 21. The settling error versus delay time is
shown in Figure 22. If the input change is delayed to the
point where the settling error is too high, simply ignore the
first data result and wait for the second conversion, which
will be fully settled.
/DOUT . F o r
−
40
−
50
f
= 2.4576MHz
−
60
−
70
−
80
Gain (dB)
−
90
−
100
−
110
−
120
50 55 60 6545
Frequency (Hz)
CLK
Figure 20. Frequency Response Near
50Hz and 60Hz
10.000000
1.000 000
0.100 000
f
= 2.4576MHz
DELAY
CLK
(ms)
0.010 000
0.001 000
Settling Error (%)
0.000 100
0.000 010
0.000 001
2 4 6 8 101214160
Delay Time, t
Figure 21. Settling Error vs Delay Time
9
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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DRDY/DOUT
V
Begin New Conversion,
Complete Previous Conversion
IN
t
DELAY
Previous Conversion Data
Figure 22. Analog Input Change Timing
POWER−UP
Self-calibration is performed at power-up to minimize offset
and gain errors. In order for the self-calibration at power-up to
work properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t
SCLK must be held low during this time. Once calibration
is complete, DRDY
/DOUT goes low, indicating data is
, as shown in Figure 23.
1
NewConversion Complete
ready for retrieval. The time required before the first data
is ready (t
to their final value (t
(f
CLK
) depends on how fast AVDD and DVDD ramp
6
). For most ramp rates, t
1
+ t2 ≈ 350ms
1
= 2.4576MHz). If the system environment is not stable
during power-up (the temperature is varying or the supply
voltages are moving around), it is recommended that a
self-calibration be issued after everything is stable.
AVDD and DVDD
DRDY/DOUT
SCLK
Data ready after power−up calibration.
t
1
t
2
SYMBOL DESCRIPTION MIN MAX UNITS
(1)
t
1
(1)
t
2
NOTE: (1) Values given for f
scale proportional to CLK period.
AVDD and DVDD settling time.
Wait time for calibration and first data
conversion.
= 2.4576MHz. For different CLK frequencies,
CLK
316
100 ms
ms
Figure 23. Power-Up Timing
10
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"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
DATA FORMAT
The ADS1245 outputs 24 bits of data in Binary Two’s
Complement format. The least significant bit (LSB) has a
weight of (2V
produces an output code of 7FFFFFh and the negative
full-scale input produces an output code of 8000000h. The
output clips at these codes for signals exceeding
full-scale. Table 1 summarizes the ideal output codes for
different input signals.
Table 1. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE
v*2V
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
)/(223 − 1). A positive full-scale input
REF
≥ +2V
) 2V
23)
(2
* 2V
23)
(2
REF
* 1
0
* 1
REF
REF
REF
ǒ
(2
23)
2
23
* 1
Ǔ
7FFFFF
000001
000000
FFFFFF
800000
(1)
H
H
H
H
H
DATA RETRIEVAL
The ADS1245 continuously converts the analog input
signal. To retrieve data, wait until DRDY
as shown in Figure 24. After this occurs, begin shifting out
the data by applying SCLKs. Data is shifted out most
significant bit (MSB) first. It is not required to shift out all the
24 bits of data, but the data must be retrieved before the
new data is updated (see t
) or else it will be overwritten.
3
Avoid data retrieval during the update period.
DRDY
/DOUT remains at the state of the last bit shifted out
until it is taken high (see t
), indicating that new data is
7
being updated.
To avoid having DRDY
/DOUT remain in the state of the
last bit, shift a 25th SCLK to force DRDY
Figure 25. This technique is useful when a host controlling
the ADS1245 is polling DRDY
/DOUT to determine when
data is ready.
/DOUT goes low,
/DOUT high; see
Data is ready.
DRDY/DOU T 23 22 21
t
t
3
SCLK
SYMBOL DESCRIPTION MIN MAX UNITS
t
3
t
4
(1)
t5
t
6
t
7
(2)
t
8
NOTES:
DRDY/DOUT low to first SCLK rising edge.
SCLK positive or negative pulse width.
SCLK rising edge to new data bit valid;
propagation delay.
SCLK rising edge to old data bit valid: hold time.
Data updating, no read back allowed.
Conversion time (1/data rate).
(1) Load on DRDY/DOUT = 20pF||100kΩ.
(2) Values given for f
proportional to CLK period. For example, for f
5
124
= 2.4576MHz. For different CLK frequencies, scale
CLK
Data
t
4
New data is ready.
LSBMSB
0
t
6
t
4
t
8
0
100
50
0
152
66.667
= 4.9152MHz, t8→33.333ms.
CLK
152
66.667
ns
ns
ns
ns
µs
ms
t
7
Figure 24. Data Retrieval Timing
11
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
Data is ready. New data is ready.
www.ti.com
Data
DRDY/DOUT
SCLK
23
22 21 0
12425
25th SCLK to force DRDY/DOUT
Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards
SELF-CALIBRATION
The user can initiate self-calibration at any time, though i n
many applications the ADS1245 drift performance is good
enough that the self-calibration performing automatically
at power-up is all that is needed. To initiate a
self-calibration, apply at least two additional SCLKs after
retrieving 24 bits of data. Figure 26 shows the timing
pattern. The 25th SCLK will send DRDY
falling edge of the 26th SCLK will begin the calibration
cycle. Additional SCLK pulses may be sent after the 26th
SCLK, but minimizing activity on SCLK during calibration
provides best results.
/DOUT high. The
high
When the calibration is complete, DRDY
/DOUT will go
low, indicating that new data is ready. There is no need to
alter the analog input signal applied to the ADS1245 during
calibration; the inputs pins are disconnected within the
ADC and the appropriate signals are automatically applied
internally. The first conversion after a calibration is fully
settled and va l i d f o r u s e . T h e t i m e r e q u i r e d f o r a c a l i b r a t i o n
depends on two independent signals: the falling edge of
SCLK and an internal clock derived from CLK. Variations
in the internal calibration values will change the time
required for calibration (t
MIN/MAX specs. t
12
) within the range given by the
9
and t
described in the next section
13
are likewise affected.
SCLK
23DRDY/DOUT
124
SYMBOL DESCRIPTION MIN MAX UNITS
(1)
t
9
NOTE: (1) Values given for f
scale proportional to CLK period.
First data ready after calibration.
= 2.4576MHz. For different CLK frequencies,
CLK
Cal begins
25 26
209 210
t
9
ms
Figure 26. Self-Calibration Timing
Data ready after calibration
2322 21 0
12
www.ti.com
"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
SLEEP MODE
Sleep mode dramatically reduces power consumption
(typically < 1µW with CLK stopped) by shutting down all of
the active circuitry. To enter Sleep mode, simply hold
SCLK high after DRDY
Figure 27. Sleep Mode can be initiated at any time during
read-back; it is not necessary to retrieve all 24 bits of data
beforehand. Once t
Sleep mode will activate. DRDY
Sleep mode begins. SCLK must remain high to stay in
Sleep mode. To exit Sleep mode (wakeup), set SCLK low.
The first data after exiting Sleep Mode is valid. It is not
necessary to stop CLK during Sleep mode, but doing so
will further reduce the digital supply current.
DRDY/DOUT 23 22 21
SCLK
/DOUT goes low, as shown in
11 has passed with SCLK held high,
/DOUT stays high once
124
t
10
t
11
Sleep Mode with Self-Calibration
Self-calibration can be set to run immediately after exiting
Sleep mode. This is useful when the ADS1245 is put in
Sleep mode for long periods of time and self-calibration is
desired afterwards to compensate for temperature or
supply voltage changes.
To force a self-calibration with Sleep mode, shift 25 bits out
before taking SCLK high to enter Sleep mode.
Self-calibration begins after wakeup. Figure 28 shows the
appropriate timing. Note the extra time needed after
wakeup for calibration before data is ready. The first data
after Sleep mode with self-calibration is fully settled and
can be used.
Sleep Mode
023
Data ready after wakeup
Wakeup
t
12
SYMBOL DESCRIPTION MIN MAX UNITS
(1)
t
10
(1)
t11
(1)
t
12
NOTES: (1) V alues given for f
CLK period.
Figure 27. Sleep-Mode Timing; Can Be Used for SIngle Conversions
DRDY/DOUT 23
SCLK
12425
SYMBOL DESCRIPTION MIN MAX UNITS
(1)
t
13
NOTE: (1) Values given for f
proportional to CLK period.
SCLK HIGH after DRDY/DOUT goes low to activate Sleep
Mode.
Sleep Mode activation time.
Data ready after wakeup.
= 2.4576MHz. For different CLK frequencies, scale proportional to
CLK
SleepMode
22 21 0 23
t
11
Data ready after wakeup and calibration.
= 2.4576MHz. For different CLK frequencies, scale
CLK
0
63.7
66.57166.5
Data ready after wakeup and calibration
Wakeup and begin cal.
t
13
210 211
72
ms
ms
ms
ms
Figure 28. Sleep-Mode with Self-Calibration on Wakeup Timing; Can Be Used for SIngle Conversions
13
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
www.ti.com
SINGLE CONVERSIONS
When only single conversions are needed, Sleep mode
can be used to start and stop the ADS1245. To make a
single conversion, first enter the Sleep Mode holding
SCLK high. Now, when ready to start the conversion, take
SCLK low. The ADS1245 will wake up and begin the
conversion. Wait for DRDY
/DOUT to go low, and then
retrieve the data. Afterwards, take SCLK high to stop the
ADS1245 from converting and re−enter Sleep mode.
Continue to hold SCLK high until ready to start the next
conversion. Operating in this fashion greatly reduces
power consumption since the ADS1245 is shut down while
idle between conversions. Self−calibrations can be
performed prior to the start of the single conversions by
using the waveform shown in Figure 28.
SINGLE-SUPPLY OPERATION
It is possible to operate the ADS1245 with a single supply.
For a 3V supply, simply connect AVDD and DVDD
together. Figure 29 shows an example of the ADS1245
running on a single 5V supply. An external resistor, R
used to drop 5V supply down to a desired voltage level of
DVDD. For example, if the desired DVDD supply voltage
is 3V and AVDD is 5V, the value of R
should be:
1
R1+ (5V* 3V)ń5mA [ 400kW
where 5mA is a typical digital current consumption when
DVDD = 3V (refer to the typical characteristic Digital
Current vs Digital Supply). A buffer on DRDY/DOUT can
provide level−shifting if required.
DVDD can be set to a desired voltage by choosing a proper
value of R
, but keep in mind that DVDD must be set
1
between 1.8V and 3.6V. Note that the maximum logic high
output of DRDY
/DOUT is equal to DVDD, but both CLK
and SCLK inputs can be driven with 5V logic regardless of
the DVDD or AVDD voltage. Use 0.1mF capacitors to
bypass both AVDD and DVDD.
1
(1)
, is
to + 5V logic
SN74L VC C3 245A
from
+5V logic
109876
CLK SCLK DRDY/DOUT DV DD AVDD
GND VREFP VRE FN AINN A INP
12345
from
+5V logic
ADS1245
0.1µF
++
+5V
0.1µF
R
1
Figure 29. Example of the ADS1244 Running on a
Single 5V Supply
MULTI-CHANNEL SYSTEMS
Multiple ADS1245s can be operated in parallel to measure
multiple input signals. Figure 30 shows an example of a
two-channel system. For simplicity, the supplies and
reference circuitry were not included. The same CLK
signal should be applied to all devices. To be able to
synchronize the ADS1245s, connect the same SCLK
signal to all devices as well. When ready to synchronize,
place all the devices in Sleep mode. Afterwards, a wakeup
command will synchronize all the ADS1245s; that is, they
will sample the input signals simultaneously
The DRDY
same time after synchronization. The falling edges,
indicating that new data is ready, will vary with respect to
each other no more than timing specification t
variation is due to possible differences in the ADS1245
internal calibration settings. To account for this when using
multiple devices, either wait for t
device DRDY
have gone low before retrieving data.
/DOUT outputs will go low at approximately the
14. This
14 to pass after seeing one
/DOUT go low, or wait until all DRDY/DOUTs
14
www.ti.com
IN1
IN2
1
2
3
4
5
1
2
3
4
5
GND
VREFP
VREFN
AINN
AINP
GND
VREFP
VREFN
AINN
AINP
ADS1245
DRDY/DOUT
ADS1245
DRDY/DOUT
CLK
SCLK
DVDD
AVDD
CLK
SCLK
DVDD
AVDD
10
9
8
7
6
10
9
8
7
6
CLK and SCLK
Sources
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
OUT1
OUT2
OUT1
t
14
OUT2
SYMBOL
t
14
DESCRIPTION MIN
Difference between DRDY/
DOUTs going low in
MAX UNITS
± 500 µs
multichannel systems.
Figure 30. Example of Using Multiple ADS1245s in Parallel
15
"#$%&
SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
SUMMARY OF SERIAL INTERFACE WAVEFORMS
www.ti.com
DRDY/DOUT
SCLK
DRDY/DOUT
SCLK
D
RDY/DOUT
SCLK
23 22 21 0
MSB LSB
124
a. Data Retrieval
23 22 21 0
12425
b. Data Retrieval with DRDY/DOUT Forced High Afterwards
23 22 21 0
1242526
Begin calibration
c. Self-Calibration
Data ready after calibration
DRDY/DOUT
SCLK
DRDY/DOUT
SCLK
Data ready
Sleep Mode
23 22 21 0
Wakeup and
start conversion
124
d. Sleep Mode/Single Conversions
Data ready after
wakeup and calibration
Sleep Mode
23 22 21 0
Wakeup and
begin cal.
12425
e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup
Figure 31. Summary of Serial Interface Waveforms
16
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
ADS1245IDGSR ACTIVE MSOP DGS 10 2500 TBD Call TI Call TI
ADS1245IDGST ACTIVE MSOP DGS 10 250 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(2)
Lead/Ball Finish MSL Peak Temp
(3)
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