TEXAS INSTRUMENTS ADS1242, ADS1243 Technical data

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ANALOG-TO-DIGITAL CONVERTER

24-Bit

ADS1242

A

®

D

S

A

1

2

D

4

2

®

S

1

2

4

3

ADS1243

SBAS235B – DECEMBER 2001 – OCTOBER 2004

FEATURES

● 24 BITS NO MISSING CODES

● SIMULTANEOUS 50Hz AND 60Hz REJECTION

(–90dB MINIMUM)

● 0.0015% INL

● 21 BITS EFFECTIVE RESOLUTION

(PGA = 1), 19 BITS (PGA = 128)

● PGA GAINS FROM 1 TO 128

● SINGLE-CYCLE SETTLING

● PROGRAMMABLE DATA OUTPUT RATES

● EXTERNAL DIFFERENTIAL REFERENCE

OF 0.1V TO 5V

● ON-CHIP CALIBRATION

● SPI™ COMPATIBLE

● 2.7V TO 5.25V SUPPLY RANGE

● 600µW POWER CONSUMPTION

● UP TO EIGHT INPUT CHANNELS

● UP TO EIGHT DATA I/O

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● LIQUID / GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTATION

● WEIGHT SCALES

V

DD

2µA

DESCRIPTION

The ADS1242 and ADS1243 are precision, wide dynamic
range, delta-sigma, analog-to-digital (A/D) converters with
24-bit resolution operating from 2.7V to 5.25V supplies.
These delta-sigma, A/D converters provide up to 24 bits of no
missing code performance and effective resolution of 21 bits.

The input channels are multiplexed. Internal buffering can be
selected to provide a very high input impedance for direct
connection to transducers or low-level voltage signals. Burn­out current sources are provided that allow for the detection
of an open or shorted sensor. An 8-bit digital-to-analog
converter (DAC) pr o vides an offset correction with a range of
50% of the FSR (Full-Scale Range).

The Programmable Gain Amplifier (PGA) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a second-order
delta-sigma modulator and programmable FIR filter that pro­vides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.

The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1242 and ADS1243 are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weight scales, chromatography, and portable
instrumentation.

V

DD

Offset

DAC

V

REF+VREF–

X

X

IN

OUT

Clock Generator

0/D0

A

IN

1/D1

A

IN

A

2/D2

IN

3/D3

A

IN

4/D4

A

IN

5/D5

A

IN

6/D6

A

IN

A

7/D7

IN

ADS1243

Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

IN+

MUX

IN–

2µA

GND

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A = 1:128

+

BUF PGA

GND

2nd-Order
Modulator

Digital

PDWN DRDY

Filter

Controller Registers

Serial Interface

Copyright © 2001-2004, Texas Instruments Incorporated

SCLK
D

IN

D

OUT

CS

ABSOLUTE MAXIMUM RATINGS

VDD to GND ........................................................................... –0.3V to +6V

Input Current ............................................................... 100mA, Momentary

Input Current .................................................................10mA, Continuous

A

.................................................................... GND – 0.5V to VDD + 0.5V

IN

Digital Input Voltage to GND...................................... –0.3V to V

Digital Output Voltage to GND ................................... –0.3V to V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –60°C to +100°C

Lead Temperature (soldering, 10s) .............................................. +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

(1)

+ 0.3V

DD

+ 0.3V

DD

DEMO BOARD ORDERING INFORMATION

PRODUCT DESCRIPTION

ADS1241-EVM ADS1241 Evaluation Module

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER

ADS1242 TSSOP-16 PW –40°C to +85°C ADS1242 ADS1242IPWT Tape and Reel, 250

(1)

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

SPECIFIED

(2)

MEDIA, QUANTITY

" """"ADS1242IPWR Tape and Reel, 2500

ADS1243 TSSOP-20 PW –40°C to +85°C ADS1243 ADS1243IPWT Tape and Reel, 250

" """"ADS1243IPWR Tape and Reel, 2500

NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

(2) The ordering number contains grade, temperature range, package, and transport media information. Ordering the ADS1242IPWT will get a single

250-piece tape and reel of the ADS1242, Industrial Temperature Range device in a PW package.

DIGITAL CHARACTERISTICS: T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Input/Output
Logic Family CMOS
Logic Level: V

Input Leakage: I

Master Clock Rate: f
Master Clock Period: t

NOTE: (1) V

IH

(1)

V

IL

V

OH

V

OL

IH

I

IL

OSC

OSC

for XIN is GND to GND + 0.05V.

IL

MIN

to T

, VDD 2.7V to 5.25V

MAX

0.8 • V

DD

IOH = 1mA VDD – 0.4 V
IOL = 1mA GND GND + 0.4 V

VI = V

DD

VI = 0 –10 µA

1/f

OSC

GND 0.2 • V

15MHz

200 1000 ns

V

DD

10 µA

V

DD

V

2

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ADS1242, 1243

SBAS235B

ELECTRICAL CHARACTERISTICS: VDD = 5V

All specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT

Analog Input Range Buffer OFF GND – 0.1 V

Full-Scale Input Range

Differential Input Impedance Buffer OFF 5/PGA MΩ

Bandwidth

f

= 3.75Hz –3dB 1.65 Hz

DATA

f

= 7.50Hz –3dB 3.44 Hz

DATA

f

= 15.00Hz –3dB 14.6 Hz

DATA

Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA

OFFSET DAC

Offset DAC Range RANGE = 0 ±V

Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C

SYSTEM PERFORMANCE

Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection at DC 100 dB

Normal-Mode Rejection f

Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V

VOLTAGE REFERENCE INPUT

Reference Input Range REF IN+, REF IN– 0V
V

REF

Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage V
Current PGA = 1, Buffer OFF 240 375 µA

Power Dissipation PGA = 1, Buffer OFF 1.2 1.9 mW

TEMPERATURE RANGE

Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) Calibration can minimize these errors. (2) ∆V

(1)
(1)
(1)

(3)

to T

MIN

(AIN0 – AIN7)

(1)

, VDD = +5V, f

MAX

= 19.2kHz, PGA = 1, Buffer ON, f

MOD

DATA

Buffer ON GND + 0.05 V

(In+) – (In–), See Block Diagram, RANGE = 0

RANGE = 1

Buffer ON 5 GΩ

RANGE = 1 ±V

f

= 60Hz, f

CM

f

= 50Hz, f

CM

= 50Hz, f

SIG

f

= 60Hz, f

SIG

V

≡ (REF IN+) – (REF IN–), RANGE = 0

REF

RANGE = 1 0.1 V

= 60Hz, f

VREFCM

V

REF

= 15Hz 130 dB

DATA

= 15Hz 120 dB

DATA

= 15Hz 100 dB

DATA

= 15Hz 100 dB

DATA

(2)

)

OUT/VDD

= 15Hz 120 dB

DATA

= 2.5V 1.3 µA

DD

PGA = 128, Buffer OFF 450 800 µA

PGA = 1, Buffer ON 290 425 µA

PGA = 128, Buffer ON 960 1400 µA

SLEEP Mode 60 µA

Read Data Continuous Mode

PDWN 0.5 nA

is a change in digital result. (3) 12pF switched capacitor at f

OUT

= 15Hz, V

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

ADS1242
ADS1243

+ 0.1 V

DD

– 1.5 V

DD

±V

REF

±V

/(2 • PGA)

REF

/(2 • PGA) V

REF

/(4 • PGA) V

REF

7.5 ppm of FS

0.02 ppm of FS/°C

0.005 %

0.5 ppm/°C

80 95 dB

0.1 2.5 2.6 V

DD

DD

4.75 5.25 V

230 µA

clock frequency.

SAMP

/PGA V

V

V

V

ADS1242, 1243

SBAS235B

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3

ELECTRICAL CHARACTERISTICS: VDD = 3V

All specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT

Analog Input Range Buffer OFF GND – 0.1 V

Full-Scale Input Voltage Range

Input Impedance Buffer OFF 5/PGA MΩ

Bandwidth

f

= 3.75Hz –3dB 1.65 Hz

DATA

f

= 7.50Hz –3dB 3.44 Hz

DATA

f

= 15.00Hz –3dB 14.6 Hz

DATA

Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA

OFFSET DAC

Offset DAC Range RANGE = 0 ±V

Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C

SYSTEM PERFORMANCE

Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection at DC 100 dB

Normal-Mode Rejection f

Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V

VOLTAGE REFERENCE INPUT

Reference Input Range REF IN+, REF IN– 0V
V

REF

Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage V
Current PGA = 1, Buffer OFF 190 375 µA

Power Dissipation PGA = 1, Buffer OFF 0.6 1.2 mW

TEMPERATURE RANGE

Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) Calibration can minimize these errors. (2) ∆V

(1)

(1)

(1)

(3)

to T

MIN

(AIN0 – AIN7)

(1)

, VDD = +3V, f

MAX

= 19.2kHz, PGA = 1, Buffer ON, f

MOD

DATA

Buffer ON GND + 0.05 V

(In+) – (In–) See Block Diagram, RANGE = 0

RANGE = 1

Buffer ON 5 GΩ

RANGE = 1 ±V

f

= 60Hz, f

CM

f

= 50Hz, f

CM

= 50Hz, f

SIG

f

= 60Hz, f

SIG

V

≡ (REF IN+) – (REF IN–), RANGE = 0

REF

RANGE = 1 0.1 2.5 2.6 V

= 60Hz, f

VREFCM

V

REF

= 15Hz 130 dB

DATA

= 15Hz 120 dB

DATA

= 15Hz 100 dB

DATA

= 15Hz 100 dB

DATA

(2)

)

OUT/VDD

= 15Hz 120 dB

DATA

= 1.25 0.65 µA

DD

PGA = 128, Buffer OFF 460 700 µA

PGA = 1, Buffer ON 240 375 µA

PGA = 128, Buffer ON 870 1325 µA

SLEEP Mode 75 µA

Read Data Continuous Mode

PDWN = 0 0.5 nA

is a change in digital result. (3) 12pF switched capacitor at f

OUT

= 15Hz, V

≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise specified.

REF

ADS1242
ADS1243

+ 0.1 V

DD

– 1.5 V

DD

±V

/PGA V

REF

±V

/(2 • PGA)

REF

/(2 • PGA) V

REF

/(4 • PGA) V

REF

15 ppm of FS

0.04 ppm of FS/°C

0.01 %

1.0 ppm/°C

75 90 dB

0.1 1.25 1.30 V

DD

2.7 3.3 V

113 µA

clock frequency.

SAMP

V

V

4

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ADS1242, 1243

SBAS235B

PIN CONFIGURATION (ADS1242)

PIN CONFIGURATION (ADS1243)

Top View TSSOP Top View TSSOP

V

X

X

OUT

PDWN

V

REF+

V

REF–

AIN0/D0
A

1/D1

IN

1

DD

2

IN

3
4

ADS1242

5
6
7
8

16

DRDY

15

SCLK

14

D

OUT

13

D

IN

12

CS

11

GND

10

A

3/D3

IN

9

A

2/D2

IN

PIN DESCRIPTIONS (ADS1242)

PIN

NUMBER NAME DESCRIPTION

1V
2X
3X

4 PDWN Active LOW. Power Down. The power down func-

5V
6V
7A
8A
9A

10 A

REF+

REF–
IN
IN
IN
IN

11 GND Ground
12 CS Active LOW, Chip Select
13 D
14 D
15 SCLK Serial Clock, Schmitt Trigger
16 DRDY Active LOW, Data Ready

Power Supply

DD

Clock Input

IN

Clock Output, used with crystal or ceramic

OUT

resonator.

tion shuts down the analog and digital circuits.
Positive Differential Reference Input

Negative Differential Reference Input
0/D0 Analog Input 0/Data I/O 0
1/D1 Analog Input 1/Data I/O 1
2/D2 Analog Input 2/Data I/O 2
3/D3 Analog Input 3/Data I/O 3

Serial Data Input, Schmitt Trigger

IN

Serial Data Output

OUT

V

X

X

OUT

PDWN

V

REF+

V

REF–

AIN0/D0
A

1/D1

IN

A

4/D4

IN

A

5/D5

IN

1

DD

2

IN

3
4
5

ADS1243

6
7
8
9

10

20

DRDY

19

SCLK

18

D

OUT

17

D

IN

16

CS

15

GND

14

A

3/D3

IN

13

A

2/D2

IN

12

A

7/D7

IN

11

A

6/D6

IN

PIN DESCRIPTIONS (ADS1243)

PIN

NUMBER NAME DESCRIPTION

1V
2X
3X

OUT

4 PDWN Active LOW. Power Down. The power down func-

5V
6V
7A
8A

9A
10 A
11 A
12 A
13 A
14 A
15 GND Ground

REF+

REF–
IN
IN
IN
IN
IN
IN
IN
IN

16 CS Active LOW, Chip Select
17 D
18 D
19 SCLK Serial Clock, Schmitt Trigger
20 DRDY Active LOW, Data Ready

Power Supply

DD

Clock Input

IN

Clock Output, used with crystal or ceramic
resonator.

tion shuts down the analog and digital circuits.
Positive Differential Reference Input

Negative Differential Reference Input
0/D0 Analog Input 0/Data I/O 0
1/D1 Analog Input 1/Data I/O 1
4/D4 Analog Input 4/Data I/O 4
5/D5 Analog Input 5/Data I/O 5
6/D6 Analog Input 6/Data I/O 6
7/D7 Analog Input 7/Data I/O 7
2/D2 Analog Input 2/Data I/O 2
3/D3 Analog Input 3/Data I/O 3

Serial Data Input, Schmitt Trigger

IN

Serial Data Output

OUT

ADS1242, 1243

SBAS235B

www.ti.com

5

TIMING DIAGRAMS

CS

SCLK

(POL = 0)

D

IN

t

3

t

4

MSB

t

1

t

5

t

2

t

6

t

2

t

10

t

11

LSB

DIAGRAM 1.

DIAGRAM 2.

D

OUT

NOTE: (1) Bit order = 0.

SCLK Reset Waveform

SCLK

DRDY

SCLK

(Command or Command and Data)

t

13

t

12

t

17

t

19

t

DATA

t

14

t

7

MSB

t

8

(1)

LSB

t

9

(1)

ADS1242 or ADS1243

Resets On

t

Falling Edge

13

t

15

t

18

300 • t
t13 : > 5 • t
550 • t
1050 • t

PDWN

< t12 < 500 • t

OSC

OSC

< t14 < 750 • t

OSC

< t15 < 1250 • t

OSC

OSC

OSC

OSC

t

16

TIMING CHARACTERISTICS TABLES

SPEC DESCRIPTION MIN MAX UNITS

t

1

t

2

t

3

t

4

t

5

t

6

(1)

t

7

(1)

t

8

t

9

t

10

t

11

t

16

t

17

t

18

t

19

NOTES: (1) Load = 20pF 10kΩ to GND.

SCLK Period 4t

3 DRDY Periods
SCLK Pulse Width, HIGH and LOW 200 ns
CS low to first SCLK Edge; Setup Time

(2)

0ns
DIN Valid to SCLK Edge; Setup Time 50 ns
Valid DIN to SCLK Edge; Hold Time 50 ns
Delay between last SCLK edge for DIN and first SCLK edge for D

OUT

:

RDATA, RDATAC, RREG, WREG 50 t

SCLK Edge to Valid New D
SCLK Edge to D
Last SCLK Edge to D
NOTE: D

OUT

, Hold Time 0 ns

OUT

Tri-State 6 10 t

OUT

goes tri-state immediately when CS goes HIGH.

OUT

50 ns

CS LOW time after final SCLK edge. 0 ns
Final SCLK edge of one command until first edge SCLK

of next command:

RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC

4t

SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods
SELFCAL 4 DRDY Periods

RESET (also SCLK Reset) 16 t
Pulse Width 4t
Allowed analog input change for next valid conversion. 5000 t
DOR update, DOR data not valid. 4 t
First SCLK after DRDY goes LOW:

RDATAC Mode 10 t

Any other mode 0 t

(2) CS may be tied LOW.

OSC

OSC

OSC

OSC

OSC
OSC
OSC
OSC

OSC
OSC

Periods

Periods

Periods

Periods

Periods
Periods
Periods
Periods

Periods
Periods

6

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ADS1242, 1243

SBAS235B

TYPICAL CHARACTERISTICS

POWER SUPPLY REJECTION RATIO

vs FREQUENCY

Frequency of Power Supply (Hz)

110 1k100 10k 100k

PSRR (dB)

140

120

100

80

60

40

20

0

Buffer ON

All specifications, VDD = +5V, f

= 2.4576MHz, PGA = 1, f

OSC

= 15Hz, and V

DATA

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

21.5

21.0

20.5

20.0

19.5

19.0

ENOB (rms)

18.5

18.0
Buffer OFF

17.5

17.0

20.5

20.0

19.5

19.0

18.5

18.0

ENOB (rms)

17.5

17.0

16.5

16.0

EFFECTIVE NUMBER OF BITS vs PGA SETTING

DR = 10

DR = 01

DR = 00

1 2 4 8 16 1286432

PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING

DR = 10

DR = 01

DR = 00

Buffer OFF, V

1 2 4 8 16 64 12832

REF

= 1.25V

PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING

22

21

DR = 00

PGA Setting

V

IN

DR = 10

DR = 01

(V)

20

19

18

ENOB (rms)

17

Buffer ON

16

15

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

Noise (rms, ppm of FS)

0.4

0.2

1 2 4 8 16 1286432

NOISE vs INPUT SIGNAL

0

–2.5 –1.5 0.5–0.5 1.5 2.5

COMMON-MODE REJECTION RATIO

140

120

100

80

60

CMRR (dB)

40

20

Buffer ON

0

1 10 100 1k 10k 100k

Frequency of Power Supply (Hz)

ADS1242, 1243

SBAS235B

vs FREQUENCY

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7

TYPICAL CHARACTERISTICS (Cont.)

All specifications, VDD = +5V, f

= 2.4576MHz, PGA = 1, f

OSC

= 15Hz, and V

DATA

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

OFFSET vs TEMPERATURE

50

PGA1

0

–50

–100

Offset (ppm of FS)

–150

–200

–50 –30 10–10 30 50 70 90

10

8
6
4
2
0

–2

INL (ppm of FS)

–4
–6
–8

–10

–2.5 –2.0 –1.0 –0.5–1.5 0 0.5 1.0 1.5 2.0 2.5

PGA128

INTEGRAL NONLINEARITY vs INPUT SIGNAL

+85°C

(Cal at 25°C)

PGA64

Temperature (°C)

–40°C

V

(V)

IN

+25°C

PGA16

1.00010

1.00006

1.00002

0.99998

0.99994

Gain (Normalized)

0.99990

0.99986
–50 –30 10–10 30 50 70 90

260

250

240

230

220

Current (µA)

210

200

190

–50 –30 10–10 30 50 70 90

GAIN vs TEMPERATURE

(Cal at 25°C)

Temperature (°C)

CURRENT vs TEMPERATURE

(Buffer Off)

Temperature (°C)

350
300
250
200
150

Current (µA)

100

50

0

–50

3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0

8

CURRENT vs VOLTAGE

Normal

4.91MHz

SLEEP

4.91MHz

Normal

2.45MHz

(V)

V

DD

SLEEP

2.45MHz

Power Down

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300

250

200

(µA)

DIGITAL

I

4.91MHz

150

100

50

0

3.0 3.5 4.0 4.5 5.0

SUPPLY CURRENT vs SUPPLY

SLEEP

Power Down

Normal

4.91MHz

(V)

V

DD

Normal

2.45MHz

SLEEP

2.45MHz

ADS1242, 1243

SBAS235B