TEXAS INSTRUMENTS ADS1240, ADS1241 Technical data

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A

D

S

1

2

4

0

ADS1240

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS NO MISSING CODES

● SIMULTANEOUS 50Hz AND 60Hz REJECTION

(–90dB MINIMUM)

● 0.0015% INL

● 21 BITS EFFECTIVE RESOLUTION

(PGA = 1), 19 BITS (PGA = 128)

● PGA GAINS FROM 1 TO 128

● SINGLE CYCLE SETTLING

● PROGRAMMABLE DATA OUTPUT RATES

● EXTERNAL DIFFERENTIAL REFERENCE

OF 0.1V TO 5V

● ON-CHIP CALIBRATION

● SPI™ COMPATIBLE

● 2.7V TO 5.25V SUPPLY RANGE

● 600µW POWER CONSUMPTION

● UP TO EIGHT INPUT CHANNELS

● UP TO EIGHT DATA I/O

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● WEIGH SCALES

● LIQUID / GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTATION

AV

24-Bit

DESCRIPTION

The ADS1240 and ADS1241 are precision, wide dynamic range, delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution operating from 2.7V to 5.25V power supplies. The delta-sigma A/D converter provides up to 24 bits of no missing code performance and effective resolution of 21 bits.

The input channels are multiplexed. Internal buffering can be selected to provide very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/A) converter provides an offset correction with a range of 50% of the Full-Scale Range (FSR).

The Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128, with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a 2nd-order delta-sigma modulator and programmable Finite-Impulse Response (FIR) filter that provides a simultaneous 50Hz and 60Hz notch. The reference input is differential and can be used for ratiometric conversion.

The serial interface is SPI compatible. Up to eight bits of data I/O are also provided that can be used for input or output. The ADS1240 and ADS1241 are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation.

AGNDAV

DD

2µA

A

D

S

1

2

4

1

SBAS173C – JUNE 2001 – REVISED NOVEMBER 2003

V

REF+VREF–

Offset

DAC

ADS1241

X

IN

OUT

Clock Generator

0/D0

A

IN

1/D1

A

IN

2/D2

A

IN

3/D3

A

IN

4/D4

A

IN

5/D5

A

IN

6/D6

A

IN

7/D7

A

IN

A

INCOM

ADS1241

Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

MUX

2µA

AGND

www.ti.com

A = 1:128

BUF PGA

+

2nd-Order Modulator

DD

Digital

Filter

Controller Registers

Serial Interface

DSYNCPDWN RESET DRDYBUFEN DGNDDV

POL SCLK D

IN

D

OUT

CS

ABSOLUTE MAXIMUM RATINGS

AVDD to DGND ...................................................................... –0.3V to +6V

DV

to DGND...................................................................... –0.3V to +6V

DD

Input Current ............................................................... 100mA, Momentary

DGND to AGND ....................................................................–0.3V to 0.3V

Input Current ................................................................. 10mA, Continuous

A

.................................................................AGND –0.5V to AVDD + 0.5V

IN

Digital Input Voltage to DGND ................................. –0.3V to DV

Digital Output Voltage to DGND ..............................–0.3V to DV

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –60°C to +150°C

Lead Temperature (soldering, 10s) .............................................. +300°C

NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.

(1)

DD DD

+ 0.3V + 0.3V

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

EVALUATION MODULE ORDERING INFORMATION

PRODUCT DESCRIPTION

ADS1241EVM ADS1240 and ADS1241 Evaluation Module

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE-LEAD DESIGNATOR

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

ADS1240 SSOP-24 DB –40°C to +85°C ADS1240E ADS1240E Rails, 60

(1)

"" " ""ADS1240E/1K Tape and Reel, 1000

ADS1241 SSOP-28 DB –40°C to +85°C ADS1241E ADS1241E Rails, 48

"" " ""ADS1241E/1K Tape and Reel, 1000

SPECIFIED

RANGE MARKING NUMBER MEDIA, QUANTITY

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Input/Output Logic Family CMOS Logic Level: V

Input Leakage: I

Master Clock Rate: f Master Clock Period: t

IH

V

IL

V

OH

V

OL

IH

I

IL

OSC

IOH = 1mA DVDD – 0.4 V IOL = 1mA DGND DGND + 0.4 V VI = DV

DD

VI = 0 –10 µA

1/f

OSC

0.8 • DV

DD

DGND 0.2 • DV

15MHz

200 1000 ns

DV

DD

10 µA

V V

2

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ADS1240, 1241

SBAS173C

ELECTRICAL CHARACTERISTICS: AVDD = 5V

All specifications T

PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT

Analog Input Range Buffer OFF AGND – 0.1 AV

Full-Scale Input Range

Differential Input Impedance Buffer OFF 5/PGA M Ω

Bandwidth

f

= 3.75Hz –3dB 1.65 Hz

DATA

f

= 7.50Hz –3dB 3.44 Hz

DATA

f

= 15.00Hz –3dB 14.6 Hz

DATA

Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance 9pF Input Leakage Current Modulator OFF, T = 25°C5 pA Burnout Current Sources 2 µA

OFFSET DAC

Offset DAC Range RANGE = 0 ±V

Offset Monotonicity 8 Bits Offset DAC Gain Error ±10 % Offset DAC Gain Error Drift 1 ppm/°C

SYSTEM PERFORMANCE

Resolution No Missing Codes 24 Bits Integral Nonlinearity End Point Fit ±0.0015 % of FS Offset Error Offset Drift Gain Error 0.005 % Gain Error Drift Common-Mode Rejection at DC 100 dB

Normal-Mode Rejection f

Output Noise See Typical Characteristics Power-Supply Rejection at DC, dB = –20 log(∆V

VOLTAGE REFERENCE INPUT

V

REF

Reference Input Range REF IN+, REF IN– 0 AV

Common-Mode Rejection at DC 120 dB Common-Mode Rejection f Bias Current

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV Analog Current PDWN = 0, or SLEEP 1 nA

Digital Current Normal Mode, DV

Power Dissipation PGA = 1, Buffer OFF, DV

NOTES: (1) Calibration can minimize these errors to the level of the noise.

(2) ∆V (3) 12pF switched capacitor at f

to T

MIN

, AVDD = +5V, DVDD = +2.7V to 5.25V, f

MAX

(AIN0 – AIN7, A

(1)

(3)

is a change in digital result.

OUT

INCOM

= 19.2kHz, PGA = 1, Buffer ON, f

MOD

)

Buffer ON AGND + 0.05 AV

(In+) – (In–), See Block Diagram, RANGE = 0

RANGE = 1

Buffer ON 5 GΩ

RANGE = 1 ±V

f

= 60Hz, f

CM

f

= 50Hz, f

CM

= 50Hz, f

SIG

f

= 60Hz, f

SIG

V

≡ (REF IN+) – (REF IN–), RANGE = 0

REF

= 15Hz 130 dB

DATA

= 15Hz 120 dB

DATA

= 15Hz 100 dB

DATA

= 15Hz 100 dB

DATA

/∆VDD)

OUT

RANGE = 1 0.1 AV

VREFCM

= 60Hz, f

V

REF

= 15Hz 120 dB

DATA

= 2.5V 1.3 µA

DD

PGA = 1, Buffer OFF 120 250 µA

PGA = 128, Buffer OFF 400 675 µA

PGA = 1, Buffer ON 160 300 µA

PGA = 128, Buffer ON 760 1275 µA

= 5V 80 125 µA

SLEEP Mode, DV

Read Data Continuous Mode, DVDD = 5V

DD

= 5V 60 µA

DD

PDWN 0.5 nA

= 5V 1.1 1.9 mW

DD

clock frequency.

SAMP

= 15Hz, and V

DATA

= +2.5V, unless otherwise specified.

REF

ADS1240 ADS1241

+ 0.1 V

DD

– 1.5 V

DD

±V

/PGA V

REF

±V

/(2 • PGA)

REF

/(2 • PGA) V

REF

/(4 • PGA) V

REF

V

7.5 ppm of FS

0.02 ppm of FS/°C

0.5 ppm/°C

(2)

80 95 dB

0.1 2.5 2.6 V

DD DD

V V

4.75 5.25 V

230 µA

ADS1240, 1241

SBAS173C

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3

ELECTRICAL CHARACTERISTICS: AVDD = 3V

All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, f

PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT

(AIN0 – AIN7, A

Analog Input Range Buffer OFF AGND – 0.1 AV

INCOM

)

Buffer ON AGND + 0.05 AV

Full-Scale Input Voltage Range

(In+) – (In–) See Block Diagram, RANGE = 0

RANGE = 1 Input Impedance Buffer OFF 5/PGA MΩ Differential Buffer ON 5 GΩ Bandwidth

f

= 3.75Hz –3dB 1.65 Hz

DATA

f

= 7.50Hz –3dB 3.44 Hz

DATA

f

= 15.00Hz –3dB 14.6 Hz

DATA

Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance 9pF Input Leakage Current Modulator OFF, T = 25°C5 pA Burnout Current Sources 2 µA

OFFSET DAC

Offset DAC Range RANGE = 0 ±V

RANGE = 1 ±V

Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±10 % Offset DAC Gain Error Drift 2 ppm/°C

SYSTEM PERFORMANCE

Resolution No Missing Codes 24 Bits Integral Nonlinearity End Point Fit ±0.0015 % of FS Offset Error Offset Drift Gain Error 0.01 % Gain Error Drift

(1)

Common-Mode Rejection at DC 100 dB

f

= 60Hz, f

CM

f

= 50Hz, f

Normal-Mode Rejection f

Output Noise See Typical Characteristics

CM SIG

f

SIG

= 50Hz, f = 60Hz, f

Power-Supply Rejection at DC, dB = –20 log(∆V

VOLTAGE REFERENCE INPUT

V

REF

Reference Input Range REF IN+, REF IN– 0 AV

V

≡ (REF IN+) – (REF IN–), RANGE = 0

REF

RANGE = 1 0.1 2.5 2.6 V Common-Mode Rejection at DC 120 dB

Common-Mode Rejection f Bias Current

(3)

VREFCM

= 60Hz, f

V

REF

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV Analog Current PDWN = 0, or SLEEP 1 nA

PGA = 1, Buffer OFF 107 225 µA

PGA = 128, Buffer OFF 355 600 µA

PGA = 1, Buffer ON 118 275 µA

PGA = 128, Buffer ON 483 1225 µA

Digital Current Normal Mode, DV

SLEEP Mode, DV

Read Data Continuous Mode, DVDD = 3V

PDWN = 0 0.5 nA

Power Dissipation PGA = 1, Buffer OFF, DV

NOTES: (1) Calibration can minimize these errors to the level of the noise.

(2) ∆V (3) 12pF switched capacitor at f

is a change in digital result.

OUT

clock frequency.

SAMP

= 19.2kHz, PGA = 1, Buffer ON, f

MOD

= 15Hz, and V

DATA

= +1.25V, unless otherwise specified.

REF

ADS1240 ADS1241

+ 0.1 V

DD

– 1.5 V

DD

±V

/PGA V

REF

±V

/(2 • PGA)

REF

/(2 • PGA) V

REF

/(4 • PGA) V

REF

15 ppm of FS

0.04 ppm of FS/°C

1.0 ppm/°C

= 15Hz 130 dB

DATA

= 15Hz 120 dB

DATA

= 15Hz 100 dB

DATA

= 15Hz 100 dB

DATA

(2)

OUT

/∆VDD)

75 90 dB

0.1 1.25 1.30 V

DD

= 15Hz 120 dB

DATA

= 1.25 0.65 µA

DD

= 3V 50 100 µA

DD

= 3V 40 µA

DD

= 3V 0.6 1.2 mW

DD

2.7 3.3 V

113 µA

V

4

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ADS1240, 1241

SBAS173C

PIN CONFIGURATION (ADS1240)

PIN CONFIGURATION (ADS1241)

Top View SSOP Top View SSOP

DV

DGND

X

OUT

RESET

DSYNC

PDWN

DGND

V

REF+

V

REF–

AIN0/D0 A

1/D1

IN

1

DD

2 3

IN

4 5 6

ADS1240

7 8

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

BUFEN DRDY SCLK D

OUT

D

IN

CS POL AV

DD

AGND A

INCOM

AIN3/D3 A

2/D2

IN

PIN DESCRIPTIONS (ADS1240)

NUMBER NAME DESCRIPTION

1DV 2 DGND Digital Ground 3X 4X 5 RESET Active LOW, resets the entire device. 6 DSYNC Active LOW, Synchronization Control 7 PDWN Active LOW, Power Down. The power down func-

8 DGND Digital Ground

9V 10 V 11 A 12 A

REF+

REF– IN IN

13 AIN2/D2 Analog Input 2 / Data I/O 2 14 A 15 A

IN

INCOM

16 AGND Analog Ground 17 AV 18 POL Serial Clock Polarity 19 CS Active LOW, Chip Select 20 D 21 D 22 SCLK Serial Clock, Schmitt Trigger 23 DRDY Active LOW, Data Ready 24 BUFEN Buffer Enable

Digital Power Supply

DD

Clock Input

IN

Clock Output, used with external crystals.

OUT

tion shuts down the analog and digital circuits.

Positive Differential Reference Input

Negative Differential Reference Input 0/D0 Analog Input 0 / Data I/O 0 1/D1 Analog Input 1 / Data I/O 1

3/D3 Analog Input 3 / Data I/O 3

Analog Input Common, connect to AGND if unused.

Analog Power Supply

DD

Serial Data Input, Schmitt Trigger

IN

Serial Data Output

OUT

DV

DGND

X

OUT

RESET

DSYNC

PDWN DGND

V

REF+

V

REF–

AIN0/D0

1/D1

A

IN

A

4/D4

IN

A

5/D5

IN

1

DD

2 3

IN

4 5 6 7

ADS1241

8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

BUFEN DRDY SCLK D

OUT

D

IN

CS POL AV

DD

AGND A

INCOM

AIN3/D3

2/D2

A

IN

A

7/D7

IN

A

6/D6

IN

PIN DESCRIPTIONS (ADS1241)

NUMBER NAME DESCRIPTION

1DV 2 DGND Digital Ground 3X 4X 5 RESET Active LOW, resets the entire device.

OUT

6 DSYNC Active LOW, Synchronization Control 7 PDWN Active LOW, Power Down. The power down func-

8 DGND Digital Ground

9V 10 V 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 AGND Analog Ground

REF+

REF– IN IN IN IN IN IN IN IN

INCOM

21 AV 22 POL Serial Clock Polarity 23 CS Active LOW, Chip Select 24 D 25 D 26 SCLK Serial Clock, Schmitt Trigger 27 DRDY Active LOW, Data Ready 28 BUFEN Buffer Enable

Digital Power Supply

DD

Clock Input

IN

Clock Output, used with external crystals.

tion shuts down the analog and digital circuits.

Positive Differential Reference Input

Negative Differential Reference Input 0/D0 Analog Input 0 / Data I/O 0 1/D1 Analog Input 1 / Data I/O 1 4/D4 Analog Input 4 / Data I/O 4 5/D5 Analog Input 5 / Data I/O 5 6/D6 Analog Input 6 / Data I/O 6 7/D7 Analog Input 7 / Data I/O 7 2/D2 Analog Input 2 / Data I/O 2 3/D3 Analog Input 3 / Data I/O 3

Analog Input Common, connect to AGND if unused.

Analog Power Supply

DD

Serial Data Input, Schmitt Trigger

IN

Serial Data Output

OUT

ADS1240, 1241

SBAS173C

www.ti.com

5

TIMING DIAGRAMS

SCLK

(POL = 0)

SCLK

(POL = 1)

CS

D

t

3

t

4

IN

MSB

t

1

t

5

t

2

t

6

t

2

t

10

t

11

LSB

D

OUT

(Command or Command and Data)

NOTE: (1) Bit order = 0.

SCLK Reset Waveform

t

13

SCLK

t

12

DIAGRAM 1.

t

DATA

DRDY

t

17

SCLK

t

19

DIAGRAM 2.

TIMING CHARACTERISTICS TABLES

t

7

MSB

ADS1240 or ADS1241

Resets On

t

13

t

14

t

18

t

15

Falling Edge

t

8

(1)

300 • t t13 : > 5 • t 550 • t 1050 • t

RESET, DSYNC, PDWN

< t12 < 500 • t

OSC

< t14 < 750 • t

OSC

< t15 < 1250 • t

OSC

LSB

t

9

(1)

OSC

t

16

SPEC DESCRIPTION MIN MAX UNITS

t

1

SCLK Period 4t

3 DRDY Periods

t

2

t

3

t

4

t

5

t

6

(1)

t

7

(1)

t

8

t

9

t

10

t

11

SCLK Pulse Width, HIGH and LOW 200 ns CS low to first SCLK Edge; Setup Time

(2)

0ns DIN Valid to SCLK Edge; Setup Time 50 ns Valid DIN to SCLK Edge; Hold Time 50 ns Delay between last SCLK edge for DIN and first SCLK edge for D

OUT

:

RDATA, RDATAC, RREG, WREG 50 t

SCLK Edge to Valid New D SCLK Edge to D Last SCLK Edge to D NOTE: D

OUT

, Hold Time 0 ns

OUT

Tri-State 6 10 t

OUT

goes tri-state immediately when CS goes HIGH.

OUT

50 ns

CS LOW time after final SCLK edge. 0 ns Final SCLK edge of one command until first edge SCLK

of next command:

RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC

4t

SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods SELFCAL 4 DRDY Periods RESET (also SCLK Reset or RESET Pin) 16 t

t

16

t

17

t

18

t

19

Pulse Width 4t Allowed analog input change for next valid conversion. 5000 t DOR update, DOR data not valid. 4 t First SCLK after DRDY goes LOW:

RDATAC Mode 10 t Any other mode 0 t

NOTES: (1) Load = 20pF10kΩ to DGND.

(2) CS may be tied LOW.

OSC

OSC OSC OSC OSC

OSC OSC

Periods

Periods Periods Periods Periods

Periods Periods

6

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ADS1240, 1241

SBAS173C

TYPICAL CHARACTERISTICS

POWER SUPPLY REJECTION RATIO

vs FREQUENCY

Frequency of Power Supply (Hz)

110 1k100 10k 100k

PSRR (dB)

140

120

100

80

60

40

20

0

Buffer ON

All specifications, AVDD = +5V, DVDD = +5V, f

= 2.4576MHz, PGA = 1, f

OSC

= 15Hz, and V

DATA

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

21.5

21.0

20.5

20.0

19.5

19.0

ENOB (rms)

18.5

18.0 Buffer OFF

17.5

17.0

20.5

20.0

19.5

19.0

18.5

18.0

ENOB (rms)

17.5

17.0

16.5

16.0

EFFECTIVE NUMBER OF BITS vs PGA SETTING

DR = 10

DR = 01

DR = 00

1 2 4 8 16 1286432

PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING

DR = 10

DR = 01

DR = 00

Buffer OFF, V

1 2 4 8 16 64 12832

REF

= 1.25V

PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING

22

21

DR = 00

PGA Setting

V

IN

DR = 10

DR = 01

(V)

20

19

18

ENOB (rms)

17

Buffer ON

16

15

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

Noise (rms, ppm of FS)

0.4

0.2

1 2 4 8 16 1286432

NOISE vs INPUT SIGNAL

0

–2.5 –1.5 0.5–0.5 1.5 2.5

COMMON-MODE REJECTION RATIO

140

120

100

80

60

CMRR (dB)

40

20

Buffer ON

0

1 10 100 1k 10k 100k

Frequency of Power Supply (Hz)

ADS1240, 1241

SBAS173C

vs FREQUENCY

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7