Texas Instruments ADS1234IPWRG4, ADS1232 Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

Input

Mux

DS ADC

REFP REFN

PGA

Gain=
1,2,64,or128

CAP DVDD

DGND

AGNDA1/TEMP

(1)

A0

NOTE:(1)A1forADS1234,TEMPforADS1232.

AINP1
AINN1

AINP2
AINN2

AINP3
AINN3

AINP4
AINN4

ADS1234

Only

SCLK

SPEED

DRDY/DOUT

PDWN

GAIN[1:0]

AVDD

CAP

ExternalOscillator

InternalOscillator

CLKIN/XTAL1

XTAL2

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

24-Bit Analog-to-Digital Converter

For Bridge Sensor

• Complete Front-End for Bridge Sensor

The ADS1232 and ADS1234 are precision 24-bit
analog-to-digital converters (ADCs). With an

• Up to 23.5 Effective Bits

onboard, low-noise programmable gain amplifier

• Onboard, Low-Noise PGA

(PGA), precision delta-sigma ADC and internal

• RMS Noise:

oscillator, the ADS1232/4 provide a complete

17nV at 10SPS (PGA = 128)

front-end solution for bridge sensor applications

44nV at 80SPS (PGA = 128)

including weigh scales, strain gauges and pressure
sensors.

• 19.2-Bit Noise-Free Resolution at Gain = 64

• Over 100dB Simultaneous 50Hz and 60Hz

The input multiplexer accepts either two (ADS1232)
or four (ADS1234) differential inputs. The ADS1232

Rejection

also includes an onboard temperature sensor to

• Flexible Clocking:

monitor ambient temperature. The onboard,

Low-Drift Onboard Oscillator ( ± 3%)

low-noise PGA has a selectable gain of 1, 2, 64, or

Optional External Crystal

128 supporting a full-scale differential input of ± 2.5V,

• Selectable Gains of 1, 2, 64, and 128

± 1.25V, ± 39mV, or ± 19.5mV. The delta-sigma ADC

has 23.5-bit effective resolution and is comprised of

• Easy Ratiometric Measurements–

a 3rd-order modulator and 4th-order digital filter. Two

External Voltage Reference up to 5V

data rates are supported: 10SPS (with both 50Hz

• Selectable 10SPS or 80SPS Data Rates

and 60Hz rejection) and 80SPS. The ADS1232/4 can

• Two-Channel Differential Input with Built-In

be clocked externally using an oscillator or a crystal.

Temperature Sensor (ADS1232)

There is also an internal oscillator available that
requires no external components. Offset calibration

• Four-Channel Differential Input (ADS1234)

is performed on-demand and the ADS1232/4 can be

• Simple Serial Digital Interface

put in a low-power standby mode or shut off

• Supply Range: 2.7V to 5.3V

completely in power-down mode. All of the features
of the ADS1232/4 are operated through simple

• –40 ° C to +105 ° C Temperature Range

pin-driven control. There are no digital registers to
program in order to simplify software development.
Data is output over an easily-isolated serial interface

• Weigh Scales

that connects directly to the MSP430 and other

• Strain Gauges

microcontrollers.

• Pressure Sensors

The ADS1232 is available in a TSSOP-24 package

• Industrial Process Control

and the ADS1234 is in a TSSOP-28. Both are fully
specified from -40 ° C to +105 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or see the TI website at www.ti.com.

over operating free-air temperature range (unless otherwise noted)

(1)

ADS1232, ADS1234 UNIT

AVDD to AGND –0.3 to +6 V
DVDD to DGND –0.3 to +6 V
AGND to DGND –0.3 to +0.3 V
Input Current 100, Momentary mA
Input Current 10, Continuous mA
Analog Input Voltage to AGND –0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range –40 to +105 °C
Storage Temperature Range –60 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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ELECTRICAL CHARACTERISTICS

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

All specifications at TA= –40°C to +105°C, AVDD = DVDD = VREFP = +5V, and VREFN = AGND, unless otherwise noted.

ADS1232, ADS1234

PARAMETER CONDITIONS MIN TYP MAX UNIT

Analog Inputs

Full-Scale Input Voltage

±0.5V

REF

/Gain V

(AINP – AINN)

AINxP or AINxN with respect to GND,

AGND – 0.1 AVDD + 0.1 V

Gain = 1, 2

Common-Mode Input Range

Gain = 64, 128 AGND + 1.5V AVDD – 1.5V V
Gain = 1 ± 3 nA

Differential Input Current Gain = 2 ± 6 nA

Gain = 64, 128 ± 3.5 nA

System Performance

Resolution No Missing Codes 24 Bits

Internal Oscillator, SPEED = High 78 80 82.4 SPS
Internal Oscillator, SPEED = Low 9.75 10 10.3 SPS

Data Rate

External Oscillator, SPEED = High f

CLK

/61,440 SPS

External Oscillator, SPEED = Low f

CLK

/491,520 SPS

Digital Filter Settling Time Full Settling 4 Conversions

Differential Input, End-Point Fit

± 0.0002 ± 0.001 % of FSR

(1)

Gain = 1, 2

Integral Nonlinearity (INL)

Differential Input, End-Point Fit

± 0.0004 % of FSR

Gain = 64, 128
Gain = 1 ± 0.2 ± 5 ppm of FS

Input Offset Error

(2)

Gain = 128 ± 0.02 ± 1 ppm of FS
Gain = 1 ± 0.3 µV/°C

Input Offset Drift

Gain = 128 ± 10 nV/°C
Gain = 1 ± 0.001 ± 0.02 %

Gain Error

(3)

Gain = 128 ± 0.01 ± 0.1 %
Gain = 1 ± 0.2 ppm/ ° C

Gain Drift

Gain = 128 ± 2.5 ppm/ ° C
Internal Oscillator, f

DATA

= 10SPS

100 110 dB

fIN= 50Hz or 60Hz, ± 1Hz

Normal-Mode Rejection

(4)

External Oscillator, f

DATA

= 10SPS

120 130 dB

fIN= 50Hz or 60Hz, ± 1Hz
at DC, Gain = 1, ∆ VDD = 1V 95 110 dB

Common-Mode Rejection

at DC, Gain = 128, ∆ VDD = 0.1V 95 110 dB

Input-Referred Noise See Noise Performance Tables

at DC, Gain = 1, ∆ VDD = 1V 100 120 dB

Power-Supply Rejection

at DC, Gain = 128, ∆ VDD = 0.1V 100 120 dB

Voltage Reference Input

Voltage Reference Input (V

REF

) V

REF

= VREFP – VREFN 1.5 AVDD AVDD + 0.1V V
Negative Reference Input (VREFN) AGND – 0.1 VREFP – 1.5 V
Positive Reference Input (VREFP) VREFN + 1.5 AVDD + 0.1 V
Voltage Reference

10 nA

Input Current

(1) FSR = full-scale range = V

REF

/Gain.
(2) Offset calibration can minimize these errors to the level of noise at any temperature.
(3) Gain errors are calibrated at the factory (AVDD = +5V, all gains, TA= +25 ° C).
(4) Specification is assured by the combination of design and final production test.

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ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= –40°C to +105°C, AVDD = DVDD = VREFP = +5V, and VREFN = AGND, unless otherwise noted.

ADS1232, ADS1234

PARAMETER CONDITIONS MIN TYP MAX UNIT

Digital

Logic Levels

All digital inputs except CLKIN/XTAL1 0.7 DVDD DVDD + 0.1 V

V

IH

CLKIN/XTAL1 0.7 DVDD 5.1 V

V

IL

DGND 0.2 DVDD V

V

OH

IOH= 1mA DVDD – 0.4 V

V

OL

IOL= 1mA 0.2 DVDD V
Input Leakage 0 < VIN< DVDD ± 10 µA
External Clock Input Frequency

0.2 4.9152 8 MHz

(f

CLKIN

)

Serial Clock Input Frequency (f

SCLK

) 5 MHz

Power Supply

Power-Supply Voltage

2.7 5.3 V

(AVDD, DVDD)

Normal Mode, AVDD = 3V,

600 1300 µA

Gain = 1, 2

Normal Mode, AVDD = 3V,

1350 2500 µA

Gain = 64, 128

Normal Mode, AVDD = 5V,

650 1300 µA

Analog Supply Current

Gain = 1, 2

Normal Mode, AVDD = 5V,

1350 2500 µA

Gain = 64, 128

Standby Mode 0.1 1 µA

Power-Down 0.1 1 µA

Normal Mode, DVDD = 3V,

60 95 µA

Gain = 1, 2

Normal Mode, DVDD = 3V,

75 120 µA

Gain = 64, 128

Normal Mode, DVDD = 5V,

95 130 µA

Gain = 1, 2
Digital Supply Current

Normal mode, DVDD = 5V,

75 120 µA

Gain = 64, 128

Standby Mode, SCLK = High, DVDD = 3V 45 80 µA

Standby Mode, SCLK = High, DVDD = 5V 65 80 µ A

Power-Down 0.2 1.3 µA

Normal Mode, AVDD = DVDD = 3V,

2 4.2 mW

Gain = 1, 2

Normal Mode, AVDD = DVDD = 5V,

3.7 7.2 mW

Gain = 1, 2
Power Dissipation, Total Normal Mode, AVDD = DVDD = 3V,

4.3 7.9 mW

Gain = 64, 128

Normal Mode, AVDD = DVDD = 5V,

7.1 13.1 mW

Gain = 64, 128

Standby Mode, AVDD = DVDD = 5V 0.3 0.4 mW

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NOISE PERFORMANCE

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

The ADS1232/4 offer outstanding noise performance that can be optimized for a given full-scale range using the
on-chip programmable gain amplifier. Table 1 through Table 4 summarize the typical noise performance with
inputs shorted externally for different gains, data rates, and voltage reference values.

The RMS and Peak-to-Peak noise are referred to the input. The Effective Number of Bits (ENOB) is defined as:

• ENOB = ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:

• Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)
Where FSR (Full-Scale Range) = V

REF

/Gain

Table 1. AVDD = 5V, V

REF

= 5V, Data Rate = 10SPS

GAIN RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB (RMS) NOISE-FREE BITS

1 420nV 1.79µV 23.5 21.4
2 270nV 900nV 23.1 21.4

64 19nV 125nV 22.0 19.2

128 17nV 110nV 21.1 18.4

(1) Peak-to-peak noise data is based on direct measurement.

Table 2. AVDD = 5V, V

REF

= 5V, Data Rate = 80SPS

GAIN RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB (RMS) NOISE-FREE BITS

1 1.36µV 8.3µV 21.8 19.2
2 850nV 5.5µV 21.5 18.8

64 48nV 307nV 20.6 18

128 44nV 247nV 19.7 17.2

(1) Peak-to-peak noise data is based on direct measurement.

Table 3. AVDD = 3V, V

REF

= 3V, Data Rate = 10SPS

GAIN RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB (RMS) NOISE-FREE BITS

1 450nV 2.8µV 22.6 20
2 325nV 1.8µV 22.1 19.7

64 20nV 130nV 21.2 18.5

128 18nV 115nV 20.3 17.6

(1) Peak-to-peak noise data is based on direct measurement.

Table 4. AVDD = 3V, V

REF

= 3V, Data Rate = 80SPS

GAIN RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB (RMS) NOISE-FREE BITS

1 2.2µV 12µV 20.4 17.9
2 1.2µV 6.8µV 20.2 17.8

64 54nV 340nV 19.7 17.1

128 48nV 254nV 18.9 16.5

(1) Peak-to-peak noise data is based on direct measurement of 1024 samples.

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PIN CONFIGURATION

DVDD

DGND

CLKIN/XTAL1

XTAL2

DGND
DGND

A1

A0
CAP
CAP

AINP1
AINN1
AINP3
AINN3

DRDY/DOUT
SCLK
PDWN
SPEED
GAIN1
GAIN0
AVDD
AGND
REFP
REFN
AINP2
AINN2
AINP4
AINN4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21

20
19
18
17
16
15

ADS1234

DVDD

DGND

CLKIN/XTAL1

XTAL2

DGND
DGND

TEMP

A0
CAP
CAP

AINP1
AINN1

DRDY/DOUT
SCLK
PDWN
SPEED
GAIN1
GAIN0
AVDD
AGND
REFP
REFN
AINP2
AINN2

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21

20
19
18
17
16
15
14
13

ADS1232

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

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ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

PIN CONFIGURATION (continued)

PIN DESCRIPTIONS

TERMINAL

ANALOG/DIGITAL

NAME ADS1232 ADS1234 INPUT/OUTPUT DESCRIPTION

DVDD 1 1 Digital Digital Power Supply: 2.7V to 5.3V
DGND 2 2 Digital Digital Ground
CLKIN/ External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator. Can also use

3 3 Digital/Digital Input

XTAL1 external crystal across CLKIN/XTAL1 and XTAL2 pins. See text for more details.
XTAL2 4 4 Digital External crystal connection
DGND 5 5 Digital Digital Ground
DGND 6 6 Digital Digital Ground
TEMP 7 – Digital Input Onboard Temperature Diode Enable

Input Mux Select Input pin (MSB)
Input Mux Select Input pin (LSB):

A1 A0 Channel

A1 – 7

Digital Input 0 0 AIN1

A0 8 8

0 1 AIN2
1 0 AIN3

1 1 AIN4
CAP 9 9 Analog Gain Amp Bypass Capacitor Connection
CAP 10 10 Analog Gain Amp Bypass Capacitor Connection
AINP1 11 11 Analog Input Positive Analog Input Channel 1
AINN1 12 12 Analog Input Negative Analog Input Channel 1
AINP3 – 13 Analog Input Positive Analog Input Channel 3
AINN3 – 14 Analog Input Negative Analog Input Channel 3
AINN4 – 15 Analog Input Negative Analog Input Channel 4
AINP4 – 16 Analog Input Positive Analog Input Channel 4
AINN2 13 17 Analog Input Negative Analog Input Channel 2
AINP2 14 18 Analog Input Positive Analog Input Channel 2
REFN 15 19 Analog Input Negative Reference Input
REFP 16 20 Analog Input Positive Reference Input
AGND 17 21 Analog Analog Ground
AVDD 18 22 Analog Analog Power Supply, 2.7V to 5.3V

Gain Select

GAIN1 GAIN0 GAIN

0 0 1

GAIN0 19 23

Digital Input

GAIN1 20 24

0 1 2

1 0 64

1 1 128

Data Rate Select:

SPEED DATA RATE

SPEED 21 25 Digital Input

0 10SPS
1 80SPS

PDWN 22 26 Digital Input Power-Down: Holding this pin low powers down the entire converter and resets the ADC.

Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep

SCLK 23 27 Digital Input

modes. See text for more details.
Dual-Purpose Output:

DRDY/

24 28 Digital Output Data Ready: Indicates valid data by going low.

DOUT

Data Output: Outputs data, MSB first, on the first rising edge of SCLK.

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TYPICAL CHARACTERISTICS

Time (Reading Number)

Output Code (LSB)

6
5
4
3
2
1

−

1

−

2

−

3

−

4

−

5

−

6

200 400 600 800 1000

0

PGA = 1
Data Rate = 10SPS

Time (Reading Number)

Output Code (LSB)

25
20
15
10

5
0

−

5

−

10

−

15

−

20

−

25

200 400 600 800 1000

0

PGA = 128
Data Rate = 10SPS

Output Code (LSB)

Occurrence

300

250

200

150

100

50

0

−

4

−

2

0

2

4

PGA = 1
Data Rate = 10SPS

Output Code (LSB)

Occurrence

100

90
80
70
60
50
40
30
20
10

0

−

16

1680

−

8

PGA = 128
Data Rate = 10SPS

Time (Reading Number)

Output Code(LSB)

22.5

17.5

12.5

7.5

2.5

−

2.5

−

7.5

−

12.5

−

17.5

−

22.5
200 400 600 800 1000

0

PGA = 1
Data Rate = 80SPS

Time (Reading Number)

Output Code (LSB)

70

50

30

10

−

10

−

30

−

50

−

70

200 400 600 800 1000

0

PGA = 128
Data Rate = 80SPS

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

At TA= +25 ° C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.

NOISE PLOT NOISE PLOT

Figure 1. Figure 2.

NOISE HISTOGRAM NOISE HISTOGRAM

Figure 3. Figure 4.

NOISE PLOT NOISE PLOT

Figure 5. Figure 6.

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Output Code (LSB)

Occurance

180
160
140
120
100

80
60
40
20

0

−

12

−

6

1260

PGA = 1
Data Rate = 80SPS

Output Code (LSB)

Occurance

50
45
40
35
30
25
20
15
10

5
0

−

40

−

20 0 20

40

PGA = 128
Data Rate = 80SPS

Temperature (_C)

Offset (nV)

1000

500

0

−

500

−

1000

110

−50−30−

10 10 30 50 70 90

PGA = 128
Data Rate = 10SPS

Temperature (_C)

Gain Error (%)

0.04

0.03

0.02

0.01

0

−

0.01

−

0.02
110

−50−30−

10 10 30 50 70 90

PGA = 128
Data Rate = 10SPS

VIN(V)

RMS Noise (nV)

1000

900
800
700
600
500
400
300
200
100

0

2.5

−

2.5−2.0−1.5

−

0.5

−

1.0 1.00 0.5 1.5 2.0

PGA = 1
Data Rate = 10SPS

VIN(mV)

RMS Noise (nV)

50
45
40
35
30
25
20
15
10

5
0

19

−19−

14.25−9.5−4.75 4.750 9.5 14.25

PGA = 128
Data Rate = 10SPS

ADS1232
ADS1234

SBAS350C – JUNE 2005 – REVISED JUNE 2006

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = DVDD = VREFP = 5V, and VREFN = AGND, unless otherwise noted.

NOISE HISTOGRAM NOISE HISTOGRAM

Figure 7. Figure 8.

OFFSET vs TEMPERATURE GAIN ERROR vs TEMPERATURE

Figure 9. Figure 10.

NOISE vs INPUT SIGNAL NOISE vs INPUT SIGNAL

Figure 11. Figure 12.

9