Datasheet ADS1230IPWRG4, ADS1230 Datasheet (Texas Instruments)

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FEATURES DESCRIPTION

APPLICATIONS

DS ADC

REFP REFNCAP DVDD

DGND

GAIN

AINP

AINN

SCLK

SPEED

DRDY/DOUT

PDWN

AVDD

CAP

Internal

Oscillator

CLKIN

Gain=64or128

PGA

AGND

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

20-Bit Analog-to-Digital Converter

For Bridge Sensors

• Complete Front-End for Bridge Sensor

The ADS1230 is a precision 20-bit analog-to-digital
converter (ADC). With an onboard low-noise

• Onboard PGA with Gain of 64 or 128

programmable gain amplifier (PGA), onboard

• Onboard Oscillator

oscillator, and precision 20-bit delta-sigma ADC, the

• RMS Noise:

ADS1230 provides a complete front-end solution for

40nV at 10SPS (G = 128)

bridge sensor applications including weigh scales,

88nV at 80SPS (G = 128)

strain gauges, and pressure sensors.

• 18-Bit Noise-Free Resolution

The low-noise PGA has a gain of 64 or 128,

• Selectable 10SPS or 80SPS Data Rates

supporting a full-scale differential input of ± 39mV or
± 19.5mV, respectively. The delta-sigma ADC has

• Simultaneous 50Hz and 60Hz Rejection at

20-bit effective resolution and is comprised of a

10SPS

3rd-order modulator and 4th-order digital filter. Two

• External Voltage Reference up to 5V for

data rates are supported: 10SPS (with both 50Hz

Ratiometric Measurements

and 60Hz rejection) and 80SPS. The ADS1230 can
be clocked by the internal oscillator or an external

• Simple, Pin-Driven Control

clock source. Offset calibration is performed

• Two-Wire Serial Digital Interface

on-demand, and the ADS1230 can be put in a

• Tiny 16-pin TSSOP Package

low-power standby mode or shut off completely in

• Supply Range: 2.7V to 5.3V

power-down mode.

• –40 ° C to +85 ° C Temperature Range

All of the features of the ADS1230 are controlled by
dedicated pins; there are no digital registers to
program. Data are output over an easily-isolated
serial interface that connects directly to the MSP430

• Weigh Scales

and other microcontrollers.

• Strain Gauges

The ADS1230 is available in a TSSOP-16 package

• Pressure Sensors
and is specified from –40 ° C to +85 ° C.

• Industrial Process Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com .

over operating free-air temperature range (unless otherwise noted)

(1)

ADS1230 UNIT

AVDD to AGND –0.3 to +6 V
DVDD to DGND –0.3 to +6 V
AGND to DGND –0.3 to +0.3 V

100, Momentary mA

Input Current

10, Continuous mA
Analog Input Voltage to AGND –0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 ° C
Operating Temperature Range –40 to +85 ° C
Storage Temperature Range –60 to +150 ° C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

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ELECTRICAL CHARACTERISTICS

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

All specifications at TA= –40 ° C to +85 ° C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted.

ADS1230

PARAMETER CONDITIONS MIN TYP MAX UNIT

Analog Inputs

Full-Scale Input Voltage (AINP – AINN) ± 0.5V

REF

/PGA V
Common-Mode Input Range AGND + 1.5V AVDD – 1.5V V
Differential Input Current ± 2 nA

System Performance

Resolution No Missing Codes 20 Bits

Internal Oscillator, SPEED = High 80 SPS
Internal Oscillator, SPEED = Low 10 SPS

Data Rate

External Oscillator, SPEED = High f

CLK

/61,440 SPS

External Oscillator, SPEED = Low f

CLK

/491,520 SPS

Digital Filter Settling Time Full Settling 4 Conversions

Differential Input, End-Point Fit, G = 64 ± 10 ppm

Integral Nonlinearity (INL)

Differential Input, End-Point Fit, G = 128 ± 6 ppm

Input Offset Error

(1)

± 3 ppm of FS
Input Offset Drift ± 10 nV/ ° C
Gain Error ± 0.8 %
Gain Drift ± 4 ppm/ ° C

Internal Oscillator 80 90 dB

fIN= 50Hz or 60Hz ± 1Hz,

Normal-Mode Rejection

(2)

f

DATA

= 10SPS

External Oscillator

(3)

90 100 dB

Common-Mode Rejection at DC, Δ VDD = 0.1V 110 dB

f

DATA

= 10SPS 53 nV, rms

Input-Referred Noise

f

DATA

= 80SPS 100 nV, rms

Power-Supply Rejection at DC, Δ VDD = 0.1V 90 100 dB

Voltage Reference Input

Voltage Reference Input (V

REF

) V

REF

= REFP – REFN 1.5 AVDD AVDD + 0.1V V
Negative Reference Input (REFN) AGND – 0.1 REFP – 1.5 V
Positive Reference Input (REFP) REFN + 1.5 AVDD + 0.1 V
Voltage Reference Input Current 10 nA

Digital

All digital inputs except CLKIN 0.7 DVDD DVDD + 0.1 V

V

IH

CLKIN 0.7 DVDD 5.1 V

Logic Levels V

IL

DGND 0.2 DVDD V

V

OH

IOH= 1mA DVDD – 0.4 V

V

OL

IOL= 1mA 0.2 DVDD V
Input Leakage 0 < VIN< DVDD ± 10 μ A
External Clock Input Frequency (f

CLKIN

) 0.2 4.9152 6 MHz

Serial Clock Input Frequency (f

SCLK

) 5 MHz

(1) Offset calibration can minimize these errors to the level of noise at any temperature.
(2) Specification is assured by the combination of design and final production test.
(3) External oscillator = 4.9152MHz.

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ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= –40 ° C to +85 ° C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted.

ADS1230

PARAMETER CONDITIONS MIN TYP MAX UNIT

Power Supply

Power-Supply Voltage (AVDD, DVDD) 2.7 5.3 V

Normal Mode, AVDD = 3V 900 1400 μ A

Normal Mode, AVDD = 5V 900 1400 μ A
Analog Supply Current

Standby Mode 0.1 1 μ A

Power-Down 0.1 1 μ A

Normal Mode, DVDD = 3V 60 100 μ A

Normal mode, DVDD = 5V 95 140 μ A
Digital Supply Current Standby Mode, SCLK = High, DVDD = 3V 45 65 μ A

Standby Mode, SCLK = High, DVDD = 5V 65 80 μ A

Power-Down 0.2 μ A

Normal Mode, AVDD = DVDD = 3V 2.9 4.5 mW
Power Dissipation, Total Normal Mode, AVDD = DVDD = 5V 5.0 7.7 mW

Standby Mode, AVDD = DVDD = 5V 0.3 0.4 mW

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PIN CONFIGURATION

DVDD

DGND

CLKIN

GAIN

CAP

CAP

AINP

AINN

DRDY/DOUT

SCLK

PDWN

SPEED

AVDD

AGND

REFP

REFN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADS1230

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

PW PACKAGE

TSSOP-16
(Top View)

PIN DESCRIPTIONS

ANALOG/DIGITAL

NAME TERMINAL INPUT/OUTPUT DESCRIPTION

DVDD 1 Digital Digital Power Supply: 2.7V to 5.3V
DGND 2 Digital Digital Ground
CLKIN 3 Digital/Digital Input External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator.

PGA Gain Select

GAIN PGA

GAIN 4 Digital Input

0 64

1 128
CAP 5 Analog Gain Amp Bypass Capacitor Connection
CAP 6 Analog Gain Amp Bypass Capacitor Connection
AINP 7 Analog Input Positive Analog Input
AINN 8 Analog Input Negative Analog Input
REFN 9 Analog Input Negative Reference Input
REFP 10 Analog Input Positive Reference Input
AGND 11 Analog Analog Ground
AVDD 12 Analog Analog Power Supply, 2.7V to 5.3V

Data Rate Select:

SPEED DATA RATE

SPEED 13 Digital Input

0 10SPS

1 80SPS
PDWN 14 Digital Input Power-Down: Holding this pin low powers down the entire converter and resets the ADC.

Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep

SCLK 15 Digital Input modes. See the Offset Calibration , Standby Mode , and Standby Mode with Offset Calibration sections

for more details.
Dual-Purpose Output:

DRDY/DOUT 16 Digital Output Data Ready: Indicates valid data by going low.

Data Output: Outputs data, MSB first, on the first rising edge of SCLK.

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NOISE PERFORMANCE

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

The ADS1230 offers outstanding noise performance. Table 1 summarizes the typical noise performance with
inputs shorted externally for different data rates and voltage reference values.

The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:

ENOB = ln (FSR/RMS noise)/ln(2)

The Noise-Free Bits are defined as:

Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)

Where:

FSR (Full-Scale Range) = V

REF

/Gain.

Table 1. Noise Performance for AV

DD

= 5V and V

REF

= 5V

RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB

DATA RATE GAIN (nV) (nV) (RMS) NOISE-FREE BITS

64 53 290 20.5 18

10

128 40 198 19.8 17.5

64 100 480 19.5 17.3

80

128 88 480 18.7 16.3

(1) Peak-to-peak data are based on direct measurement.

Table 2. Noise Performance for AV

DD

= 3V and V

REF

= 3V

RMS NOISE PEAK-TO-PEAK NOISE

(1)

ENOB

DATA RATE GAIN (nV) (nV) (RMS) NOISE-FREE BITS

64 46 290 20.6 18

10

128 49 259 19.6 17.2

64 100 576 19.5 17

80

128 102 461 18.5 16.3

(1) Peak-to-peak data are based on direct measurement.

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TYPICAL CHARACTERISTICS

4

3

2

1

0

10008006004002000

OutputCode(LSB)

Time(ReadingNumber)

PGA=64
DataRate=10SPS

3

2

1

0

-1

-2

-3

-4

-5

-6

10008006004002000

OutputCode(LSB)

Time(ReadingNumber)

PGA=64
DataRate=80SPS

900

800

700

600

500

400

300

200

100

0

321

Occurrence

OutputCode(LSB)

PGA=64
DataRate=10SPS

400

350

300

250

200

150

100

50

0

1 2-5 -4 -3 -2 -1 0

Occurrence

OutputCode(LSB)

PGA=64
DataRate=80SPS

0

-1

-2

-3

-4

-5

-6

10008006004002000

OutputCode(LSB)

Time(ReadingNumber)

PGA=128
DataRate=10SPS

8

6

4

2

0

-2

-4

-6

-8

-10

10008006004002000

OutputCode(LSB)

Time(ReadingNumber)

PGA=128
DataRate=80SPS

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

At TA= +25 ° C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.

NOISE PLOT NOISE PLOT

Figure 1. Figure 2.

NOISE HISTOGRAM NOISE HISTOGRAM

Figure 3. Figure 4.

NOISE PLOT NOISE PLOT

Figure 5. Figure 6.

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500

450

400

350

300

250

200

150

100

50

0

-5 -4 -3 -2 -1 0

Occurrence

OutputCode(LSB)

PGA=128
DataRate=10SPS

250

200

150

100

50

0

-7 -5-6 -4 -3 -2 -1 0 1 2 43 5 6 7

Occurrence

OutputCode(LSB)

PGA=128
DataRate=80SPS

1000

800

600

400

200

0

-200

-400

-600

-800

1007550250-25-50

Offset(nV)

Temperature( C)°

PGA=64
DataRate=10SPS

-0.02

-0.03

-0.04

-0.05

-0.06

1007550250-25-50

GainError(%)

Temperature( C)°

PGA=64
DataRate=10SPS

50

45

40

35

30

25

20

15

10

5

0

40-10 0 10 20 30-40 -30 -20

RMSNoise(nV)

V (mV)

IN

PGA=64
DataRate=10SPS

120

100

80

60

40

40-10 0 10 20 30-40 -30 -20

RMSNoise(nV)

V (mV)

IN

PGA=64
DataRate=80SPS

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.

NOISE HISTOGRAM NOISE HISTOGRAM

Figure 7. Figure 8.

OFFSET vs TEMPERATURE GAIN ERROR vs TEMPERATURE

Figure 9. Figure 10.

NOISE vs INPUT SIGNAL NOISE vs INPUT SIGNAL

Figure 11. Figure 12.

8

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10

5

0

-5

-10

40-10 0 10 20 30-40 -30 -20

INL(ppm)

V (mV)

IN

-40°C

-20°C

+25°C

+70°C

+85°C

PGA=64
DataRate=10SPS

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

200 10-20 -10

INL(ppm)

V (mV)

IN

PGA=128
DataRate=10SPS

- °20 C

+ °85 C

+ °25 C

+ °70 C

- °40 C

1200

1000

800

600

400

200

0

1007550250-25-50

AnalogCurrent( A)m

Temperature( C)°

PGA=64,128

97

96

95

94

93

92

91

90

89

88

1007550250-25-50

DigitalCurrent( A)m

Temperature( C)°

PGA=64

PGA=128

9.85

9.80

9.75

9.70
1007550250-25-50

DataRate(SPS)

Temperature( C)°

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.

INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY

vs INPUT SIGNAL vs INPUT SIGNAL

Figure 13. Figure 14.

ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE

(Normal Mode) (Normal Mode)

Figure 15. Figure 16.

DATA RATE

vs TEMPERATURE

Figure 17.

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OVERVIEW

ANALOG INPUTS (AINP, AINN)

R

INT

R

INT

R

F1

R

1

R

F2

ADC

A3

Gain=1or2

CAP

AINP

CAP

A2

A1

450W

18pF

AINN

450W

18pF

Bypass Capacitor

LOW-NOISE PGA

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

unipolar input ranges from 0mV to +39mV (Gain =

64) or 0mV to +19.5mV (Gain = 128). The inputs of

The ADS1230 is a precision, 20-bit ADC that

the ADS1230 are protected with internal diodes

includes a low-noise PGA, internal oscillator,

connected to the power-supply rails. These diodes

third-order delta-sigma ( Δ Σ ) modulator, and

clamp the applied signal to prevent it from damaging

fourth-order digital filter. The ADS1230 provides a

the input circuitry.

complete front-end solution for bridge sensor
applications such as weigh scales, strain guages,
and pressure sensors.

Clocking can be supplied by an external clock or by
a precision internal oscillator. Data can be output at
10SPS for excellent 50Hz and 60Hz rejection, or at
80SPS when higher speeds are needed. The
ADS1230 is easy to configure, and all digital control
is accomplished through dedicated pins; there are no
registers to program. A simple two-wire serial
interface retrieves the data.

The input signal to be measured is applied to the
input pins AINP and AINN. The ADS1230 accepts
differential input signals, but can also measure
unipolar signals. When measuring unipolar (or
single-ended signals) with respect to ground,

Figure 18. Simplified Diagram of the PGA

connect the negative input (AINN) to ground and
connect the input signal to the positive input (AINP).
Note that when the ADS1230 is configured this way,
only half of the converter full-scale range is used,

By applying a 0.1 μ F external capacitor (C

EXT

) across

since only positive digital output codes are produced.

two capacitor pins combined with the internal 2k Ω
resistor R

INT

(on-chip), a low-pass filter with a corner
frequency of 720Hz is created to bandlimit the signal
path before the modulator input. This low-pass filter

The ADS1230 features a low-drift, low-noise PGA

serves two purposes. First, the input signal is

that provides a complete front-end solution for bridge

bandlimited to prevent aliasing as well as to filter out

sensors. A simplified diagram of the PGA is shown in

the high-frequency noise. Second, it attenuates the

Figure 18 . It consists of two chopper-stabilized

chopping residue from the amplifier to improve

amplifiers (A1 and A2) and three accurately-matched

temperature drift performance. It is not required to

resistors (R

1

, R

F1

, and R

F2

), which construct a

use high-quality capacitors (such as ceramic or

differential front-end stage with a gain of 64, followed

tantalum capacitors) for a general application.

by gain stage A3 (Gain = 1 or 2). The PGA inputs

However, high-quality capacitors such as poly are

are equipped with an EMI filter, as shown in

recommended for high-linearity applications.

Figure 18 . The cutoff frequency of the EMI filter is

19.6MHz. By using AVDD as the reference input, the
bipolar input ranges from –39mV to +39mV (Gain =

64) or –19.5mV to +19.5mV (Gain = 128), and the

10

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VOLTAGE REFERENCE INPUTS CLOCK SOURCES

Z

EFF

+

1

2f

MOD

C

BUF

Z

EFF

+

1

(2)(76.8kHz)(13fF)

+ 500MW

CLK_DETECT

Internal

Oscillator

MUX

ToADC

S

S0 S1

EN

CLKIN

AVDD

(1)f

MOD

=76.8kHz

Z =500MW

EFF

(1)

REFP REFN

AVDD

ESD

Protection

C

BUF

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

(REFP, REFN)

The ADS1230 can use an external clock source or

The voltage reference used by the modulator is internal oscillator to accommodate a wide variety of
generated from the voltage difference between applications. Figure 20 shows the equivalent circuitry
REFP and REFN: V

REF

= REFP – REFN. The of the clock source. The CLK_DETECT block
reference inputs use a structure similar to that of the determines whether the crystal oscillator/external
analog inputs. In order to increase the reference clock signal is applied to the CLKIN pin so that the
input impedance, a switching buffer circuitry is used internal oscillator is bypassed or activated. When the
to reduce the input equivalent capacitance. The CLKIN pin frequency is above ~200kHz, the
reference drift and noise impact ADC performance. CLK_DETECT output goes low and shuts down the
In order to achieve best results, pay close attention internal oscillator. When the CLKIN pin frequency is
to the reference noise and drift specifications. A below ~200kHz, the CLK_DETECT output goes high
simplified diagram of the circuitry on the reference and activates the internal oscillator. It is highly
inputs is shown in Figure 19 . The switches and recommended to hard-wire the CLKIN pin to ground
capacitors can be modeled approximately using an when the internal oscillator is chosen.
effective impedance of:

Where:

f

MOD

= modulator sampling frequency (76.8kHz)

C

BUF

= input capacitance of the buffer

For the ADS1230:

Figure 20. Equivalent Circuitry of the Clock

Source

An external clock may be used by driving the CLKIN
pin directly. The Electrical Characteristics table
shows the allowable frequency range. The clock
input may be driven with 5V logic, regardless of the
DVDD or AVDD voltage.

Figure 19. Simplified Reference Input Circuitry

ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the
voltages on the reference pins do not go below GND
by more than 100mV, and likewise, do not exceed
AVDD by 100mV:

GND – 100mV < (REFP or REFN) < AVDD + 100mV

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FREQUENCY RESPONSE

Frequency(kHz)

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

38.4 76.8

0

f =4.9152MHz

CLK

Gain(dB)

Frequency(Hz)

Gain(dB)

0

-50

-100

-150

0 10 20 30 40 50 60 70 80 90 100

(a)

Frequency(Hz)

(b)

Gain(dB)

-50

-100

-150

494846 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

DataRate=10SPS

DataRate=10SPS

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

The ADS1230 uses a sinc

4

digital filter with the

frequency response (f

CLK

= 4.9152MHz) shown in

Figure 21 . The frequency response repeats at

multiples of the modulator sampling frequency of

76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).

Figure 21. Frequency Response

To help see the response at lower frequencies,

Figure 22 (a) illustrates the response out to 100Hz,

when the data rate = 10SPS. Notice that signals at
multiples of 10Hz are rejected, and therefore
simultaneous rejection of 50Hz and 60Hz is

Figure 22. Frequency Response Out To 100Hz

achieved.
The benefit of using a sinc

4

filter is that every

The ADS1230 data rate and frequency response

frequency notch has four zeros on the same location.

scale directly with clock frequency. For example, if

This response, combined with the low drift internal

f

CLK

increases from 4.9152MHz to 6.144MHz when

oscillator, provides an excellent normal-mode

the SPEED pin is tied high, the data rate increases

rejection of line-cycle interference.

from 80SPS to 100SPS, while notches also increase

Figure 22 (b) shows the same plot, but zooms in on

from 80Hz to 100Hz. Note that these changes are

the 50Hz and 60Hz notches with the SPEED pin tied

only possible when the external clock source is

low (10SPS data rate). With only a ± 3% variation of

applied.

the internal oscillator, over 100dB of normal-mode
rejection is achieved.

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SETTLING TIME DATA FORMAT

DATA RATE

AbruptChangeinExternalV

IN

V

IN

DRDY/DOUT

Startof
Conversion

1stConversion;
includes
unsettledV .

IN

2ndConversion;
V settled,but

IN

digitalfilter
unsettled.

3rdConversion;
V settled,but

IN

digitalfilter
unsettled.

4thConversion;
V settled,but

IN

digitalfilter
unsettled.

5thConversion;
V anddigital

IN

filterboth
settled.

Conversion

Time

DRDY/DOUT 19 18 17

1 2 3 20 21 22 23 24

0

LSBMSB

DataReady

SCLK

NewDataReady

1 2

3

4

Data

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

In certain instances, large changes in input will The ADS1230 outputs 20 bits of data in binary two’s
require settling time. For example, an external complement format. The least significant bit (LSB)
multiplexer in front of the ADS1230 can put large has a weight of 0.5V

REF

/(2

19

– 1). The positive
changes in input voltage by simply switching the full-scale input produces an output code of 7FFFFh
multiplexer input channels. Abrupt changes in the and the negative full-scale input produces an output
input will require four data conversion cycles to code of 800000h. The output clips at these codes for
settle. When continuously converting, five readings signals exceeding full-scale. Table 4 summarizes the
may be necessary in order to settle the data. If the ideal output codes for different input signals.
change in input occurs in the middle of the first

The ADS1230 is a 20-bit ADC. After data conversion

conversion, four more full conversions of the

is completed, applying 20 SCLKs retrieves 20 bits of

fully-settled input are required to get fully-settled

data (MSB first). However, if the SCLKs continue to

data. Discard the first four readings because they

be applied after 20 bits of data are retrieved, the

contain only partially-settled data. Figure 23

DOUT pin outputs four 1s for the 21st through the

illustrates the settling time for the ADS1230 in

24th SCLK, as shown in Figure 24 .

Continuous Conversion mode.

Table 4. Ideal Output Code vs Input Signal

(1)

INPUT SIGNAL V

IN

(AINP – AINN) IDEAL OUTPUT

The ADS1230 data rate is set by the SPEED pin, as
shown in Table 3 . When SPEED is low, the data rate

≥ +0.5V

REF

/Gain 7FFFFh

is nominally 10SPS. This data rate provides the

00001h

(+0.5V

REF

/Gain)/(2

19

– 1)

lowest noise, and also has excellent rejection of both

0 00000h

50Hz and 60Hz line-cycle interference. For

FFFFFh

(–0.5V

REF

/Gain)/(2

19

– 1)

applications requiring fast data rates, setting SPEED

≤ –0.5V

REF

/Gain 80000h

high selects a data rate of nominally 80SPS.

(1) Excludes effects of noise, INL, offset,

Table 3. Data Rate Settings

and gain errors.

DATA RATE

SPEED Internal Oscillator External

PIN or 4.9152MHz Crystal Oscillator

0 10SPS f

CLKIN

/ 491,520

1 80SPS f

CLKIN

/ 61,440

Figure 23. Settling Time in Continuous Conversion Mode

Figure 24. Data Retrieval Format

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DATA READY/DATA OUTPUT ( DRDY/DOUT) DATA RETRIEVAL

SERIAL CLOCK INPUT (SCLK)

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

This digital output pin serves two purposes. First, it The ADS1230 continuously converts the analog input
indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes
Afterwards, on the first rising edge of SCLK, the low, as shown in Figure 25 . After DRDY/DOUT goes
DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying SCLKs.
outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to
(MSB) first. Data are shifted out on each subsequent shift out all 20 bits of data, but the data must be
SCLK rising edge. After all 20 bits have been retrieved before new data are updated (within t

CONV

)
retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data
additional SCLK. It then stays high until new data are retrieval during the update period (t

UPDATE

). If 24
ready. This configuration is useful when polling on SCLKs have been applied, DRDY/DOUT will be high
the status of DRDY/DOUT to determine when to since the last four bits have been appended by '1'.
begin data retrieval. However, if only 20 SCLKs have been applied,

DRDY/DOUT remains at the state of the last bit
shifted out until it is taken high (see t

UPDATE

),

indicating that new data are being updated. To avoid

This digital input shifts serial data out with each

having DRDY/DOUT remain in the state of the last

rising edge. This input has built-in hysteresis, but

bit, the 21st SCLK can be applied to force

care should still be taken to ensure a clean signal.

DRDY/DOUT high, as shown in Figure 26 . This

Glitches or slow-rising signals can cause unwanted

technique is useful when a host controlling the

additional shifting. For this reason, it is best to make

device is polling DRDY/DOUT to determine when

sure the rise and fall times of SCLK are both less

data are ready.

than 50ns.

14

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DRDY/DOUT 19 18

17

1 20

0

LSBMSB

Data

a)20BitsofDataRetrieval

b)24BitsofDataRetrieval

DataReady

SCLK

t

DS

t

CONV

t

SCLK

t

PD

NewDataReady

DRDY/DOUT 19 18 17

1 20 21 22 23 24

2

3

4

0 1

LSBMSB

Data

DataReady

SCLK

NewDataReady

t

SCLK

t

HT

t

UPDATE

t

DS

t

SCLK

t

PD

t

SCLK

t

CONV

t

HT

t

UPDATE

19

1 20 21

18 17 0

Data

21stSCLKtoForce /DOUTHighDRDY

DataReady NewDataReady

DRDY/DOUT

SCLK

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

Figure 25. Data Retrieval Timing

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

DS

DRDY/DOUT low to first SCLK rising edge 0 ns

t

SCLK

SCLK positive or negative pulse width 100 ns

t

PD

SCLK rising edge to new data bit valid: propagation delay 50 ns

t

HT

SCLK rising edge to old data bit valid: hold time 0 ns

t

UPDATE

(1)

Data updating: no readback allowed 39 μ s

SPEED = 1 12.5 ms

t

CONV

(1)

Conversion time (1/data rate)

SPEED = 0 100 ms

(1) Value given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period.

Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards

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OFFSET CALIBRATION

19DRDY/DOUT

SCLK

1

23 24 25 26

20

t

CAL

21 22

3 4

1 2

1918 17 0

DataReadyAfterCalibration

CalibrationBegins

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

During this time, the analog input pins are
disconnected within the ADC and the appropriate

Offset calibration can be initiated at any time to

signal is applied internally to perform the calibration.

remove the ADS1230 inherited offset error. To

When the calibration is completed, DRDY/DOUT

initiate offset calibration, apply at least two additional

goes low, indicating that new data are ready. The

SCLKs after retrieving 20 bits of data plus four bits of

first conversion after a calibration is fully settled and

'1'. Figure 27 shows the timing pattern. The 25th

valid for use. The offset calibration takes exactly the

SCLK keeps DRDY/DOUT high. The falling edge of

same time as specified in (t

CAL

) immediately after the

the 26th SCLK begins the calibration cycle.

falling edge of the 26th SCLK.

Additional SCLK pulses may be sent after the 26th
SCLK; however, activity on SCLK should be
minimized during offset calibration for best results.

Figure 27. Offset-Calibration Timing

SYMBOL DESCRIPTION MIN MAX UNITS

SPEED = 1 101.28 101.29 ms

t

CAL

(1)

First data ready after calibration

SPEED = 0 801.02 801.03 ms

(1) Value given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period. Expect a ± 3% variation when an

internal oscillator is used.

16

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STANDBY MODE

DRDY/DOUT 19 18 17

1 20

0 19

SCLK

StandbyMode

DataReady

t

DSS

t

STANDBY

t

S_RDY

StartConversion

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

When t

STANDBY

has passed with SCLK held high,

Standby mode activates. DRDY/DOUT stays high

Standby mode dramatically reduces power

when Standby mode begins. SCLK must remain high

consumption by shutting down most of the circuitry.

to stay in Standby mode. To exit Standby mode

In Standby mode, the entire analog circuitry is

(wakeup), set SCLK low. The first data after exiting

powered down and only the clock source circuitry is

Standby mode is valid.

awake to reduce the wake-up time from the Standby
mode. To enter Standby mode, simply hold SCLK
high after DRDY/DOUT goes low; see Figure 28 .
Standby mode can be initiated at any time during
readback; it is not necessary to retrieve all 20 bits of
data beforehand.

Figure 28. Standby Mode Timing (can be used for single conversions)

SYMBOL DESCRIPTION MIN MAX UNITS

SPEED = 1 0 12.44 ms

SCLK high after DRDY/DOUT goes

t

DSS

(1)

low to activate Standby mode

SPEED = 0 0 99.94 ms
SPEED = 1 20 μ s

t

STANDBY

(1)

Standby mode activation time

SPEED = 0 20 μ s
SPEED = 1 52.51 52.51 ms

t

S_RDY

(1)

Data ready after exiting Standby mode

SPEED = 0 401.8 401.8 ms

(1) Value given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period. Expect a ± 3% variation when an

internal oscillator is used.

17

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STANDBY MODE WITH

Standby

Mode

Begin
Calibration

DataReady

AfterCalibration

t

STANDBY

t

SC_RDY

DRDY/DOUT 19

1

22 23 24 25

20 21

2 3 4

1

18 17 0 19

SCLK

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

To force an offset-calibration with Standby mode,

OFFSET-CALIBRATION shift 25 SCLKs and bring the SCLK pin high to enter

Standby mode. Offset-calibration then begins after

Offset-calibration can be set to run immediately after

wake-up; Figure 29 shows the appropriate timing.

exiting Standby mode. This option is useful when the

Note the extra time needed after wake-up for

ADS1230 is put in Standby mode for long periods of

calibration before data are ready. The first data after

time, and offset-calibration is desired afterwards to

Standby mode with offset-calibration is fully settled

compensate for temperature or supply voltage

and can be used right away.

changes.

Figure 29. Standby Mode with Offset-Calibration Timing (can be used for single conversions)

SYMBOL DESCRIPTION MIN MAX UNITS

SPEED = 1 103 103 ms

Data ready after exiting Standby mode

t

SC_RDY

(1)

and calibration

SPEED = 0 803 803 ms

(1) Value given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period. Expect a ± 3% variation when an

internal oscillator is used.

18

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POWER-UP SEQUENCE

AVDD

DVDD

PDWN

³ m10 s

POWER-DOWN MODE

DVDD

(1)

Connectto
ADS1230

pin

PDWN

1.2kW

2.2nF

NOTE:(1)AVDDmustbepoweredupatleast10

beforePDWNgoeshigh.

ms

DataReady

Start

Conversion

DRDY/DOUT

SCLK

CLKSource

Wakeup

Power-DownMode

PDWN

t

WAKEUP

t

TS_RDY

t

PDWN

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

When powering up the ADS1230, AVDD and DVDD
must be powered up before the PDWN pin goes
high, as shown in Figure 30 . If PDWN is not
controlled by a microprocessor, a simple RC delay
circuit must be implemented, as shown in Figure 31 .

Figure 30. Power-Up Timing Sequence

Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 20 bits of data
beforehand. Figure 32 shows the wake-up timing
from Power-Down mode.

Figure 31. RC Delay Circuit

Figure 32. Wake-Up Timing from Power-Down Mode

SYMBOL DESCRIPTION MIN TYP UNITS

Internal clock 7.95 μ s

Wake-up time after Power-Down

t

WAKEUP

mode

External clock 0.16 μ s

t

PDWN

(1)

PDWN pulse width 26 μ s

(1) Value given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period. Expect a ± 3% variation when an

internal oscillator is used.

19

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APPLICATION EXAMPLES

Noise−Free Counts +ǒ2

BIT

Eff

Ǔ

ǒ

FS

LC

FS

AD

Ǔ

Weigh Scale System

Noise−Free Counts +ǒ2

(17.5)1)

Ǔ

ǒ

10mV
39mV

Ǔ

+ 95,058

ADS1230

10

5

6

7

8

9

16

15

14

3

13

REFP

CAP

CAP

AINP

AINN

REFN

AVDD DVDD

AGND DGND

DRDY/DOUT

SCLK

PDWN

CLKIN

SPEED

0.1 Fm

0.1 Fm

+-

11 2,4

12 1

MSP430x4xx

orOther

Microprocessor

VDD

GND

GAIN

4

2.7Vto5.3V 3V

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

Where:

Figure 33 shows a typical ADS1230 hook-up as part

of a weigh scale system. In this setup, the ADS1230

BIT

EFF

= effective noise-free bits (17.5 + 1 bit

is configured at a 10SPS data rate. Note that the

from software filtering/averaging)

internal oscillator is used by grounding the CLKIN

FS

LC

= full-scale output of the load cell (10mV)

pin. The user can also apply a 4.9152MHz clock to

FS

AD

= full-scale input of the ADS1230 (39mV,

the CLKIN pin. For a typical 2mV/V load cell, the

when PGA = 128)

maximum output signal is approximately 10mV for a

Therefore:

single +5V excitation voltage. The ADS1230 can
achieve 17.5 noise-free bits at 10SPS when
PGA = 128. With the extra software
filtering/averaging (typically done by a
microprocessor), an extra bit can be expected.

With +5V supply voltage, 95,058 noise-free counts
can be expected from the ADS1230.

Figure 33. Weigh Scale Application

20

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SUMMARY OF SERIAL INTERFACE WAVEFORMS

DRDY/DOUT 19 18

17

1 20

0

LSBMSB

Data

a)20BitsofDataRetrieval

b)24BitsofDataRetrieval

DataReady

SCLK

t

DS

t

CONV

t

SCLK

t

PD

NewDataReady

DRDY/DOUT 19 18 17

1 20 21 22 23 24

2

3

4

0 1

LSBMSB

Data

DataReady

SCLK

NewDataReady

t

SCLK

t

HT

t

UPDATE

t

DS

t

SCLK

t

PD

t

SCLK

t

CONV

t

HT

t

UPDATE

19

1 20 21

18 17 0

Data

21stSCLKtoForce /DOUTHighDRDY

DataReady NewDataReady

DRDY/DOUT

SCLK

DRDY/DOUT 19 18 17

1 20

0 19

SCLK

StandbyMode

DataReady

t

DSS

t

STANDBY

t

S_RDY

StartConversion

c)DataRetrievalwithDRDY/DOUTForcedHighAfterwards

d)StandbyMode/SingleConversions

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

Figure 34. Summary of Data Retrieval Waveforms

21

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21stSCLKtoForce /DOUTHighDRDY

19DRDY/DOUT

SCLK

1

23 24 25 26

20

t

CAL

21 22

3 4

1 2

1918 17 0

DataReadyAfterCalibration

CalibrationBegins

DRDY/DOUT 19 18 17

1 20

0 19

SCLK

StandbyMode

DataReady

t

DSS

t

STANDBY

t

S_RDY

StartConversion

Standby

Mode

Begin
Calibration

DataReady

AfterCalibration

t

STANDBY

t

SC_RDY

DRDY/DOUT 19

1

22 23 24 25

20 21

2 3 4

1

18 17 0 19

SCLK

a)OffsetCalibrationTiming

b)StandbyMode/SingleConversions

c)StandbyMode/SingleConversionswithOffsetCalibration

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

Figure 35. Summary of Standby Mode and Calibration Waveforms

22

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ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2006) to A Revision ................................................................................................... Page

• Deleted min and max values for Data Rate Internal Oscillator ............................................................................................. 3

• Changed Normal Mode Rejection format and added min values ......................................................................................... 3

• Changed Voltage Reference Input section ......................................................................................................................... 11

• Changed Figure 19 ............................................................................................................................................................ 11

• Deleted second sentence of Serial Clock Input (SCLK) section ........................................................................................ 14

• Added Power-Up Sequence section with new text and two new figures (Figure 30 and Figure 31 ) ................................. 19

• Changed Figure 33 ............................................................................................................................................................ 20

23

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PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

ADS1230IPW ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

ADS1230IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

ADS1230IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

ADS1230IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

9-Jul-2007

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

M

0,10

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

28

9,80

9,60

24

7,90

7,70

2016

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

8

0,19

4,30

4,50

7

0,15

14

A

1

1,20 MAX

14

5,10

4,90

8

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

0°–8°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
Low Power www.ti.com/lpw Video & Imaging www.ti.com/video

Wireless

Wireless www.ti.com/wireless

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