TEXAS INSTRUMENTS ADS1218 Technical data
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ADS1218
SBAS187 – SEPTEMBER 2001
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
with FLASH Memory
ADS1218
FEATURES
● 24 BITS NO MISSING CODES
● 0.0015% INL
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● 4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
● PGA FROM 1 TO 128
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
●
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/°C
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
● ON-CHIP CALIBRATION
● PIN COMPATIBLE WITH ADS1216
● SPI™ COMPATIBLE
● 2.7V TO 5.25V
● < 1mW POWER CONSUMPTION
DESCRIPTION
The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-toDigital (A/D) converter with 24-bit resolution and FLASH memory operating
from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to
24 bits of no missing code performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering can be selected
to provide a very high input impedance for direct connection to transducers
or low-level voltage signals. Burn out current sources are provided that allow
for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/
A) converter provides an offset correction with a range of 50% of the FSR
(Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to
128 with an effective resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order delta-sigma modulator and
programmable sinc filter. The reference input is differential and can be used
for ratiometric conversion. The on-board current DACs (Digital-to-Analog
Converters) operate independently with the maximum current set by an
external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O are also provided
that can be used for input or output. The ADS1218 is designed for high-resolution
measurement applications in smart transmitters, industrial process control, weight
scales, chromatography, and portable instrumentation.
AGND AV
V
R
REFOUTVRCAPVREF+VREF–
DD
DAC
X
X
IN
OUT
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● LIQUID /GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES
● PRESSURE TRANSDUCERS
SPI is a registered trademark of Motorola.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
IDAC2
IDAC1
A
A
A
A
A
A
A
A
A
INCOM
0
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
AV
DD
2µA
IN+
MUX
IN–
2µA
AGND
DD
www.ti.com
8-Bit
IDAC
8-Bit
IDAC
Offset
DAC
A = 1:128
+
BUF PGA
Digital I/O
Interface
D7...D0
Clock Generator
Registers
Controller
DSYNCPDWN RESET DRDYBUFENDGNDDV
RAM
4K Bytes
FLASH
Serial Interface
WREN
POL
SCLK
D
IN
D
OUT
CS
2nd-Order
Modulator
1.25V or
2.5V
Reference
Program-
mable
Digital
Filter
Copyright © 2001, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...................................................................... –0.3V to +6V
DV
to DGND...................................................................... –0.3V to +6V
DD
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
................................................................... GND –0.5V to AVDD + 0.5V
IN
AV
to DVDD........................................................................... –6V to +6V
DD
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND....................................–0.3V to DV
Digital Output Voltage to GND ................................. –0.3V to DV
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(1)
DD
DD
+ 0.3V
+ 0.3V
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments
recommends that all integrated circuits be handled and stored using
appropriate ESD protection methods.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
ADS1218Y TQFP-48 PFB –40°C to +85°C ADS1218Y ADS1218Y/250 Tape and Reel, 250
" """"ADS1218Y/2K Tape and Reel, 2000
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS1218Y/2K” will get a single 2000-piece Tape and Reel.
SPECIFIED
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes sinc
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
(1)
Gain Error After Calibration 0.005 %
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
MIN
(1)
(1)
to T
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
(AIN0 – AIN7, A
INCOM
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 150kΩ, f
DAC
DATA
= 10Hz,
ADS1218
)
+ 0.1 V
Buffer ON AGND + 0.05 AV
DATA
DATA
DATA
/(2 • PGA) V
REF
3
DD
– 1.5 V
DD
/PGA V
REF
24 Bits
Hz
Hz
Hz
Before Calibration 7.5 ppm of FS
0.02 ppm of FS/°C
0.5 ppm/°C
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
= 50Hz, f
SIG
f
= 60Hz, f
SIG
= 10Hz 130 dB
DATA
= 50Hz 120 dB
DATA
= 60Hz 120 dB
DATA
= 50Hz 100 dB
DATA
= 60Hz 100 dB
DATA
(2)
OUT
/∆VDD)
80 95 dB
2
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 1 at 25°C 2.495 2.50 2.505 V
Short-Circuit Current Source 8mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 5 ppm/°C
Noise BW = 0.1Hz to 100Hz 10 µVp-p
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance see Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DVDD = 5V 180 275 µA
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 1.8 2.8 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
to T
MIN
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 150kΩ, f
DAC
ADS1218
V
≡ (REF IN+) – (REF IN–) 0.1 2.5 2.6 V
REF
= 60Hz, f
(3)
VREFCM
V
REF
= 60Hz 120 dB
DATA
= 2.5V 1.3 µA
DD
REF HI = 0 1.25 V
= 150kΩ, Range = 1 0.5 mA
DAC
R
= 150kΩ, Range = 2 1 mA
DAC
R
= 150kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
= 10kΩ Indefinite
DAC
R
= 0Ω 10 Minutes
DAC
= 150kΩ 8Bits
DAC
= AVDD/2 400 ppm/V
OUT
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 175 275 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 500 750 µA
DD
4.75 5.25 V
0.25 %
15 ppm/°C
– 1V
DD
PGA = 1, Buffer ON 250 350 µA
PGA = 128, Buffer ON 900 1375 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 5V
= 5V 150 µA
DD
230 µA
PDWN= LOW 1 nA
I
OFF, DVDD = 5V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
=10Hz,
V
ADS1218
SBAS187
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–) See Block Diagram ±V
Input Impedance Buffer OFF 5/PGA M Ω
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes 24 Bits
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
(1)
(1)
Gain Error After Calibration 0.010 %
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise see Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 0 at 25°C 1.245 1.25 1.255 V
Short-Circuit Current Source 3mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 5 ppm/°C
Noise BW = 0.1Hz to 100Hz 10 µVp-p
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance see Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
MIN
(AIN0 – AIN7, A
(1)
(3)
to T
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
)
INCOM
V
REF
VREFCM
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 75kΩ, f
DAC
ADS1218
+ 0.1 V
Buffer ON AGND + 0.05 AV
DATA
DATA
DATA
/(2 • PGA) V
REF
DD
– 1.5 V
DD
/PGA V
REF
Before Calibration 15 ppm of FS
0.04 ppm of FS/°C
1.0 ppm/°C
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
= 50Hz, f
SIG
f
= 60Hz, f
SIG
≡ (REF IN+) – (REF IN–) 0.1 1.25 V
= 60Hz, f
V
REF
= 75kΩ, Range = 1 0.5 mA
DAC
R
= 75kΩ, Range = 2 1 mA
DAC
R
= 75kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
DAC
R
DAC
OUT
= 10Hz 130 dB
DATA
= 50Hz 120 dB
DATA
= 60Hz 120 dB
DATA
= 50Hz 100 dB
DATA
= 60Hz 100 dB
DATA
(2)
/∆VDD)
OUT
= 60Hz 120 dB
DATA
= 1.25V 0.65 µA
75 90 dB
DD
= 10kΩ Indefinite
= 0Ω 10 Minute
DAC
= 75kΩ 8Bits
– 1V
DD
= AVDD/2 600 ppm/V
0.25 %
15 ppm/°C
DATA
=10Hz,
Hz
Hz
Hz
V
4
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DV
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 0.8 1.4 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
to T
MIN
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
DAC
= 75kΩ, f
ADS1218
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 160 250 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 450 700 µA
DD
2.7 3.3 V
PGA = 1, Buffer ON 230 325 µA
PGA = 128, Buffer ON 850 1325 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 3V
= 3V 90 200 µA
DD
= 3V 75 µA
DD
113 µA
PDWN = 0 1 nA
I
OFF, DVDD = 3V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
=10Hz,
DIGITAL CHARACTERISTICS: T
MIN
to T
, DVDD = 2.7V to 5.25V
MAX
PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input/Output
Logic Family CMOS
Logic Level: V
Input Leakage: I
Master Clock Rate: f
IH
V
IL
V
OH
V
OL
IH
I
IL
Master Clock Period: t
OSC
OSC
0.8 • DV
DD
DGND 0.2 • DV
IOH = 1mA DVDD – 0.4 V
IOL = 1mA DGND DGND + 0.4 V
VI = DV
DD
(1)
(1)
VI = 0 –10 µA
15MHz
1/f
OSC
200 1000 ns
DV
DD
DD
10 µA
V
V
NOTE: (1) For FLASH E/W operations, the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be:
2.3MHz < F
FLASH CHARACTERISTICS: T
< 4.13MHz.
OSC
MIN
to T
, DVDD = 2.7V to 5.25V, unless otherwise specified.
MAX
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Current
Page Write DV
Page Read DV
Endurance 100,000 E/W Cycles
= 5V, During WR2F Command 6.5 mA
DD
DV
= 3V, During WR2F Command 3.75 mA
DD
= 5V, During RF2R Command 4.0 mA
DD
DV
= 3V, During RF2R Command 1.2 mA
DD
Data Retention at 25°C 100 Years
DV
for Erase/Write 2.7 5.25 V
DD
ADS1218
SBAS187
5
PIN CONFIGURATION (TQFP-48)
AGND
V
REFOUT
V
V
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF–
OUTDIN
D
SCLKCSDRDY
DVDDDGND
DSYNC
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
ADS1218
43
44
45
46
47
48
12345678910112512
0
1
2
3
4
5
IN
IN
IN
A
A
AV
DD
AGND
IN
IN
IN
A
A
A
A
POL
6
IN
A
PDWN
7
IN
A
OUTXIN
X
INCOM
A
AGND
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
WREN
R
DAC
IDAC2
IDAC1
V
RCAP
AV
DD
PIN DESCRIPTIONS
PIN
NUMBER NAME DESCRIPTION
1AV
DD
2 AGND Analog Ground
3A
4A
5A
6A
7A
8A
9A
IN
IN
IN
IN
IN
IN
IN
10 AIN7 Analog Input 7
11 A
INCOM
12 AGND Analog Ground
13 AV
14 V
DD
RCAP
15 IDAC1 Current DAC1 Output
16 IDAC2 Current DAC2 Output
17 R
DAC
18 WREN Active High, FLASH Write Enable
19-22 DGND Digital Ground
23 BUFEN Buffer Enable
Analog Power Supply
0 Analog Input 0
1 Analog Input 1
2 Analog Input 2
3 Analog Input 3
4 Analog Input 4
5 Analog Input 5
6 Analog Input 6
Analog Input Common
Analog Power Supply
V
Bypass CAP
REF
Current DAC Resistor
PIN
NUMBER NAME DESCRIPTION
24 RESET Active LOW, resets the entire chip.
25 X
26 X
IN
OUT
Clock Input
Clock Output, used with crystal or resonator.
27 PDWN Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
28 POL Serial Clock Polarity
29 DSYNC Active LOW, Synchronization Control
30 DGND Digital Ground
31 DV
Digital Power Supply
DD
32 DRDY Active LOW, Data Ready
33 CS Active LOW, Chip Select
34 SCLK Serial Clock, Schmitt Trigger
35 D
36 D
IN
OUT
Serial Data Input, Schmitt Trigger
Serial Data Output
37-44 D0-D7 Digital I/O 0-7
45 AGND Analog Ground
46 V
47 V
48 V
REFOUT
REF+
REF–
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
6
ADS1218
SBAS187
TIMING SPECIFICATIONS
CS
t
SCLK
(POL = 0)
SCLK
(POL = 1)
3
t
4
D
IN
MSB
t
1
t
5
t
2
t
6
t
2
t
10
t
11
LSB
t
D
OUT
(Command or Command and Data)
7
MSB
t
8
(1)
LSB
t
9
(1)
NOTE: (1) Bit Order = 0.
ADS1218
SCLK Reset Waveform
Resets On
Falling Edge
t
13
t
13
SCLK
t
12
t
14
t
15
t
RESET, DSYNC, PDWN
DDR Update Timing
t
17
DRDY
TIMING SPECIFICATION TABLES
SPEC DESCRIPTION MIN MAX UNITS
t
1
t
2
t
3
t
4
t
5
t
6
(1)
t
7
(1)
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
NOTE: (1) Load = 20pF 10kΩ to DGND.
SCLK Period 4t
3 DRDY Periods
SCLK Pulse Width, HIGH and LOW 200 ns
CS LOW to first SCLK Edge; Setup Time 0 ns
DIN Valid to SCLK Edge; Setup Time 50 ns
Valid DIN to SCLK Edge; Hold Time 50 ns
Delay between last SCLK edge for DIN and first SCLK
edge for D
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OUT
:
CSREG, CSRAMX, CSRAM 200 t
CHKARAM, CHKARAMX 1100 t
SCLK Edge to Valid New D
SCLK Edge to D
Last SCLK Edge to D
NOTE: D
CS LOW time after final SCLK edge 0 ns
OUT
goes tri-state immediately when CS goes HIGH.
OUT
OUT
, Hold Time 0 ns
Tri-State 6 10 t
OUT
50 ns
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, SLEEP,
RDATA, RDATAC, STOPC 4 t
DSYNC, RESET 16 t
CSFL 33,000 t
CREG, CRAM 220 t
RF2R 1090 t
CREGA 1600 t
WR2F
76,850 (SPEED = 0)
101,050 (SPEED = 1)
4t
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Command, SCLK, or Pin) 16 t
SCLK Reset, First HIGH Pulse 300 500 t
SCLK Reset, LOW Pulse 5 t
SCLK Reset, Second HIGH Pulse 550 750 t
SCLK Reset, Third HIGH Pulse 1050 1250 t
Pulse Width 4t
DOR Data Not Valid 4 t
16
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
t
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
ADS1218
SBAS187
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter, V
= 1.25V, Buffer OFF
REF
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
PGA1
21
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
PGA32 PGA64 PGA128
PGA16
Sinc3 Filter, Buffer ON
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
PGA1
21
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
12
PGA32
PGA16
Sinc
3
Filter, V
PGA64
REF
PGA128
= 1.25V, Buffer ON
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
8
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA32
PGA16
PGA64
PGA128
15
14
13
Sinc2 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
FAST SETTLING FILTER
22
21
20
19
18
17
16
ENOB (rms)
15
14
13
Fast Settling Filter
12
f
f
DATA
1500
MOD
0 500 1000 1500 2000
Decimation Ratio =
ADS1218
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
CMRR vs FREQUENCY
Frequency of CM Signal (Hz)
1 10 100 1k 10k 100k
CMRR (dB)
50
0
–50
–100
–150
–200
OFFSET vs TEMPERATURE
Offset (ppm of FS)
PGA1
PGA128
PGA64
Temperature (°C)
–50 –30 10–10 30 50 70 90
PGA16
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Noise (rms, ppm of FS)
0.1
0
–2.5 –1.5 0.5–0.5 1.5 2.5
120
110
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
110 1k100 10k 100k
NOISE vs INPUT SIGNAL
(V)
V
IN
PSRR vs FREQUENCY
Frequency of Power Supply (Hz)
1.00010
1.00006
1.00002
0.99998
0.99994
Gain (Normalized)
0.99990
0.99986
–50 –30 10–10 30 50 70 90
ADS1218
SBAS187
GAIN vs TEMPERATURE
Temperature (°C)
10
–2
INL (ppm of FS)
–4
–6
–8
–10
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
8
6
4
+85°C
2
0
–2.5 –2 –1 –0.5–1.5 0 0.5 1 1.5 2 2.5
–40°C
+25°C
(V)
V
IN
9
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