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ADS1218
SBAS187 – SEPTEMBER 2001
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
with FLASH Memory
ADS1218
FEATURES
● 24 BITS NO MISSING CODES
● 0.0015% INL
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● 4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
● PGA FROM 1 TO 128
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
●
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/°C
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
● ON-CHIP CALIBRATION
● PIN COMPATIBLE WITH ADS1216
● SPI™ COMPATIBLE
● 2.7V TO 5.25V
● < 1mW POWER CONSUMPTION
DESCRIPTION
The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-toDigital (A/D) converter with 24-bit resolution and FLASH memory operating
from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to
24 bits of no missing code performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering can be selected
to provide a very high input impedance for direct connection to transducers
or low-level voltage signals. Burn out current sources are provided that allow
for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/
A) converter provides an offset correction with a range of 50% of the FSR
(Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to
128 with an effective resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order delta-sigma modulator and
programmable sinc filter. The reference input is differential and can be used
for ratiometric conversion. The on-board current DACs (Digital-to-Analog
Converters) operate independently with the maximum current set by an
external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O are also provided
that can be used for input or output. The ADS1218 is designed for high-resolution
measurement applications in smart transmitters, industrial process control, weight
scales, chromatography, and portable instrumentation.
AGND AV
V
R
REFOUTVRCAPVREF+VREF–
DD
DAC
X
X
IN
OUT
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● LIQUID /GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES
● PRESSURE TRANSDUCERS
SPI is a registered trademark of Motorola.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
IDAC2
IDAC1
A
A
A
A
A
A
A
A
A
INCOM
0
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
AV
DD
2µA
IN+
MUX
IN–
2µA
AGND
DD
www.ti.com
8-Bit
IDAC
8-Bit
IDAC
Offset
DAC
A = 1:128
+
BUF PGA
Digital I/O
Interface
D7...D0
Clock Generator
Registers
Controller
DSYNCPDWN RESET DRDYBUFENDGNDDV
RAM
4K Bytes
FLASH
Serial Interface
WREN
POL
SCLK
D
IN
D
OUT
CS
2nd-Order
Modulator
1.25V or
2.5V
Reference
Program-
mable
Digital
Filter
Copyright © 2001, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...................................................................... –0.3V to +6V
DV
to DGND...................................................................... –0.3V to +6V
DD
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
................................................................... GND –0.5V to AVDD + 0.5V
IN
AV
to DVDD........................................................................... –6V to +6V
DD
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND....................................–0.3V to DV
Digital Output Voltage to GND ................................. –0.3V to DV
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(1)
DD
DD
+ 0.3V
+ 0.3V
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments
recommends that all integrated circuits be handled and stored using
appropriate ESD protection methods.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
ADS1218Y TQFP-48 PFB –40°C to +85°C ADS1218Y ADS1218Y/250 Tape and Reel, 250
" """"ADS1218Y/2K Tape and Reel, 2000
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS1218Y/2K” will get a single 2000-piece Tape and Reel.
SPECIFIED
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes sinc
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
(1)
Gain Error After Calibration 0.005 %
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
MIN
(1)
(1)
to T
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
(AIN0 – AIN7, A
INCOM
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 150kΩ, f
DAC
DATA
= 10Hz,
ADS1218
)
+ 0.1 V
Buffer ON AGND + 0.05 AV
DATA
DATA
DATA
/(2 • PGA) V
REF
3
DD
– 1.5 V
DD
/PGA V
REF
24 Bits
Hz
Hz
Hz
Before Calibration 7.5 ppm of FS
0.02 ppm of FS/°C
0.5 ppm/°C
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
= 50Hz, f
SIG
f
= 60Hz, f
SIG
= 10Hz 130 dB
DATA
= 50Hz 120 dB
DATA
= 60Hz 120 dB
DATA
= 50Hz 100 dB
DATA
= 60Hz 100 dB
DATA
(2)
OUT
/∆VDD)
80 95 dB
2
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 1 at 25°C 2.495 2.50 2.505 V
Short-Circuit Current Source 8mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 5 ppm/°C
Noise BW = 0.1Hz to 100Hz 10 µVp-p
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance see Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DVDD = 5V 180 275 µA
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 1.8 2.8 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
to T
MIN
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 150kΩ, f
DAC
ADS1218
V
≡ (REF IN+) – (REF IN–) 0.1 2.5 2.6 V
REF
= 60Hz, f
(3)
VREFCM
V
REF
= 60Hz 120 dB
DATA
= 2.5V 1.3 µA
DD
REF HI = 0 1.25 V
= 150kΩ, Range = 1 0.5 mA
DAC
R
= 150kΩ, Range = 2 1 mA
DAC
R
= 150kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
= 10kΩ Indefinite
DAC
R
= 0Ω 10 Minutes
DAC
= 150kΩ 8Bits
DAC
= AVDD/2 400 ppm/V
OUT
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 175 275 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 500 750 µA
DD
4.75 5.25 V
0.25 %
15 ppm/°C
– 1V
DD
PGA = 1, Buffer ON 250 350 µA
PGA = 128, Buffer ON 900 1375 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 5V
= 5V 150 µA
DD
230 µA
PDWN= LOW 1 nA
I
OFF, DVDD = 5V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
=10Hz,
V
ADS1218
SBAS187
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–) See Block Diagram ±V
Input Impedance Buffer OFF 5/PGA M Ω
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes 24 Bits
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
(1)
(1)
Gain Error After Calibration 0.010 %
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise see Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 0 at 25°C 1.245 1.25 1.255 V
Short-Circuit Current Source 3mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 5 ppm/°C
Noise BW = 0.1Hz to 100Hz 10 µVp-p
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance see Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
MIN
(AIN0 – AIN7, A
(1)
(3)
to T
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
)
INCOM
V
REF
VREFCM
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
= 75kΩ, f
DAC
ADS1218
+ 0.1 V
Buffer ON AGND + 0.05 AV
DATA
DATA
DATA
/(2 • PGA) V
REF
DD
– 1.5 V
DD
/PGA V
REF
Before Calibration 15 ppm of FS
0.04 ppm of FS/°C
1.0 ppm/°C
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
= 50Hz, f
SIG
f
= 60Hz, f
SIG
≡ (REF IN+) – (REF IN–) 0.1 1.25 V
= 60Hz, f
V
REF
= 75kΩ, Range = 1 0.5 mA
DAC
R
= 75kΩ, Range = 2 1 mA
DAC
R
= 75kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
DAC
R
DAC
OUT
= 10Hz 130 dB
DATA
= 50Hz 120 dB
DATA
= 60Hz 120 dB
DATA
= 50Hz 100 dB
DATA
= 60Hz 100 dB
DATA
(2)
/∆VDD)
OUT
= 60Hz 120 dB
DATA
= 1.25V 0.65 µA
75 90 dB
DD
= 10kΩ Indefinite
= 0Ω 10 Minute
DAC
= 75kΩ 8Bits
– 1V
DD
= AVDD/2 600 ppm/V
0.25 %
15 ppm/°C
DATA
=10Hz,
Hz
Hz
Hz
V
4
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DV
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 0.8 1.4 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
to T
MIN
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, f
MOD
= 2.4576MHz, PGA = 1, Buffer ON, R
OSC
DAC
= 75kΩ, f
ADS1218
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 160 250 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 450 700 µA
DD
2.7 3.3 V
PGA = 1, Buffer ON 230 325 µA
PGA = 128, Buffer ON 850 1325 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 3V
= 3V 90 200 µA
DD
= 3V 75 µA
DD
113 µA
PDWN = 0 1 nA
I
OFF, DVDD = 3V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
=10Hz,
DIGITAL CHARACTERISTICS: T
MIN
to T
, DVDD = 2.7V to 5.25V
MAX
PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input/Output
Logic Family CMOS
Logic Level: V
Input Leakage: I
Master Clock Rate: f
IH
V
IL
V
OH
V
OL
IH
I
IL
Master Clock Period: t
OSC
OSC
0.8 • DV
DD
DGND 0.2 • DV
IOH = 1mA DVDD – 0.4 V
IOL = 1mA DGND DGND + 0.4 V
VI = DV
DD
(1)
(1)
VI = 0 –10 µA
15MHz
1/f
OSC
200 1000 ns
DV
DD
DD
10 µA
V
V
NOTE: (1) For FLASH E/W operations, the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be:
2.3MHz < F
FLASH CHARACTERISTICS: T
< 4.13MHz.
OSC
MIN
to T
, DVDD = 2.7V to 5.25V, unless otherwise specified.
MAX
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Current
Page Write DV
Page Read DV
Endurance 100,000 E/W Cycles
= 5V, During WR2F Command 6.5 mA
DD
DV
= 3V, During WR2F Command 3.75 mA
DD
= 5V, During RF2R Command 4.0 mA
DD
DV
= 3V, During RF2R Command 1.2 mA
DD
Data Retention at 25°C 100 Years
DV
for Erase/Write 2.7 5.25 V
DD
ADS1218
SBAS187
5
PIN CONFIGURATION (TQFP-48)
AGND
V
REFOUT
V
V
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF–
OUTDIN
D
SCLKCSDRDY
DVDDDGND
DSYNC
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
ADS1218
43
44
45
46
47
48
12345678910112512
0
1
2
3
4
5
IN
IN
IN
A
A
AV
DD
AGND
IN
IN
IN
A
A
A
A
POL
6
IN
A
PDWN
7
IN
A
OUTXIN
X
INCOM
A
AGND
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
WREN
R
DAC
IDAC2
IDAC1
V
RCAP
AV
DD
PIN DESCRIPTIONS
PIN
NUMBER NAME DESCRIPTION
1AV
DD
2 AGND Analog Ground
3A
4A
5A
6A
7A
8A
9A
IN
IN
IN
IN
IN
IN
IN
10 AIN7 Analog Input 7
11 A
INCOM
12 AGND Analog Ground
13 AV
14 V
DD
RCAP
15 IDAC1 Current DAC1 Output
16 IDAC2 Current DAC2 Output
17 R
DAC
18 WREN Active High, FLASH Write Enable
19-22 DGND Digital Ground
23 BUFEN Buffer Enable
Analog Power Supply
0 Analog Input 0
1 Analog Input 1
2 Analog Input 2
3 Analog Input 3
4 Analog Input 4
5 Analog Input 5
6 Analog Input 6
Analog Input Common
Analog Power Supply
V
Bypass CAP
REF
Current DAC Resistor
PIN
NUMBER NAME DESCRIPTION
24 RESET Active LOW, resets the entire chip.
25 X
26 X
IN
OUT
Clock Input
Clock Output, used with crystal or resonator.
27 PDWN Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
28 POL Serial Clock Polarity
29 DSYNC Active LOW, Synchronization Control
30 DGND Digital Ground
31 DV
Digital Power Supply
DD
32 DRDY Active LOW, Data Ready
33 CS Active LOW, Chip Select
34 SCLK Serial Clock, Schmitt Trigger
35 D
36 D
IN
OUT
Serial Data Input, Schmitt Trigger
Serial Data Output
37-44 D0-D7 Digital I/O 0-7
45 AGND Analog Ground
46 V
47 V
48 V
REFOUT
REF+
REF–
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
6
ADS1218
SBAS187
TIMING SPECIFICATIONS
CS
t
SCLK
(POL = 0)
SCLK
(POL = 1)
3
t
4
D
IN
MSB
t
1
t
5
t
2
t
6
t
2
t
10
t
11
LSB
t
D
OUT
(Command or Command and Data)
7
MSB
t
8
(1)
LSB
t
9
(1)
NOTE: (1) Bit Order = 0.
ADS1218
SCLK Reset Waveform
Resets On
Falling Edge
t
13
t
13
SCLK
t
12
t
14
t
15
t
RESET, DSYNC, PDWN
DDR Update Timing
t
17
DRDY
TIMING SPECIFICATION TABLES
SPEC DESCRIPTION MIN MAX UNITS
t
1
t
2
t
3
t
4
t
5
t
6
(1)
t
7
(1)
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
NOTE: (1) Load = 20pF 10kΩ to DGND.
SCLK Period 4t
3 DRDY Periods
SCLK Pulse Width, HIGH and LOW 200 ns
CS LOW to first SCLK Edge; Setup Time 0 ns
DIN Valid to SCLK Edge; Setup Time 50 ns
Valid DIN to SCLK Edge; Hold Time 50 ns
Delay between last SCLK edge for DIN and first SCLK
edge for D
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OUT
:
CSREG, CSRAMX, CSRAM 200 t
CHKARAM, CHKARAMX 1100 t
SCLK Edge to Valid New D
SCLK Edge to D
Last SCLK Edge to D
NOTE: D
CS LOW time after final SCLK edge 0 ns
OUT
goes tri-state immediately when CS goes HIGH.
OUT
OUT
, Hold Time 0 ns
Tri-State 6 10 t
OUT
50 ns
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, SLEEP,
RDATA, RDATAC, STOPC 4 t
DSYNC, RESET 16 t
CSFL 33,000 t
CREG, CRAM 220 t
RF2R 1090 t
CREGA 1600 t
WR2F
76,850 (SPEED = 0)
101,050 (SPEED = 1)
4t
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Command, SCLK, or Pin) 16 t
SCLK Reset, First HIGH Pulse 300 500 t
SCLK Reset, LOW Pulse 5 t
SCLK Reset, Second HIGH Pulse 550 750 t
SCLK Reset, Third HIGH Pulse 1050 1250 t
Pulse Width 4t
DOR Data Not Valid 4 t
16
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
t
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
Periods
OSC
ADS1218
SBAS187
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter, V
= 1.25V, Buffer OFF
REF
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
PGA1
21
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
PGA32 PGA64 PGA128
PGA16
Sinc3 Filter, Buffer ON
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
PGA1
21
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
12
PGA32
PGA16
Sinc
3
Filter, V
PGA64
REF
PGA128
= 1.25V, Buffer ON
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
8
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA32
PGA16
PGA64
PGA128
15
14
13
Sinc2 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
FAST SETTLING FILTER
22
21
20
19
18
17
16
ENOB (rms)
15
14
13
Fast Settling Filter
12
f
f
DATA
1500
MOD
0 500 1000 1500 2000
Decimation Ratio =
ADS1218
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
CMRR vs FREQUENCY
Frequency of CM Signal (Hz)
1 10 100 1k 10k 100k
CMRR (dB)
50
0
–50
–100
–150
–200
OFFSET vs TEMPERATURE
Offset (ppm of FS)
PGA1
PGA128
PGA64
Temperature (°C)
–50 –30 10–10 30 50 70 90
PGA16
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Noise (rms, ppm of FS)
0.1
0
–2.5 –1.5 0.5–0.5 1.5 2.5
120
110
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
110 1k100 10k 100k
NOISE vs INPUT SIGNAL
(V)
V
IN
PSRR vs FREQUENCY
Frequency of Power Supply (Hz)
1.00010
1.00006
1.00002
0.99998
0.99994
Gain (Normalized)
0.99990
0.99986
–50 –30 10–10 30 50 70 90
ADS1218
SBAS187
GAIN vs TEMPERATURE
Temperature (°C)
10
–2
INL (ppm of FS)
–4
–6
–8
–10
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
8
6
4
+85°C
2
0
–2.5 –2 –1 –0.5–1.5 0 0.5 1 1.5 2 2.5
–40°C
+25°C
(V)
V
IN
9
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
250
CURRENT vs TEMPERATURE
I
DIGITAL
200
150
100
Current (µA)
I
ANALOG
I
DIGITAL
I
ANALOG
50
0
–50 –30 10–10 30 50 70 90
Temperature (°C)
DIGITAL CURRENT
400
350
300
250
SPEED = 0
Normal
= 2.45MHz
f
OSC
SLEEP
= 4.91MHz
f
OSC
Normal
= 4.91MHz
f
OSC
200
150
Current (µA)
100
50
Power
Down
SLEEP
= 2.45MHz
f
OSC
0
3.0 4.0 5.0
V
(V)
DD
900
800
700
AVDD = 5V, Buffer = ON
Buffer = OFF
600
ADC CURRENT vs PGA
500
(µA)
I
ADC
400
AVDD = 3V, Buffer = ON
Buffer = OFF
300
200
100
0
01 824 3216 12864
PGA Setting
HISTOGRAM OF OUTPUT DATA
4500
4000
3500
3000
2500
2000
1500
Number of Occurrences
1000
500
0
–2
–1.5 –1 –0.5 0 0.5 1 1.5 2
ppm of FS
vs LOAD CURRENT
V
2.55
REFOUT
(V)
2.50
REFOUT
V
2.45
–0.5 0 0.5 1.0 1.5 2.0 2.5
Current Load (mA)
V
REFOUT
10
200
OFFSET DAC - OFFSET vs TEMPERATURE
170
140
110
80
50
20
–10
Offset (ppm of FSR)
–40
–70
–100
–50 –30 10–10 30 50 70 90
Temperature (°C)
ADS1218
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
1.000
1.000
0.999
0.999
0.998
IDAC
ROUT
vs V
OUT
VDD – V
OUT
(V)
012345
I
OUT
(Normalized)
+85°C
–40°C
+25°C
3000
2000
1000
0
–1000
–2000
–3000
–4000
–5000
–6000
IDAC MATCHING vs TEMPERATURE
IDAC Match (ppm)
Temperature (°C)
–50 –30 10–10 30 50 70 90
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
IDAC INTEGRAL NON-LINEARITY
RANGE = 1, R
DAC
= 150kΩ, V
REF
= 2.5V
IDAC Code
0 25532 64 96 128 160 192 224
INL (LSB)
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
Normalized Gain
0.99988
0.99984
0.99980
0.99976
–50 –30 10–10 30 50 70 90
1.01
1.005
1
OFFSET DAC - GAIN vs TEMPERATURE
Temperature (°C)
IDAC NORMALIZED vs TEMPERATURE
(Normalized)
0.995
OUT
I
0.99
0.985
–50 –30 10–10 30 50 70 90
Temperature (°C)
IDAC DIFFERENTIAL NON-LINEARITY
0.5
RANGE = 1, R
= 150kΩ, V
DAC
0.4
0.3
0.2
0.1
0
–0.1
DNL (LSB)
–0.2
–0.3
–0.4
–0.5
ADS1218
SBAS187
025532 64 96 128 160 192 224
IDAC Code
REF
= 2.5V
11
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of
differential inputs to be selected on any of the input channels, as shown in Figure 1. For example, if channel 1 is
selected as the positive differential input channel, any other
channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight
fully differential input channels.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the input pins.
BURNOUT CURRENT SOURCES
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open
circuit (full-scale reading) or short circuit (0V differential
reading) on the selected input differential pair.
INPUT BUFFER
The input impedance of the ADS1218 without the buffer
is 5MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the BUFEN pin
with the state of the BUFFER bit in the ACR register.
A
A
A
A
AIN3
A
A
A
A
INCOM
0
IN
IDAC1 AND IDAC2
The ADS1218 has two 8-bit current output DACs that can be
1
IN
2
IN
AV
DD
Burnout Current Source On
controlled independently. The output current is set with
R
, the range select bits in the ACR register, and the 8-bit
DAC
digital value in the IDAC register. The output current
= V
REF
/(8 • R
= 2.5V and R
RANGE–1
)(2
DAC
= 150kΩ to AGND the full-scale output
DAC
)(DAC CODE). With V
REFOUT
can be selected to be 0.5, 1, or 2mA. The compliance voltage
range is 0 to within 1V of AVDD. When the internal voltage
reference of the ADS1218 is used, it is the reference for the
4
IN
IDAC. An external reference may be used for the IDACs by
disabling the internal reference and tying the external refer-
5
ence input to the V
IN
6
IN
7
IN
Burnout Current Source On
AGND
IDAC1
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually
improve the effective resolution of the A/D converter. For
instance, with a PGA of 1 on a 5V full-scale range, the A/D
REFOUT
pin.
converter can resolve to 1µV. With a PGA of 128, on a 40mV
full-scale range, the A/D converter can resolve to 75nV. With
a PGA of 1 on a 5V full-scale range, it would require a 26-bit
A/D converter to resolve 75nV.
FIGURE 1. Input Multiplexer Configuration.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to
all 1s, the diode is connected to the input of the A/D
converter. All other channels are open. The anode of the
diode is connected to the positive input of the A/D converter,
and the cathode of the diode is connected to negative input
of the A/D converter. The output of IDAC1 is connected to
the anode to bias the diode and the cathode of the diode is
also connected to ground to complete the circuit.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode.
12
PGA OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign
and the seven LSBs provide the magnitude of the offset. Using
the ODAC register does not reduce the performance of the
A/D converter.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (f
the external clock (f
). The frequency division is deter-
OSC
) that is derived from
MOD
mined by the SPEED bit in the SETUP register.
SPEED BIT f
0f
1f
OSC
OSC
MOD
/ 128
/256
ADS1218
SBAS187
CALIBRATION
The offset and gain errors in the ADS1218, or the complete
system, can be reduced with calibration. Internal calibration of
the ADS1218 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven t
periods to complete. Therefore, it takes 14 t
DATA
DATA
periods to complete both an offset and gain calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven t
periods to complete.
DATA
Calibration should be performed after power on, a change in
temperature, a change in decimation ratio, or a change in the
PGA. Calibration will remove the offset in the ODAC register.
Therefore, changes to the ODAC register must be done after
calibration.
At the completion of calibration, the DRDY signal will go
LOW to indicate that calibration is complete and valid data is
available.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc2, or sinc
filter, as shown in Figure 2. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the fast
settling filter for the next two conversions, the first of which
should be discarded. It will then use the sinc2 followed by the
sinc3 filter to improve noise performance. This combines the
low-noise advantage of the sinc3 filter with the quick response
of the fast settling time filter. The frequency response of each
filter is shown in Figure 3.
SINC3 FILTER RESPONSE
0
–20
–40
–60
Gain (dB)
–80
–100
–120
0 30 12060 90 150 180 210 240 270 300
0
3
–20
–40
–60
Gain (dB)
–80
(–3dB = 0.262 • f
Frequency (Hz)
SINC2 FILTER RESPONSE
(–3dB = 0.318 • f
= 15.76Hz)
DATA
= 19.11Hz)
DATA
Adjustable Digital Filter
3
Sinc
Modulator
Output
Sinc
2
Fast Settling
FILTER SETTLING TIME
FILTER (Conversion Cycles)
3
Sinc
2
Sinc
Fast 1
NOTE: (1) With Synchronized Channel Changes.
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
1234+
Discard Fast Sinc
FIGURE 2. Filter Step Responses.
SETTLING TIME
(1)
3
(1)
2
(1)
2
Data Out
3
Sinc
–100
–120
030 12060 90 150 180 210 240 270 300
Frequency (Hz)
FAST SETTLING FILTER RESPONSE
–20
–40
–60
Gain (dB)
–80
–100
–120
NOTE: f
0
DATA
0
= 60Hz.
(–3dB = 0.469 • f
30 12060 90 150 180 210 240 270 300
Frequency (Hz)
= 28.125Hz)
DATA
FIGURE 3. Filter Frequency Responses.
ADS1218
SBAS187
13
VOLTAGE REFERENCE
The voltage reference used for the ADS1218 can either be
internal or external. The power-up configuration for the
voltage reference is 2.5V internal. The selection for the
voltage reference is made through the status configuration
register.
The internal voltage reference is selectable as either 1.25V
or 2.5V (AVDD = 5V only). The V
pin should have a
REFOUT
0.1µF capacitor to AGND.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +V
and –V
–V
REF
. The absolute voltage on either pin (+V
REF
) can range from AGND to AVDD, however, the
REF
REF
and
differential voltage must not exceed 2.5V. The differential
voltage reference provides easy means of performing
ratiometric measurement.
V
PIN
RCAP
This pin provides a bypass cap for noise filtering on internal
V
circuitry only. The recommended capacitor is a 0.001µF
REF
ceramic cap. If an external V
is used, this pin can be left
REF
unconnected.
CLOCK GENERATOR
The clock source for the ADS1218 can be provided from a
crystal, ceramic resonator, oscillator, or external clock. When
the clock source is a crystal or ceramic resonator, external
capacitors must be provided to ensure start-up and a stable
clock frequency. This is shown in Figure 4 and Table I.
X
Crystal
or
Ceramic Resonator
C
C
IN
1
X
OUT
2
DIGITAL I/O INTERFACE
The ADS1218 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as
inputs. All of the digital I/O pins are individually configurable
as inputs or outputs. They are configured through the DIR
control register. The DIR register defines whether the pin is an
input or output, and the DIO register defines the state of the
digital output. When the digital I/O are configured as inputs,
DIO is used to read the state of the pin.
SERIAL INTERFACE
The serial interface is standard four-wire SPI compatible (DIN,
D
, SCLK, and CS). The ADS1218 also offers the flexibil-
OUT
ity to select the polarity of the serial clock through the POL
pin. The serial interface can be clocked up to f
OSC
/4. If CS
goes HIGH, the serial interface is reset. When CS goes LOW,
a new command is expected.
The serial interface operates independently of DRDY. DRDY
is used to indicate availability of data in the DOR. In order to
ensure the validity of the data being read, DOR timing
requirements must be met.
DSYNC OPERATION
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter
is reset on the falling edge of DSYNC. The modulator is held
in reset until DSYNC is taken HIGH. Synchronization
occurs on the next rising edge of the system clock after
DSYNC is taken HIGH.
When the DSYNC command is sent, the filter counter is
reset after the last SCLK on the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command.
FIGURE 4. Crystal or Ceramic Resonator Connection.
CLOCK PART
SOURCE FREQUENCY C
Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32
Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91
Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91
Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182
C
1
2
NUMBER
TABLE I. Typical Clock Sources.
14
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically. The POR issues the RESET command as described
below.
RESET
There are three methods of reset. The RESET pin, the
RESET command, and the SCLK Reset pattern. They all
perform the same function. After a reset, the FLASH data
values from Page 0 are loaded into RAM, subsequently data
values from Bank 0 of RAM are loaded into the configuration registers.
ADS1218
SBAS187
MEMORY
Three types of memory are used on the ADS1218: registers,
RAM, and FLASH. 16 registers directly control the various
functions (PGA, DAC value, Decimation Ratio, etc.) and can
be directly read or written to. Collectively, the registers contain
all the information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio, etc.
Additional registers, such as conversion data, are accessed
through dedicated instructions.
The on-chip FLASH can be used to store non-volatile data. The
FLASH data is separate from the configuration registers and
therefore can be used for any purpose, in addition to device
configuration. The FLASH page data is read and written in 128
byte blocks through the RAM banks, i.e. all RAM banks map
to a single page of FLASH, as shown in Figure 5.
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
Configuration
Register Bank
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 0
16 bytes
FLASH
4k Bytes
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
Bank 2
16 bytes
Page 0
128 bytes
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
RAM
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers,
Bank 7
16 bytes
i.e.: the RAM can be used as general-purpose RAM.
The ADS1218 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks are
available. Therefore, each configuration could be written once
and recalled as needed without having to serially retransmit all
Page 31
128 bytes
the configuration data. Checksum commands are also included, which can be used to verify the integrity of RAM.
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER
MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0
IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0
ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0
DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0
DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0
DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00
M/DEC1 DRDY U/B SMODE1 SMODE0 WREN DEC10 DEC09 DEC08
OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
0A
0B
0C
0D
0E
00
01
02
03
04
05
06
07
08
09
0F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
FIGURE 5. Memory Organization.
TABLE II. Registers.
ADS1218
SBAS187
15
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively without
having to address each bank individually. For example, if
you were currently accessing bank 0 at offset 0xF (the last
location of bank 0), the next access would be bank 1 and
offset 0x0. Any access after bank 7 and offset 0xF will wrap
around to bank 0 and Offset 0x0.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of bank
and offset addressing. Looking at linear and bank addressing
syntax, we have the following comparison: in the linear
memory map, the address 0x14 is equivalent to bank 1 and
offset 0x4. Simply stated, the most significant four bits
represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register
address for that bank of memory.
FLASH
Reads and Writes to FLASH occur on a Page basis.
Therefore, the entire contents of RAM is used for both
Read and Write operations. The FLASH is independent of
the Registers, i.e., the FLASH can be used as generalpurpose FLASH.
Upon power-up or reset, the contents of FLASH Page 0 are
loaded into RAM subsequently the contents of RAM Bank
0 are loaded into the configuration register. Therefore, the
user can customize the power-up configuration for the device. Care should be taken to ensure that data for FLASH
Page 0 is written correctly, in order to prevent unexpected
operation upon power-up.
The ADS1218 supports any combination of eight analog
inputs and the FLASH memory supports up to 32 unique Page
configurations. With this flexibility, the device could support
32 unique configurations for each of the eight analog input
channels. For instance, the on-chip temperature sensor could
be used to monitor temperature then different calibration
coefficients could be recalled for each of the eight analog
input channels based on the change in temperature. This
would enable the user to recall calibration coefficients for
every 4°C change in temperature over the industrial temperature range which could be used to correct for drift errors.
Checksum commands are also included, which can be used to
verify the integrity of FLASH.
The following two commands can be used to manipulate the
FLASH. First, the contents of FLASH can be written to with
the WR2F (write RAM to FLASH) command. This command first erases the designated FLASH page and then
writes the entire content of RAM (all banks) into the designated FLASH page. Second, the contents of FLASH can be
read with the RF2R (read FLASH to RAM) command. This
command reads the designated FLASH page into the entire
contents of RAM (all banks). In order to ensure maximum
endurance and data retention, the SPEED bit in the SETUP
register must be set for the appropriate f
frequency.
OSC
Writing to or erasing FLASH can be disabled either through
the WREN pin or the WREN register bit. If the WREN pin
is LOW OR the WREN bit is cleared, then the WR2F
command has no effect. This protects the integrity of the
FLASH data from being inadvertently corrupted.
Accessing the FLASH data either through read, write, or
erase may effect the accuracy of the conversion result.
Therefore, the conversion result should be discarded when
accesses to FLASH are done.
16
ADS1218
SBAS187
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iii01110
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ID ID ID SPEED REF EN REF HI BUF EN
BIT ORDER
bit 7-5 Factory Programmed Bits
bit 4 SPEED: FLASH Access Clock Speed
0 : 2.30MHz > f
1 : 3.12MHz > f
> 3.12MHz (default)
OSC
> 4.13MHz
OSC
bit 3 REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
bit 2 REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
bit 1 BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 0 BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only
controls the bit order within the byte of data that is
shifted out.
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
H
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 = Temperature Sensor Diode Anode
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Chan-
nel Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 =
Temperature Sensor Diode Cathode Analog GND
ACR (Address 02H) Analog Control Register
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0
H
bit 7 BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
IDAC Current =
8
•
V
REF
R
2
()
DAC
RANGE
1
−
DAC Code
()
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Ampli-
fier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
IDAC1 (Address 03H) Current DAC 1
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
H
The DAC code bits set the output of DAC1 from 0 to fullscale. The value of the full-scale current is set by this Byte,
V
, R
REF
, and the DAC1 range bits in the ACR register.
DAC
IDAC2 (Address 04H) Current DAC 2
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
H
The DAC code bits set the output of DAC2 from 0 to fullscale. The value of the full-scale current is set by this Byte,
V
, R
REF
, and the DAC2 range bits in the ACR register.
DAC
ADS1218
SBAS187
17
ODAC (Address 05H) Offset DAC Setting
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
H
bit 7 Offset Sign
0 = Positive
1 = Negative
V
bit 6-0 Offset =
NOTE: Calibration will cancel the value in the ODAC register. Therefore, writing
to the ODAC register should be done after calibration.
2 127•
REF
PGA
•
Code
bit 5-4 SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
10 = Sinc2 filter
11 = Sinc3 Flash filter
bit 3 WREN: Write Enable
0 = Flash Writing Disabled (default)
1 = Flash Writing Enabled
This bit is AND’d with the WREN pin to enable or
disable Flash Writing and Erasing
bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
DIO (Address 06H) Digital I/O Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
H
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
DIR (Address 07H) Direction control for digital I/O
Reset Value = FF
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
H
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
DEC0 (Address 08H) Decimation Register
(Least Significant 8 bits)
Reset Value = 80
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00
H
The decimation value is defined with 11 bits for a range of
20 to 2047. This register is the least significant 8 bits. The
3 most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
OCR0 (Address 0AH) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
H
OCR1 (Address 0BH) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
H
OCR2 (Address 0CH) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
H
FSR0 (Address 0DH) Full-Scale Register
(Least Significant Byte)
Reset Value = 24
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
H
M/DEC1 (Address 09H) Mode and Decimation Register
Reset Value = 07
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DRDY U/B SMODE1 SMODE0 WREN DEC10 DEC09 DEC08
H
bit 7 DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6 U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B ANALOG INPUT DIGITAL OUTPUT
0 Zero 0x000000
1 Zero 0x000000
+FSR 0x7FFFFF
–FSR 0x800000
+FSR 0xFFFFFF
–FSR 0x000000
18
FSR1 (Address 0EH) Full-Scale Register
(Middle Byte)
Reset Value = 90
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR15 FSR14 FSR13 FSR12 FSR011 FSR10 FSR09 FSR08
H
FSR2 (Address 0FH) Full-Scale Register
(Most Significant Byte)
Reset Value = 67
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR23 FSR22 FSR21 FSR20 FSR019 FSR18 FSR17 FSR16
H
ADS1218
SBAS187
COMMAND DEFINITIONS
D
IN
• • •
0000 0011 • • •
(1)
uuuu uuuu uuuu uuuu uuuu uuuu
D
OUT
xxxx xxxx • • •
(1)
MSB Mid-Byte LSB
D
IN
xxxx xxxx
D
OUT
MSB Mid-Byte
xxxx
LSB
DRDY
• • •
• • •
NOTE: (1) For wait time, refer to timing specification.
The commands listed below control the operation of the
ADS1218. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four f
cycles before the data is ready (e.g., RDATA).
COMMANDS DESCRIPTION COMMAND BYTE 2ND COMMAND BYTE
RDATA Read Data 0000 0001 (01
RDATAC Read Data Continuously 0000 0011 (03
STOPC Stop Read Data Continuously 0000 1111 (0F
RREG Read from REG Bank “rrrr” 0001 rrrr(1x
RRAM Read from RAM Bank “aaa” 0010 0aaa (2x
CREG Copy REGs to RAM Bank “aaa” 0100 0aaa(4x
CREGA Copy REGS to all RAM Banks 0100 1000 (48
WREG Write to REG “rrrr” 0101 rrrr (5x
WRAM Write to RAM Bank “aaa” 0110 0aaa (6x
RF2R Read FLASH page to RAM 100f ffff(8, 9x
WR2F Write RAM to FLASH page 101f ffff(A, Bx
CRAM Copy RAM Bank “aaa” to REG 1100 0aaa (Cx
CSRAMX Calc RAM Bank “aaa” Checksum 1101 0aaa (Dx
CSARAMX Calc all RAM Bank Checksum 1101 1000 (D8
CSREG Calc REG Checksum 1101 1111 (DF
CSRAM Calc RAM Bank “aaa” Checksum 1110 0aaa (Ex
CSARAM Calc all RAM Banks Checksum 1110 1000 (E8
CSFL Calc FLASH Checksum 1110 1100 (EC
SELFCAL Self Cal Offset and Gain 1111 0000 (F0
SELFOCAL Self Cal Offset 1111 0001 (F1
SELFGCAL Self Cal Gain 1111 0010 (F2
SYSOCAL Sys Cal Offset 1111 0011 (F3
SYSGCAL Sys Cal Gain 1111 0100 (F4
DSYNC Sync DRDY 1111 1100 (FC
SLEEP Put in SLEEP Mode 1111 1101 (FD
RESET Reset to Power-Up Values 1111 1110 (FE
NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
OSC
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
a = RAM bank address (0 to 7)
f = FLASH page address (0 to 31)
) —
H
) —
H
) —
H
) xxxx_nnnn (# of reg-1)
H
) xnnn_nnnn (# of bytes-1)
H
) —
H
) —
H
) xxxx_nnnn (# of reg-1)
H
) xnnn_nnnn (# of bytes-1)
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
) —
H
TABLE III. Command Summary.
RDATA Read Data
Description: Read a single data value from the Data Output
Register (DOR) which is the most recent conversion result.
This is a 24-bit value.
Operands: None
Bytes: 1
Encoding: 0000 0001
Data Transfer Sequence:
0000 0001 • • •
D
IN
xxxx xxxx • • •
D
OUT
NOTE: (1) For wait time, refer to timing specification.
(1)
xxxx xxxx xxxx xxxx xxxx xxxx
(1)
MSB Mid-Byte LSB
RDATAC Read Data Continuous
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands: None
Bytes: 1
Encoding: 0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC
or RESET.
ADS1218
SBAS187
19
STOPC Stop Continuous
CREG Copy Registers to RAM Bank
Description: Ends the continuous data output mode.
Operands: None
Bytes: 1
Encoding: 0000 1111
Data Transfer Sequence:
0000 1111
D
IN
xxxx xxxx
D
OUT
RREG Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
If the count exceeds the remaining registers, the addresses will
wrap back to the beginning.
Operands: r, n
Bytes: 2
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Operands: a
Bytes: 1
Encoding: 0100 0aaa
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
0100 0011
D
IN
xxxx xxxx
D
OUT
CREGA Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the
RAM banks. Refer to timing specifications for command
execution time.
Operands: None
Bytes: 1
Encoding: 0100 1000
Data Transfer Sequence:
0001 0001 0000 0001 xxxx xxxx xxxx xxxx
D
IN
D
NOTE: (1) For wait time, refer to timing specification.
xxxx xxxx xxxx xxxx MUX ACR
OUT
• • •
• • •
(1)
(1)
RRAM Read from RAM
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
Operands: a, n
Bytes: 2
Encoding: 0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20
0010 0010 x000 0001 xxxx xxxx xxxx xxxx
D
IN
D
xxxx xxxx xxxx xxxx
OUT
• • •
• • •
(1)
(1)
RAM Data
20
H
H
RAM Data
21
H
0100 1000
D
IN
xxxx xxxx
D
OUT
WREG Write to Register
Description: Write to the registers starting with the register
specified as part of the instruction. The number of registers
that will be written is one plus the value of the second byte.
Operands: r, n
Bytes: 2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 06H (DIO)
0101 0110 xxxx 0001
D
IN
D
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUT
Data for DIO Data for DIR
NOTE: (1) For wait time, refer to timing specification.
20
ADS1218
SBAS187
WRAM Write to RAM
CRAM Copy RAM Bank to Registers
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value
of the second byte.
Operands: a, n
Bytes: 2
Encoding: 0110 0aaa xnnn nnnn
Data Transfer Sequence:
Write to Two RAM Locations starting from 10
0110 0001 x000 0001
D
IN
D
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUT
Data for
10
H
H
Data for
11
H
RF2R Read FLASH Page to RAM
Description: Read the selected FLASH page to the RAM.
Operands: f
Bytes: 1
Encoding: 100f ffff
Data Transfer Sequence:
Read FLASH Page 2 to RAM
1000 0010
D
IN
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the
data from the RAM bank.
Operands: a
Bytes: 1
Encoding: 1100 0aaa
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
1100 0000
D
IN
xxxx xxxx
D
OUT
CSRAMX Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. The ID, DRDY and DIO bits are
masked so they are not included in the checksum.
Operands: a
Bytes: 1
Encoding: 1101 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
xxxx xxxx
D
OUT
WR2FWrite RAM to FLASH
Description: Write the contents of RAM to the selected
FLASH page.
Operands: f
Bytes: 1
Encoding: 101f ffff
Data Transfer Sequence:
Write RAM to FLASH page 31
1011 1111
D
IN
xxxx xxxx
D
OUT
1101 0011
D
IN
xxxx xxxx
D
OUT
CSARAMX Calculate the Checksum
for all RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands: None
Bytes: 1
Encoding: 1101 1000
Data Transfer Sequence:
1101 1000
D
IN
xxxx xxxx
D
OUT
ADS1218
SBAS187
21
CSREG Calculate the Checksum of
Registers
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands: None
Bytes: 1
Encoding: 1101 1111
Data Transfer Sequence:
1101 1111
D
IN
xxxx xxxx
D
OUT
CSRAM Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Operands: a
Bytes: 1
Encoding: 1110 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
CSFL
Calculate Checksum for all FLASH Pages
Description: Calculate the checksum for all FLASH pages.
The checksum is calculated as a sum of all the bytes with the
carry ignored. All bits are included in the checksum calculation, there is no masking of bits.
Operands: None
Bytes: 1
Encoding: 1110 1100
Data Transfer Sequence:
1110 1100
D
IN
xxxx xxxx
D
OUT
SELFCAL Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Control Register (OCR) and the Full-Scale Register (FSR) are
updated with new values after this operation.
Operands: None
Bytes: 1
Encoding: 1111 0000
Data Transfer Sequence:
1111 0000
D
IN
1110 0010
D
IN
xxxx xxxx
D
OUT
CSARAM Calculate Checksum for all
RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. All bits are included in the checksum calculation,
there is no masking of bits.
Operands: None
Bytes: 1
Encoding: 1110 1000
Data Transfer Sequence:
1110 1000
D
IN
xxxx xxxx
D
OUT
xxxx xxxx
D
OUT
SELFOCAL Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this
operation.
Operands: None
Bytes: 1
Encoding: 1111 0001
Data Transfer Sequence:
1111 0001
D
IN
xxxx xxxx
D
OUT
22
ADS1218
SBAS187
SELFGCAL Gain Self Calibration
DSYNC Sync DRDY
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values
after this operation.
Operands: None
Bytes: 1
Encoding: 1111 0010
Data Transfer Sequence:
1111 0010
D
IN
xxxx xxxx
D
OUT
SYSOCAL System Offset Calibration
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1218 computes the OCR register
value that will compensate for offset errors. The Offset
Control Register (OCR) is updated after this operation.
Operands: None
Bytes: 1
Encoding: 1111 0011
Data Transfer Sequence:
Description: Synchronizes the ADS1218 to the serial clock
edge.
Operands: None
Bytes: 1
Encoding: 1111 1100
Data Transfer Sequence:
1111 1100
D
IN
xxxx xxxx
D
OUT
SLEEP Sleep Mode
Description: Puts the ADS1218 into a low power sleep mode.
To exit sleep mode strobe SCLK.
Operands: None
Bytes: 1
Encoding: 1111 1101
Data Transfer Sequence:
1111 1101
D
IN
xxxx xxxx
D
OUT
1111 0011
D
IN
xxxx xxxx
D
OUT
SYSGCAL System Gain Calibration
Description: Starts the system gain calibration process. For a
system gain calibration, the differential input should be set to
the reference voltage and the ADS1218 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
Operands: None
Bytes: 1
Encoding: 1111 0100
Data Transfer Sequence:
1111 0100
D
IN
xxxx xxxx
D
OUT
RESET Reset to Powerup Values
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
Operands: None
Bytes: 1
Encoding: 1111 1110
Data Transfer Sequence:
1111 1110
D
IN
xxxx xxxx
D
OUT
ADS1218
SBAS187
23
LSB
MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 x rdata x rdatac x x x x x x x x x x x stopc
0001 rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg
0010 rram rram rram rram rram rram rram rram x x x x x x x x
0011 x x x x x x x x x x x x x x x x
0100 creg creg creg creg creg creg creg creg crega x x x x x x x
0101 wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg wreg
0110 wram wram wram wram wram wram wram wram x x x x x x x x
0111 x x x x x x x x x x x x x x x x
1000 rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r
1001 r f2r rf2r rf2r rf2r r f2r rf2r rf2r rf2r rf2r r f2r rf2r rf 2r rf2r r f2r rf2r r f2r
1010 wr2f wr2f wr2f wr2f wr2f wr2f w r2f wr2f wr 2f w r2f wr2f wr 2f wr2f wr2f wr2f wr2f
1011 wr2f wr2f wr2f wr2f wr2f wr2f w r2f wr2f wr 2f w r2f wr2f wr 2f wr2f wr2f wr2f wr2f
1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7 x x x x x x x x
1101 x x x x x x csreg
1110 x x x csfl x x x
1111 self self self sys sys x x x x x x x dsync sleep reset x
x = Reserved
0123456789ABCDEF
01234567
01234567
0123456789ABCDEF
01234567
0123456789ABCDEF
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0123456789ABCDEF
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
csramx csramx csramx csramx csramx csramx csramx csramx csramx
01234567
csram 0 csram 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7 csram
cal ocal gcal ocal gcal
TABLE IV. ADS1218 Command Map.
24
ADS1218
SBAS187
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI), allows a controller to
communicate synchronously with the ADS1218. The
ADS1218 operates in slave only mode.
SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted
and received. The SCLK signal synchronizes shifting and
sampling of the information on the two serial data lines: D
and D
. The CS signal allows individual selection of an
OUT
ADS1218 device; an ADS1218 with CS HIGH is not active
on the bus.
Clock Phase and Polarity Controls (POL)
The clock polarity is specified by the POL pin, which selects
an active HIGH or active LOW clock, and has no effect on
the transfer format.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input to the ADS1218, is generated by the master device and synchronizes data transfer on
the DIN and D
lines. When transferring data to or from
OUT
the ADS1218, burst mode may be used i.e., multiple bits of
data may be transferred back-to-back with no delay in
SCLKs or toggling of CS.
Chip Select (CS)
The chip select (CS) input of the ADS1218 must be externally asserted before a master device can exchange data with
the ADS1218. CS must be LOW before data transactions
and must stay LOW for the duration of the transaction.
DIGITAL INTERFACE
The ADS1218’s programmable functions are controlled
using a set of on-chip registers, as outlined previously. Data
is written to these registers via the part’s serial interface and
read access to the on-chip registers is also provided by this
interface.
The ADS1218’s serial interface consists of four signals: CS,
SCLK, DIN, and D
data into the on-chip registers while the D
. The DIN line is used for transferring
OUT
line is used for
OUT
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on
DIN or D
) take place with respect to this SCLK signal.
OUT
The DRDY line is used as a status signal to indicate when
data is ready to be read from the ADS1218’s data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
CS is used to select the device. It can be used to decode the
ADS1218 in systems where a number of parts are connected
to the serial bus.
The timing specification shows the timing diagram for
interfacing to the ADS1218 with CS used to decode the part.
The ADS1218 serial interface can operate in three-wire
mode by tying the CS input LOW. In this case, the SCLK,
IN
DIN, and D
ADS1218 and the status of DRDY can be obtained by
lines are used to communicate with the
OUT
interrogating bit 7 of the M/DEC1 register. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port pin.
DEFINITION OF TERMS
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
Analog Input Differential Voltage—g
equation: (IN+ – IN–).
Thus, a positive digital output is pro-
iven by the following
duced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the
differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
Conversion Cycle—the term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the t
time period.
DATA
However, each digital output is actually based on the modulator results from several t
FILTER SETTING MODULATOR RESULTS
fast settling 1 t
2
sinc
3
sinc
time periods.
DATA
2 t
3 t
time period
DATA
time period
DATA
time period
DATA
Data Rate—The rate at which conversions are completed.
See definition for f
DATA
.
Decimation Ratio—defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise and vice-versa.
ADS1218
SBAS187
25
Effective Resolution—the effective resolution of the
ADS1218 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter’s
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
BITS rms BIPOLAR Vrms UNIPOLAR Vrms
2
•.•V
10
24 298nV 149nV
22 1.19µV 597nV
20 4.77µV 2.39µV
18 19.1µV 9.55µV
16 76.4µV 38.2µV
14 505µV 152.7µV
12 1.22mV 610µV
PGA
602
20
REF
ER
V
PGA
10
REF
60220.•
ER
f
—the frequency, or switching speed, of the input
SAMP
sampling capacitor. The value is given by one of the following equations:
PGA SETTING SAMPLING FREQUENCY
f
1, 2, 4, 8
16
32
64, 128
f
—the frequency of the digital output data produced by
DATA
the ADS1218, f
f
DATA
=
Decimation Ratio
is also referred to as the Data Rate.
DATA
f
MOD OSC
f
f
f
f
=
mfactor Decimation Ratio
SAMP
SAMP
SAMP
SAMP
=
mfactor
f
OSC
=
mfactor
f
OSC
=
mfactor
f
OSC
=
mfactor
•
OSC
•2
•4
•8
f
Filter Selection—the ADS1218 uses a (sinx/x) filter or sinc
filter. Actually there are three different sinc filters that can
be selected. A fast settling filter will settle in one t
DATA
cycle. The sinc2 filter will settle in two cycles and have
lower noise. The sinc3 will achieve the lowest noise and
highest number of effective bits, but requires three cycles to
settle. The ADS1218 will operate with any one of these
filters, or it can operate in an auto mode, where it will select
the fast settling filter after a new channel is selected and will
then switch to sinc2 followed by sinc3. This allows fast
settling response and still achieves low noise after the
necessary number of t
f
—the frequency of the crystal oscillator or CMOS
OSC
DATA
cycles.
compatible input signal at the XIN input of the ADS1218.
f
—the frequency or speed at which the modulator of the
MOD
ADS1218 is running. This depends on the SPEED bit as
given by the following equation:
SPEED = 0 SPEED = 1
mfactor 128 256
f
=
mfactor
OSC
f
MOD
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1218 is defined as the “input”,
which produces the positive full-scale digital output minus
the “input”, which produces the negative full-scale digital
output. The full-scale range changes with gain setting as
shown in Table V.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
LSB Weight
Full Scale Range
−
=
N
2
where N is the number of bits in the digital output.
t
—the inverse of f
DATA
, or the period between each
DATA
data output.
5V SUPPLY ANALOG INPUT
GAIN SETTING FULL-SCALE RANGE INPUT VOLTAGES
15V±2.5V ±1.25V
22.5V±1.25V ±0.625V
4 1.25V ±0.625V ±312.5mV
8 0.625V ±312.5mV ±156.25mV
16 312.5mV ±156.25mV ±78.125mV
32 156.25mV ±78.125mV ±39.0625mV
64 78.125mV ±39.0625mV ±19.531mV
128 39.0625mV ±19.531mV ±9.766mV
NOTES: (1) With a 2.5V reference. (2) The ADS1218 allows common-mode voltage as long as the absolute input voltage on A
AGND or above AV
.
DD
DIFFERENTIAL PGA OFFSET FULL-SCALE DIFFERENTIAL PGA SHIFT
(1)
(2)
RANGE RANGE INPUT VOLTAGES
2• V
PGA
GENERAL EQUATIONS
REF
TABLE V. Full-Scale Range versus PGA Setting.
26
(2)
RANGE
±V
REF
PGA
P or AINN does not go below
IN
±•V
2
ADS1218
SBAS187
REF
PGA
TOPIC INDEX
TOPIC PAGE
ABSOLUTE MAXIMUM RATINGS ..........................................................................................................................2
PACKAGE AND ORDERING INFORMATION ........................................................................................................2
ELECTRICAL CHARACTERISTICS (AVDD = 5V) .................................................................................................. 2
ELECTRICAL CHARACTERISTICS (AVDD = 3V) .................................................................................................. 4
PIN CONFIGURATION ............................................................................................................................................6
TIMING SPECIFICATIONS ......................................................................................................................................7
TYPICAL CHARACTERISTICS ...............................................................................................................................8
OVERVIEW.............................................................................................................................................................12
MEMORY ................................................................................................................................................................15
REGISTER BANK TOPOLOGY ............................................................................................................................15
DETAILED REGISTER DEFINITIONS ..................................................................................................................17
COMMAND DEFINITIONS .....................................................................................................................................19
ADS1218 COMMAND MAP...................................................................................................................................24
SERIAL PERIPHERAL INTERFACE .....................................................................................................................25
DIGITAL INTERFACE ............................................................................................................................................25
DEFINITION OF TERMS ........................................................................................................................................25
ADS1218
SBAS187
27
PACKAGE DRAWING
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
37
48
1,05
0,95
0,50
36
0,27
0,17
25
24
13
1
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
12
M
0,08
0,05 MIN
Seating Plane
0,13 NOM
Gage Plane
0,25
0°–7°
0,75
0,45
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
0,08
4073176/B 10/96
28
ADS1218
SBAS187
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
ADS1218Y/250 ACTIVE TQFP PFB 48 250
ADS1218Y/2K ACTIVE TQFP PFB 48 2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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