TEXAS INSTRUMENTS ADS1217 Technical data
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A
D
S
1
2
1
7
SBAS260B – MAY 2002 – REVISED OCTOBER 2004
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
ADS1217
FEATURES
● 24 BITS NO MISSING CODES
● INL: 0.0012% of FSR (max)
● FULL-SCALE INPUT: ±2V
REF
● PGA FROM 1 TO 128
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
● ON-CHIP 1.25V/2.5V REFERENCE
● ON-CHIP CALIBRATION
● SPI COMPATIBLE
● POWER SUPPLY: 2.7V to 5.25V
● < 1mW POWER CONSUMPTION, VDD = 3V
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGH SCALES
● PRESSURE TRANSDUCERS
IDAC2
IDAC1
DESCRIPTION
The ADS1217 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from 2.7V to 5.25V supplies. The delta-sigma,
A/D converter provides up to 24 bits of no missing code
performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering
can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals.
Burnout current sources are provided that allow for the
detection of an open or shorted sensor. An 8-bit Digital-toAnalog Converter (DAC) provides an offset correction with a
range of 50% of the FSR (Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a 2nd-order,
delta-sigma modulator and programmable sinc filter. The
reference input is differential and can be used for ratiometric
measurements. The onboard current DACs operate independently with the maximum current set by an external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O
are also provided that can be used for input or output. The
ADS1217 is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh
scales, chromatography, and portable instrumentation.
V
AGND AV
R
REFOUTVRCAPVREF+VREF–
8-Bit
IDAC
8-Bit
IDAC
DAC
Voltage
Reference
DD
X
X
IN
Clock Generator
OUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
A
IN
A
IN
A
IN
A
IN
A
IN
A
IN
A
IN
A
IN
A
INCOM
0
1
2
3
4
5
6
7
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MUX
Offset
DAC
+
BUF PGA
PDWN
DYSNC
2nd-Order
Modulator
DD
Program-
mable
Digital
Filter
Digital I/O
Interface
Controller
D7BUFEN ...D0DGNDDV
Registers
Serial Interface
RAM
RESET
POL
SCLK
D
IN
D
OUT
CS
DRDY
Copyright © 2002-2004, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
(1)
AVDD to AGND ...................................................................... –0.3V to +6V
DV
to DGND...................................................................... –0.3V to +6V
DD
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
................................................................... GND –0.5V to AVDD + 0.5V
IN
AV
to DVDD........................................................................... –6V to +6V
DD
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND.................................... –0.3V to DV
Digital Output Voltage to GND ................................. –0.3V to DV
Maximum Junction Temperature ................................................... +150°C
+ 0.3V
DD
+ 0.3V
DD
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS1217 TQFP-48 PFB –40°C to +85°C ADS1217 ADS1217IPFBT Tape and Reel, 250
" """"ADS1217IPFBR Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, f
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
(AIN0 – AIN7, A
Full-Scale Input Voltage (A
Analog Input Voltage Buffer OFF AGND – 0.1 AV
INCOM
)
) – (A
IN+
IN–
Buffer ON AGND + 0.05 AV
Differential Input Impedance Buffer OFF 10/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469f
2
Sinc
Filter –3dB 0.318f
3
Sinc
Filter –3dB 0.262f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1%
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes Sinc
3
Filter 24 Bits
Integral Nonlinearity End Point Fit, Differential Input, 0.0003 0.0012 % of FSR
Buffer Off
Offset Error Before Calibration 7.5 ppm of FSR
Offset Drift 0.02 ppm of FSR/°C
Gain Error Before Calibration 0.005 %
Gain Error Drift 0.5 ppm/°C
Common-Mode Rejection at DC 100 dB
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
Normal-Mode Rejection f
Output Noise See Typical Characteristics
CM
SIG
f
SIG
= 50Hz, f
= 60Hz, f
DATA
DATA
DATA
DATA
DATA
Power-Supply Rejection at DC, dB = –20log(∆V
NOTES: (1) FSR is Full-Scale Range. (2) ∆V
is change in digital result. (3) 12pF switched capacitor at f
OUT
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 150kΩ, f
DAC
= 10Hz, and V
DATA
REF
ADS1217
) ±2V
/PGA V
REF
DATA
DATA
DATA
/(PGA) V
REF
+ 0.1 V
DD
– 1.5 V
DD
Hz
Hz
Hz
= 10Hz 130 dB
= 50Hz 120 dB
= 60Hz 120 dB
= 50Hz 100 dB
= 60Hz 100 dB
(2)
OUT
/∆VDD)
80 95 dB
clock frequency.
SAMP
= +2.5V,
(1)
2
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ADS1217
SBAS260B
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, f
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE INPUT
Reference Input (V
Negative Reference Input (V
Positive Reference Input (V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
(3)
)V
REF
) AGND – 0.1 (V
REF–
)(V
REF+
≡ (V
REF
VREFCM
V
REF
) – (V
REF+
= 60Hz, f
DATA
= 2.5V, PGA = 1 1.3 µA
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 1 2.4 2.5 2.6 V
REF HI = 0 1.25 V
Short-Circuit Current Source 8mA
Short-Circuit Current Sink 50 µA
Drift 15 ppm/°C
Noise V
Output Impedance Sourcing 100µA3Ω
= 0.1µF, BW = 0.1Hz to 100Hz 10 µVrms
RCAP
Startup Time 5ms
IDAC
Full-Scale Output Current R
Current Setting Resistance (R
Monotonicity R
)10kΩ
DAC
Compliance Voltage 0AV
= 150kΩ, Range = 1 0.5 mA
DAC
R
= 150kΩ, Range = 2 1 mA
DAC
R
= 150kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
= 150kΩ 8 Bits
DAC
Output Impedance See Typical Characteristics
PSRR V
Gain Error Individual IDAC 5 %
= AVDD/2, Code > 16 400 ppm/V
OUT
Gain Error Drift Individual IDAC 75 ppm/°C
Gain Error Mismatch
Gain Error Mismatch Drift
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
A/D Converter Current (I
ADC
+ I
+ I
VREF
IDAC)
) PGA = 1, Buffer OFF 175 275 µA
ADC
PDWN = 0, or SLEEP 1 nA
PGA = 128, Buffer OFF 500 750 µA
DD
PGA = 1, Buffer ON 250 350 µA
PGA = 128, Buffer ON 900 1375 µA
V
I
REF
IDAC
Current (I
Current (I
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
IDAC
Digital Current Normal Mode, DV
SLEEP Mode, DV
Read Data Continuous Mode, DV
PDWN = 0 1 nA
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 1.8 2.8 mW
IDACs OFF, DV
NOTES: (1) FSR is Full-Scale Range. (2) ∆V
is change in digital result. (3) 12pF switched capacitor at f
OUT
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 150kΩ, f
DAC
= 10Hz, and V
DATA
ADS1217
) 0.1 2.5 2.6 V
REF–
) + 0.1 AVDD + 0.1 V
REF–
) – 0.1 V
REF+
= 60Hz 120 dB
– 1 V
DD
0.25 %
15 ppm/°C
4.75 5.25 V
= 5V 180 275 µA
DD
= 5V 150 µA
DD
DD
= 5V 230 µA
DD
= 5V
clock frequency.
SAMP
= +2.5V,
REF
ADS1217
SBAS260B
www.ti.com
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, f
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
(AIN0 – AIN7, A
Full-Scale Input Voltage
Analog Input Range Buffer OFF AGND – 0.1 AV
INCOM
)
(A
) – (A
IN+
IN–
Buffer ON AGND + 0.05 AV
Input Impedance Buffer OFF 10/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469f
2
Sinc
Filter –3dB 0.318f
3
Sinc
Filter –3dB 0.262f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1%
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes Sinc
3
Filter 24 Bits
Integral Nonlinearity End Point Fit, Differential Input, 0.0003 0.0012 % of FSR
Buffer Off, T = 25°C
Offset Error Before Calibration 15 ppm of FSR
Offset Drift 0.04 ppm of FSR/°C
Gain Error Before Calibration 0.010 %
Gain Error Drift 1.0 ppm/°C
Common-Mode Rejection at DC 100 dB
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
Normal-Mode Rejection f
Output Noise See Typical Characteristics
CM
SIG
f
SIG
= 50Hz, f
= 60Hz, f
DATA
DATA
DATA
DATA
DATA
Power-Supply Rejection at DC, dB = –20 log(∆V
VOLTAGE REFERENCE INPUT
Reference Input (V
Negative Reference Input (V
Positive Reference Input (V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
(3)
)V
REF
) AGND – 0.1 (V
REF–
)(V
REF+
REF
VREFCM
≡ (V
) – (V
REF+
= 60Hz, f
DATA
V
= 1.25V 0.65 µA
REF
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 0 1.2 1.25 1.3 V
Short-Circuit Current Source 3mA
Short-Circuit Current Sink 50 µA
Drift 15 ppm/°C
Noise V
Output Impedance Sourcing 100µA3Ω
= 0.1µF, BW = 0.1Hz to 100Hz 10 µVrms
RCAP
Startup Time 5ms
IDAC
Full-Scale Output Current R
Current Setting Resistance (R
Monotonicity R
)10kΩ
DAC
Compliance Voltage 0AV
= 75kΩ, Range = 1 0.5 mA
DAC
R
= 75kΩ, Range = 2 1 mA
DAC
R
= 75kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
= 75kΩ 8 Bits
DAC
Output Impedance See Typical Characteristics
PSRR V
Gain Error Individual IDAC 5 %
= AVDD/ 2, Code > 16 600 ppm/V
OUT
Gain Error Drift Individual IDAC 75 ppm/°C
Gain Error Mismatch
Gain Error Mismatch Drift
NOTES: (1) FSR is Full-Scale Range. (2) ∆V
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
is change in digital result. (3) 12pF switched capacitor at f
OUT
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 75kΩ, f
DAC
= 10Hz, and V
DATA
= +1.25V,
REF
ADS1217
)
±2V
/PGA V
REF
DATA
DATA
DATA
/(PGA) V
REF
+ 0.1 V
DD
– 1.5 V
DD
= 10Hz 130 dB
= 50Hz 120 dB
= 60Hz 120 dB
= 50Hz 100 dB
= 60Hz 100 dB
(2)
/∆VDD)
OUT
) 0.1 1.25 1.3 V
REF–
75 90 dB
) – 0.1 V
) + 0.1 AVDD + 0.1 V
REF–
REF+
= 60Hz 120 dB
– 1 V
DD
0.25 %
15 ppm/°C
clock frequency.
SAMP
Hz
Hz
Hz
(1)
4
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ADS1217
SBAS260B
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, f
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
A/D Converter Current (I
ADC
+ I
+ I
VREF
ADC
) PDWN = 0, or SLEEP 1 nA
IDAC
) PGA = 1, Buffer OFF 160 250 µA
PGA = 128, Buffer OFF 450 700 µA
DD
PGA = 1, Buffer ON 230 325 µA
PGA = 128, Buffer ON 850 1325 µA
V
I
REF
IDAC
Current (I
Current (I
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
IDAC
Digital Current Normal Mode, DV
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 3V
PDWN = 0 1 nA
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 0.8 1.4 mW
IDACs OFF, DV
NOTES: (1) FSR is Full-Scale Range. (2) ∆V
is change in digital result. (3) 12pF switched capacitor at f
OUT
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 75kΩ, f
DAC
= 10Hz, and V
DATA
ADS1217
2.7 3.3 V
= 3V 90 200 µA
DD
= 3V 75 µA
DD
DD
= 3V
113 µA
clock frequency.
SAMP
REF
ELECTRICAL CHARACTERISTICS: Digital
All specifications at –40°C to +85°C, and DVDD = +2.7V to 5.25V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT/OUTPUT
Logic Level
V
IH
(1)
V
IL
V
OH
V
OL
Input Leakage: I
IN
CLOCK RATES
Master Clock Rate: f
Master Clock Period: t
NOTE: (1) Maximum V
OSC
OSC
for XIN is DGND + 0.05V.
IL
IOH = 1mA DVDD – 0.4 V
IOL = 1mA DGND DGND + 0.4 V
0 < VI < DV
DD
1/f
OSC
0.8 × DV
DD
DGND 0.2 × DV
DV
DD
DD
–10 10 µA
1 8 MHz
125 1000 ns
= +1.25V,
V
V
ADS1217
SBAS260B
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5
PIN CONFIGURATION
Top View TQFP
AGND
V
REFOUT
V
V
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF–
OUTDIN
D
SCLKCSDRDY
DVDDDGND
DSYNC
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
ADS1217
43
44
45
46
47
48
12345678910112512
0
1
2
3
4
5
IN
IN
IN
A
A
AV
DD
AGND
IN
IN
A
IN
A
A
A
POL
6
IN
A
PDWN
7
IN
A
OUTXIN
X
INCOM
A
AGND
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
DGND
R
DAC
IDAC2
IDAC1
V
RCAP
AV
DD
PIN DESCRIPTIONS
PIN
NUMBER NAME DESCRIPTION
1AV
DD
2 AGND Analog Ground
3A
4A
5A
6A
7A
8A
9A
10 A
11 A
IN
IN
IN
IN
IN
IN
IN
IN
INCOM
12 AGND Analog Ground
13 AV
14 V
DD
RCAP
15 IDAC1 Current DAC1 Output
16 IDAC2 Current DAC2 Output
17 R
DAC
18-22 DGND Digital Ground
23 BUFEN Buffer Enable Input
24 RESET Active LOW, resets the entire chip.
Analog Power Supply
0 Analog Input 0
1 Analog Input 1
2 Analog Input 2
3 Analog Input 3
4 Analog Input 4
5 Analog Input 5
6 Analog Input 6
7 Analog Input 7
Analog Input Common
Analog Power Supply
V
Bypass Capacitor
REFOUT
Current DAC Resistor
PIN
NUMBER NAME DESCRIPTION
25 X
26 X
IN
OUT
Clock Input
Clock Output, used with crystal or resonator.
27 PDWN Active LOW. Power Down. The power-down
function shuts down the analog and digital
circuits.
28 POL Serial Clock Polarity Input
29 DSYNC Active LOW, Synchronization Control Input
30 DGND Digital Ground
31 DV
DD
Digital Power Supply
32 DRDY Active LOW, Data Ready Output
33 CS Active LOW, Chip Select Input
34 SCLK Serial Clock, Schmitt Trigger
35 D
36 D
IN
OUT
Serial Data Input, Schmitt Trigger
Serial Data Output
37-44 D0-D7 Digital I/O 0-7
45 AGND Analog Ground
46 V
47 V
48 V
REFOUT
REF+
REF–
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
6
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ADS1217
SBAS260B
TIMING DIAGRAMS
CS
SCLK
(POL = 0)
SCLK
(POL = 1)
D
IN
t
3
t
4
MSB
t
1
t
5
t
2
t
6
t
2
t
10
t
11
LSB
t
D
OUT
(Command or Command and Data)
7
MSB
t
8
(1)
LSB
t
9
(1)
NOTE: (1) Bit Order = 0.
SCLK Reset Waveform
ADS1217
Resets On
Falling Edge
t
13
t
13
SCLK
t
12
t
14
t
15
t
t
17
RESET, DSYNC, PDWN
16
DRDY
TIMING CHARACTERISTICS
SPEC DESCRIPTION MIN MAX UNITS
t
1
t
2
t
3
t
4
t
5
t
6
(2)
t
7
(2)
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
NOTES: (1) CS may be tied LOW. (2) Load = 20pF.
SCLK Period 4t
3 DRDY Periods
SCLK Pulse Width, HIGH and LOW 200 ns
CS LOW to First SCLK Edge; Setup Time
(1)
0ns
DIN Valid to SCLK Edge; Setup Time 50 ns
Valid DIN to SCLK Edge; Hold Time 50 ns
Delay Between Last SCLK Edge for DIN and First SCLK
Edge for D
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OUT
:
CSREG, CSRAMX, CSRAM 200 t
CSARAM, CSARAMX 1100 t
SCLK Edge to Valid New D
SCLK Edge to D
Last SCLK Edge to D
NOTE: D
OUT
, Hold Time 0 ns
OUT
Tri-State 6 10 t
OUT
goes tri-state immediately when CS goes HIGH.
OUT
50 ns
CS LOW Time After Final SCLK Edge 0 ns
Final SCLK Edge of One Op Code Until First Edge SCLK
of Next Command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, t
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC 4 t
CREG, CRAM 220 t
CREGA 1600 t
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Input pin, command, or SCLK pattern) 16 t
300 500 t
5t
550 750 t
1050 1250 t
Pulse Width 4t
Data Not Valid 4 t
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
ADS1217
SBAS260B
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7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, and V
DATA
= +2.5V, unless otherwise specified.
REF
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
PGA1
PGA8
PGA4
PGA2
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter, BUFFER OFF
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter, V
= 1.25V, BUFFER OFF
REF
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA2
PGA1
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
PGA16
PGA32
PGA64
Sinc3 Filter, BUFFER ON
PGA128
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
12
PGA32
PGA16
Sinc3 Filter, V
PGA64
REF
PGA128
= 1.25V, BUFFER ON
0 500 1000 1500 2000
Decimation Ratio
8
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
20
19
18
17
16
ENOB (rms)
PGA32
PGA16 PGA64
15
14
13
Sinc2 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
MOD
DATA
PGA8
PGA128
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EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
FAST SETTLING FILTER
22
21
20
19
18
17
16
ENOB (rms)
15
14
13
Fast Settling Filter
12
f
f
DATA
1500
MOD
0 500 1000 1500 2000
Decimation Ratio =
ADS1217
SBAS260B
TYPICAL CHARACTERISTICS (Cont.)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
COMMON-MODE REJECTION RATIO vs FREQUENCY
Frequency of CM Signal (Hz)
1 10 100 1k 10k 100k
CMRR (dB)
140
120
100
80
60
40
20
0
–20
–40
OFFSET vs TEMPERATURE
Offset (ppm of FS)
Temperature (°C)
–50 0 50 100
PGA128
PGA16
PGA64
PGA1
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, and V
DATA
= +2.5V, unless otherwise specified.
REF
0.7
0.6
0.5
0.4
0.3
0.2
Noise (rms, ppm of FS)
0.1
0
–5 –3–4102–1–2345
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
120
110
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
110 1k100 10k 100k
NOISE vs INPUT SIGNAL
V
(V)
IN
Frequency of Power Supply (Hz)
1.00010
1.00006
1.00002
0.99998
0.99994
Gain (Normalized)
0.99990
0.99986
ADS1217
–50 –30 10–10 30 50 70 90
SBAS260B
GAIN vs TEMPERATURE
Temperature (°C)
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INTEGRAL NONLINEARITY vs INPUT SIGNAL
6
–40°C
4
2
0
–2
INL (ppm of FS)
–4
–6
–5 –4 –2 –1–3 012345
+25°C
+85°C
(V)
V
IN
9
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