TEXAS INSTRUMENTS ADS1216 Technical data
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A
D
S
1
2
1
6
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
ADS1216
SBAS171B – JUNE 2001
FEATURES
● 24 BITS NO MISSING CODES
● 0.0015% INL
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● PGA FROM 1 TO 128
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
● ON-CHIP 1.25V/2.5V REFERENCE
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
● ON-CHIP CALIBRATION
● SPI™ COMPATIBLE
● 2.7V TO 5.25V
● < 1mW POWER CONSUMPTION
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES
● PRESSURE TRANSDUCERS
SPI is a registered trademark of Motorola.
IDAC2
IDAC1
DESCRIPTION
The ADS1216 is a precision, wide dynamic range, delta-sigma, Analogto-Digital (A/D) converter with 24-bit resolution operating from 2.7V to
5.25V supplies. The delta-sigma, A/D converter provides up to 24 bits of
no missing code performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering can be
selected to provide a very high input impedance for direct connection to
transducers or low-level voltage signals. Burn out current sources are
provided that allow for the detection of an open or shorted sensor. An 8bit Digital-to-Analog (D/A) converter provides an offset correction with
a range of 50% of the FSR (Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable gains
of 1 to 128 with an effective resolution of 19 bits at a gain of 128.
The A/D conversion is accomplished with a second-order deltasigma modulator and programmable sinc filter. The reference input
is differential and can be used for ratiometric cancellation. The onboard current DACs (Digital-to-Analog Converters) operate independently with the maximum current set by an external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O are
also provided that can be used for input or output. The ADS1216 is
designed for high-resolution measurement applications in smart
transmitters, industrial process control, weight scales, chromatography, and portable instrumentation.
V
AGND AV
AV
DD
R
REFOUTVRCAPVREF+VREF–
8-Bit
IDAC
8-Bit
IDAC
Offset
DAC
DAC
1.25V or
2.5V
Reference
DD
2µA
X
X
IN
Clock Generator
OUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
AIN0
1
A
IN
2
A
IN
3
A
IN
4
A
IN
5
A
IN
6
A
IN
7
A
IN
A
INCOM
www.ti.com
IN+
MUX
BUF PGA
IN–
2µA
AGND
DD
+
A = 1:128
2nd-Order
Modulator
Digital I/O
Interface
...D0
Program-
mable
Digital
Filter
DSYNCPDWN RESET DRDYD7BUFENDGNDDV
Controller
Registers
RAM
Serial Interface
POL
SCLK
D
D
CS
IN
OUT
Copyright © 2000, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...................................................................... –0.3V to +6V
DV
to DGND...................................................................... –0.3V to +6V
DD
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
................................................................... GND –0.5V to AVDD + 0.5V
IN
AV
to DVDD........................................................................... –6V to +6V
DD
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND.................................... –0.3V to DV
Digital Output Voltage to GND ................................. –0.3V to DV
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
(1)
DD
DD
+ 0.3V
+ 0.3V
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PACKAGE SPECIFIED
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
ADS1216Y TQFP-48 PFB –40 to +85 ADS1216Y ADS1216Y/250 Tape and Reel
"""""ADS1216Y/2K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., / 2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS1216Y/2K” will get a single 2000-piece Tape and Reel.
(1)
MEDIA
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes sinc
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
Gain Error
(1)
(1)
(1)
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
to T
MIN
(AIN0 – AIN7, A
(1)
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
)
INCOM
Buffer ON AGND + 0.05 AV
3
Filter 24 Bits
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
SIG
f
SIG
= 50Hz, f
= 60Hz, f
DATA
DATA
DATA
DATA
DATA
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 150kΩ, f
DAC
DATA
= 10Hz,
ADS1216
+ 0.1 V
DD
– 1.5 V
DD
/PGA V
REF
DATA
DATA
DATA
/(2 • PGA) V
REF
Hz
Hz
Hz
7.5 ppm of FS
0.02 ppm of FS/°C
0.005 %
0.5 ppm/°C
= 10Hz 130 dB
= 50Hz 120 dB
= 60Hz 120 dB
= 50Hz 100 dB
= 60Hz 100 dB
(2)
OUT
/∆VDD)
80 95 dB
2
ADS1216
SBAS171B
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– AGND AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 1 2.4 2.50 2.6 V
Short-Circuit Current Source 8mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 15 ppm/°C
Noise V
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance See Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DV
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 1.6 2.5 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
MIN
to T
, AVDD = +5V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 150kΩ, f
DAC
ADS1216
V
≡ (REF IN+) – (REF IN–) 0.1 2.5 2.6 V
REF
VREFCM
= 60Hz, f
V
REF
= 60Hz 120 dB
DATA
= 2.5V 1.3 µA
DD
REF HI = 0 1.25 V
= 0.1µF, BW = 0.1Hz to 100Hz 10 µVp-p
RCAP
= 150kΩ, Range = 1 0.5 mA
DAC
R
= 150kΩ, Range = 2 1 mA
DAC
R
= 150kΩ, Range = 3 2 mA
DAC
R
= 15kΩ, Range = 3 20 mA
DAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 140 225 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 430 650 µA
= 10kΩ Indefinite
DAC
R
= 0Ω 10 Minute
DAC
= 150kΩ 8 Bits
DAC
= AVDD/2 400 ppm/V
OUT
– 1 V
DD
0.25 %
15 ppm/°C
DD
4.75 5.25 V
PGA = 1, Buffer ON 180 275 µA
PGA = 128, Buffer ON 800 1250 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
= 5V 180 275 µA
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 5V
DD
= 5V 150 µA
DD
230 µA
PDWN 1 nA
I
OFF, DVDD = 5V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
= 10Hz,
V
ADS1216
SBAS171B
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Analog Input Range Buffer OFF AGND – 0.1 AV
Full-Scale Input Voltage Range (In+) – (In–) See Block Diagram ±V
Input Impedance Buffer OFF 5/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
2
Sinc
Filter –3dB 0.318 • f
3
Sinc
Filter –3dB 0.262 • f
Programmable Gain Amplifier User Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes sinc
Integral Non-Linearity End Point Fit ±0.0015 % of FS
Offset Error
Offset Drift
Gain Error
(1)
(1)
(1)
Gain Error Drift
Common-Mode Rejection at DC 100 dB
Normal-Mode Rejection f
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆V
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0 AV
V
REF
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
Bias Current
(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage REF HI = 0 1.2 1.25 1.3 V
Short-Circuit Current Source 3mA
Short-Circuit Current Sink 50 µA
Short-Circuit Duration Sink or Source Indefinite
Drift 15 ppm/°C
Noise V
Output Impedance Sourcing 100µA3Ω
Startup Time 50 µs
IDAC
Full-Scale Output Current R
Maximum Short-Circuit Current Duration R
Monotonicity R
Compliance Voltage 0AV
Output Impedance See Typical Characteristics
PSRR V
Absolute Error Individual IDAC 5 %
Absolute Drift Individual IDAC 75 ppm/°C
Mismatch Error
Mismatch Drift
to T
MIN
(AIN0 – AIN7, A
(1)
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
)
INCOM
Buffer ON AGND + 0.05 AV
3
Filter 24 Bits
f
= 60Hz, f
CM
f
= 50Hz, f
CM
f
= 60Hz, f
CM
SIG
f
SIG
V
≡ (REF IN+) – (REF IN–) 0.1 1.25 1.3 V
REF
VREFCM
= 0.1µF, BW = 0.1Hz to 100Hz 10 µVp-p
RCAP
DAC
R
DAC
R
DAC
R
DAC
DATA
DATA
DATA
= 50Hz, f
DATA
= 60Hz, f
DATA
= 60Hz, f
DATA
V
= 1.25V 0.65 µA
REF
= 75kΩ, Range = 1 0.5 mA
= 75kΩ, Range = 2 1 mA
= 75kΩ, Range = 3 2 mA
= 15kΩ, Range = 3 20 mA
= 10kΩ Indefinite
DAC
R
= 0Ω 10 Minute
DAC
= 75kΩ 8 Bits
DAC
= AVDD/2 600 ppm/V
OUT
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 75kΩ, f
DAC
DATA
= 10Hz,
ADS1216
+ 0.1 V
DD
– 1.5 V
DD
/PGA V
REF
DATA
DATA
DATA
/(2 • PGA) V
REF
15 ppm of FS
0.04 ppm of FS/°C
0.010 %
1.0 ppm/°C
= 10Hz 130 dB
= 50Hz 120 dB
= 60Hz 120 dB
= 50Hz 100 dB
= 60Hz 100 dB
OUT
/∆VDD)
75 90 dB
DD
(2)
= 60Hz 120 dB
– 1 V
DD
0.25 %
15 ppm/°C
Hz
Hz
Hz
V
4
ADS1216
SBAS171B
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications T
V
≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
REF
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AV
Analog Current (I
ADC Current (I
V
Current (I
REF
I
Current (I
DAC
Digital Current Normal Mode, DV
Power Dissipation PGA = 1, Buffer OFF, REFEN = 0, 0.6 1.2 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Calibration can minimize these errors. (2) ∆ V
MIN
to T
, AVDD = +3V, DVDD = +2.7V to 5.25V, f
MAX
= 19.2kHz, PGA = 1, Buffer ON, R
MOD
= 75kΩ, f
DAC
ADS1216
+ I
+ I
ADC
VREF
) PGA = 1, Buffer OFF 120 200 µA
ADC
) PDWN = 0, or SLEEP 1 nA
DAC
PGA = 128, Buffer OFF 370 600 µA
DD
2.7 3.3 V
PGA = 1, Buffer ON 170 250 µA
PGA = 128, Buffer ON 750 1200 µA
) 250 375 µA
VREF
) Excludes Load Current 480 675 µA
DAC
SLEEP Mode, DV
Read Data Continuous Mode, DVDD = 3V
= 3V 90 200 µA
DD
= 3V 75 µA
DD
113 µA
PDWN = 0 1 nA
I
OFF, DVDD = 3V
DACS
is change in digital result. (3) 12pF switched capacitor at f
OUT
clock frequency.
SAMP
DATA
= 10Hz,
DIGITAL SPECIFICATIONS: T
MIN
to T
, DVDD 2.7V to 5.25V
MAX
PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input/Output
Logic Family CMOS
Logic Level: V
Input Leakage: I
Master Clock Rate: f
IH
V
IL
V
OH
V
OL
IH
I
IL
Master Clock Period: t
OSC
OSC
0.8 • DV
DD
DGND 0.2 • DV
IOH = 1mA DVDD – 0.4 V
IOL = 1mA DGND DGND + 0.4 V
VI = DV
DD
VI = 0 –10 µA
1 5 MHz
1/f
OSC
200 1000 ns
DV
DD
DD
10 µA
V
V
ADS1216
SBAS171B
5
PIN CONFIGURATION
Top View TQFP
AGND
V
REFOUT
V
V
D0
D1
D2
D3
D4
D5
D6
D7
REF+
REF–
OUTDIN
D
SCLKCSDRDY
DVDDDGND
DSYNC
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
ADS1216
43
44
45
46
47
48
12345678910112512
0
1
2
3
4
5
IN
IN
IN
A
A
AV
DD
AGND
IN
IN
A
IN
A
A
A
POL
6
IN
A
PDWN
7
IN
A
OUTXIN
X
INCOM
A
AGND
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
DGND
R
DAC
IDAC2
IDAC1
V
RCAP
AV
DD
PIN DESCRIPTIONS
PIN
NUMBER NAME DESCRIPTION
1AV
DD
2 AGND Analog Ground
3A
4A
5A
6A
7A
8A
9A
10 A
11 A
IN
IN
IN
IN
IN
IN
IN
IN
INCOM
12 AGND Analog Ground
13 AV
14 V
DD
RCAP
15 IDAC1 Current DAC1 Output
16 IDAC2 Current DAC2 Output
17 R
DAC
18-22 DGND Digital Ground
23 BUFEN Buffer Enable
24 RESET Active LOW, resets the entire chip.
Analog Power Supply
0 Analog Input 0
1 Analog Input 1
2 Analog Input 2
3 Analog Input 3
4 Analog Input 4
5 Analog Input 5
6 Analog Input 6
7 Analog Input 7
Analog Input Common
Analog Power Supply
V
Bypass CAP
REF
Current DAC Resistor
PIN
NUMBER NAME DESCRIPTION
25 X
26 X
IN
OUT
Clock Input
Clock Output, used with crystal or resonator.
27 PDWN Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
28 POL Serial Clock Polarity
29 DSYNC Active LOW, Synchronization Control
30 DGND Digital Ground
31 DV
DD
Digital Power Supply
32 DRDY Active LOW, Data Ready
33 CS Active LOW, Chip Select
34 SCLK Serial Clock, Schmitt Trigger
35 D
36 D
IN
OUT
Serial Data Input, Schmitt Trigger
Serial Data Output
37-44 D0-D7 Digital I/O 0-7
45 AGND Analog Ground
46 V
47 V
48 V
REFOUT
REF+
REF–
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
6
ADS1216
SBAS171B
TIMING DIAGRAMS
CS
SCLK
(POL = 0)
SCLK
(POL = 1)
D
IN
t
3
t
4
MSB
t
1
t
5
t
2
t
6
t
2
t
10
t
11
LSB
t
D
OUT
(Command or Command and Data)
7
MSB
t
8
(1)
LSB
t
9
(1)
NOTE: (1) Bit Order = 0.
SCLK Reset Waveform
ADS1216
Resets On
Falling Edge
t
13
t
13
SCLK
t
12
t
14
t
15
t
t
17
RESET, DSYNC, PDWN
16
DRDY
TIMING CHARACTERISTICS
SPEC DESCRIPTION MIN MAX UNITS
t
1
t
2
t
3
t
4
t
5
t
6
(1)
t
7
(1)
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
NOTE: (1) Load = 20pF 10kΩ to DGND. (2) CS may be tied LOW.
SCLK Period 4t
3 DRDY Periods
SCLK Pulse Width, HIGH and LOW 200 ns
CS LOW to first SCLK Edge; Setup Time
(2)
0ns
DIN Valid to SCLK Edge; Setup Time 50 ns
Valid DIN to SCLK Edge; Hold Time 50 ns
Delay between last SCLK edge for DIN and first SCLK
edge for D
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OUT
:
CSREG, CSRAMX, CSRAM 200 t
CSARAM, CSARAMX 1100 t
SCLK Edge to Valid New D
SCLK Edge to D
Last SCLK Edge to D
NOTE: D
OUT
, Hold Time 0 ns
OUT
Tri-State 6 10 t
OUT
goes tri-state immediately when CS goes HIGH.
OUT
50 ns
CS LOW time after final SCLK edge 0 ns
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, t
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC 4 t
CREG, CRAM 220 t
CREGA 1600 t
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Command, SCLK or Pin) 16 t
300 500 t
5t
550 750 t
1050 1250 t
Pulse Width 4t
DOR Data Not Valid 4 t
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
Periods
ADS1216
SBAS171B
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64 PGA128
15
14
13
Sinc3 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
PGA1
PGA2
PGA4
PGA8
21
20
19
18
17
16
ENOB (rms)
PGA16
PGA32
PGA64
PGA128
15
14
13
Sinc3 Filter, V
= 1.25V, BUFFER OFF
REF
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
MOD
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA2
PGA1
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
14
13
PGA16
PGA32
PGA64
Sinc3 Filter, Buffer ON
PGA128
12
0 500 1000 1500 2000
f
Decimation Ratio =
MOD
f
DATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
PGA8
20
19
18
17
16
ENOB (rms)
15
PGA16
PGA32
PGA64
PGA128
14
13
Sinc3 Filter, V
= 1.25, BUFFER ON
REF
12
0 500 1000 1500 2000
Decimation Ratio
8
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
PGA1
PGA2
PGA4
20
19
18
17
16
ENOB (rms)
PGA32
PGA16 PGA64
15
14
13
Sinc2 Filter
12
0 500 1000 1500 2000
f
Decimation Ratio =
f
DATA
MOD
PGA8
PGA128
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
FAST SETTLING FILTER
22
21
20
19
18
17
16
ENOB (rms)
15
14
13
Fast Settling Filter
12
f
MOD
f
DATA
1500
0 500 1000 1500 2000
Decimation Ratio =
ADS1216
SBAS171B
TYPICAL CHARACTERISTICS (Cont.)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
CMRR vs FREQUENCY
Frequency of CM Signal (Hz)
1 10 100 1k 10k 100k
CMRR (dB)
AVDD = +5V, DVDD = +5V, f
= 2.4576MHz, PGA = 1, R
OSC
= 150kΩ, f
DAC
= 10Hz, V
DATA
≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
REF
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Noise (rms, ppm of FS)
0.1
0
–2.5 –1.5 0.5–0.5 1.5 2.5
120
110
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
110 1k100 10k 100k
NOISE vs INPUT SIGNAL
(V)
V
IN
PSRR vs FREQUENCY
Frequency of Power Supply (Hz)
50
0
–50
–100
Offset (ppm of FS)
–150
–200
–50 –30 10–10 30 50 70 90
OFFSET vs TEMPERATURE
PGA1
PGA64
PGA128
Temperature (°C)
PGA16
1.00010
1.00006
1.00002
0.99998
0.99994
Gain (Normalized)
0.99990
0.99986
–50 –30 10–10 30 50 70 90
ADS1216
SBAS171B
GAIN vs TEMPERATURE
Temperature (°C)
10
–2
INL (ppm of FS)
–4
–6
–8
–10
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
8
6
4
+85°C
2
0
–2.5 –2 –1 –0.5–1.5 0 0.5 1 1.5 2 2.5
–40°C
+25°C
V
(V)
IN
9
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