TEXAS INSTRUMENTS ADS1174, ADS1178 Technical data

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ADS1174

ADS1178

PRODUCTPREVIEW

VREFP VREFN AVDD DVDD

TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[8:1] CLKDIV

Control

Logic

SPI and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC SCLK DOUT[8:1] DIN

Input2

Input1

Input4

Input3

Input6

Input5

Input8

Input7

PWDN[4:1]

ADS1178

Four Digital Filters

AVDD DVDD

TEST[1:0] FORMAT[2:0] CLK SYNC

CLKDIV

Control

Logic

SPI and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC SCLK DOUT[4:1] DIN

ADS1174

MODE

Eight Digital Filters

VREFP VREFN

Input2

Input1

Input4

Input3

查询ADS1174供应商

Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters

FEATURES

234

• Synchronously Sample Four/Eight Channels

• Selectable Operating Modes:

High-Speed: 52kSPS Data Rate, 30mW/ch Low-Power: 10kSPS Data Rate, 8mW/ch

• AC Performance:

25kHz Bandwidth 97dB SNR – 105dB THD

• Digital Filter:

Linear Phase Response Passband Ripple: ± 0.005dB Stop Band Attenuation: 100dB

• Selectable SPI™ or Frame Sync Serial

Interface

• Simple Pin-Driven Control

• Low Sampling Aperture Error

• Specified from – 40 ° C to +105 ° C

• Analog Supply: 5V

• I/O Supply: 1.8V to 3.3V

• Digital Core Supply: 1.8V

APPLICATIONS

• 3-Phase Power Monitors

• Defibrillators and ECG Monitors

• Coriolis Flow Meters

• Vibration/Modal Analysis

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

DESCRIPTION

The ADS1174 (quad) and ADS1178 (octal) are multiple delta-sigma ( Δ Σ ) analog-to-digital converters (ADCs) with data rates up to 52k samples-per-second (SPS), which allow synchronous sampling of four and eight channels. These devices use identical packages, permitting drop-in expandability.

The delta-sigma architecture offers near ideal 16-bit ac performance (97dB SNR, – 105dB THD, 1LSB linearity) combined with 0.005dB passband ripple, and linear phase response.

The high-order, chopper- stabilized modulator achieves very low drift (4 μ V/ ° C offset, 4ppm/ ° C gain) and low noise (1LSB response (FIR) filter provides a usable signal bandwidth up to 90% of the Nyquist rate with 100dB of stop band attenuation while suppressing modulator and signal out-of-band noise.

Two operating modes allow for optimization of speed and power: High-speed mode (32mW/Ch at 52kSPS), and Low-power mode (8mW/Ch at 10kSPS).

A SYNC input control pin allows the device conversions to be started and synchronized to an external event. SPI and Frame-Sync serial interfaces are supported. The device is fully specified over the extended industrial range ( – 40 ° C to +105 ° C) and is available in an HTQFP-64 PowerPAD™ package.

). The on-chip finite impulse

2 PowerPAD is a trademark of Texas Instruments. 3 SPI is a trademark of Motorola, Inc. 4 All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ADS1174 ADS1178

SBAS373 – OCTOBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

AVDD to AGND – 0.3 to +6.0 V DVDD, IOVDD to DGND – 0.3 to +3.6 V AGND to DGND – 0.3 to +0.3 V

Input Current

Analog Input to AGND – 0.3 to AVDD + 0.3 V Digital Input or Output to DGND – 0.3 to DVDD + 0.3 V Maximum Junction Temperature +150 ° C Operating Temperature Range – 40 to +105 ° C Storage Temperature Range – 60 to +150 ° C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(1)

ADS1174, ADS1178 UNIT

100, Momentary mA

10, Continuous mA

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ELECTRICAL CHARACTERISTICS

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f VREFN = 0V, and all channels active, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage (FSR Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 V Common-mode input voltage VCM= (AINP + AINN)/2 2.5 V

Differential input impedance

DC PERFORMANCE

Resolution No missing codes 16 Bits

Data rate (f

Integral nonlinearity (INL) Differential input 0.5 TBD LSB Offset error 0.150 TBD mV Offset drift 1.8 μ V/ ° C Offset match TBD mV Gain error 0.1 TBD % Gain drift 2 ppm/ ° C Gain match TBD % Noise Shorted input 1 TBD LSB Common-mode rejection fCM= 60Hz 100 dB

Power-supply rejection

AC PERFORMANCE

Crosstalk VIN= 1kHz, – 0.5dBFS 107 dB Sampling aperture match 200 ps Signal-to-noise ratio (SNR) (unweighted) 97 dB Total harmonic distortion (THD) Spurious-free dynamic range – 108 dB Passband ripple ± 0.005 dB Passband 0.453 f – 3dB Bandwidth 0.49 f Stop band attenuation 100 dB Stop band 0.547 f Group delay 38/f Settling time (latency) Complete settling 76/f

)

DATA

(1) FSR = full-scale range = 2V (2) THD includes the first nine harmonics of the input signal.

(1)

) VIN= (AINP – AINN) ± V

High-Speed mode 28 k Ω Low-Power mode 140 k Ω

High-Speed mode 52,734 SPS Low-Power mode 10,547 SPS

AVDD f = 60Hz 80 dB DVDD f = 60Hz 80 dB

(2)

High-Speed mode VIN= 1kHz, – 0.5dBFS – 105 dB

REF

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

= 27MHz, VREFP = 2.5V,

CLK

ADS1174, ADS1178

REF

DATA DATA

DATA

63.453 f

DATA DATA DATA

Hz Hz

s s

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ADS1174 ADS1178

SBAS373 – OCTOBER 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f VREFN = 0V, and all channels active, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOLTAGE REFERENCE INPUTS

Reference input voltage (V Negative reference input (VREFN) AGND – 0.1 VREFP – 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V

ADS1174 Reference Input impedance

ADS1178 Reference Input impedance

DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)

Input leakage 0 < V Master clock rate (f

POWER SUPPLY

AVDD 4.75 5 5.25 V DVDD 1.65 1.8 1.95 V IOVDD 1.65 3.3 3.6 V

ADS1174 AVDD current

ADS1178 AVDD current

ADS1174 DVDD current

ADS1178 DVDD current

ADS1174 IOVDD current

ADS1178 IOVDD current

ADS1174 Power dissipation

ADS1178 Power dissipation

CLK

) V

REF

) 0.1 27 MHz

= 27MHz, VREFP = 2.5V,

CLK

ADS1174, ADS1178

= VREFP – VREFN 0.5 2.5 3.1 V

REF

High-Speed mode 2.6 k Ω Low-Power mode 13 k Ω High-Speed mode 1.3 Low-Power mode 6.5

0.7 IOVDD IOVDD V DGND 0.3 IOVDD V

IOH= 5mA 0.8 IOVDD IOVDD V IOL= 5mA DGND 0.2 IOVDD V

< IOVDD ± 10 μ A

IN DIGITAL

High-Speed mode 22 TBD mA Low-Power mode 5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 40 TBD mA Low-Power mode 9 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 9 TBD mA Low-Power mode 2.5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 17 TBD mA Low-Power mode 4.5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 100 TBD μ A Low-Power mode 100 TBD μ A Power-Down mode 1 TBD μ A High-Speed mode 150 TBD μ A Low-Power mode 150 TBD μ A Power-Down mode 1 TBD μ A High-Speed mode 125 TBD mW Low-Power mode 32 TBD mW High-Speed mode 225 TBD mW Low-Power mode 60 TBD mW

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PRODUCTPREVIEW

ADS1174/ADS1178 PIN ASSIGNMENTS

AINN7

(1)

AINP7

(1)

AINN8

(1)

AINP8

(1)

AVDD

AGND

PWDN1

PWDN2

PWDN3

PWDN4

PWDN5

(1)

PWDN6

(1)

PWDN7

(1)

PWDN8

(1)

MODE

IOVDD

AINP2

AINN2

AINP1

AINN1

AVDD

AGND

DGND

TEST0

TEST1

CLKDIV

SYNC

DIN

DOUT8

(1)

DOUT7

(1)

DOUT6

(1)

DOUT5

(1)

AINN3

AINP3

AINN4

AINP4

AVDD

AGND

VREFN

VREFP

VCOM

AGND

AVDD

AINP5

(1)

AINN6

(1)

AINP6

(1)

AINN5

(1)

DOUT4

DOUT3

DOUT2

DOUT1

DGND

IOVDD

DGND

DVDD

CLK

SCLK

DRDY

/FSYNC

FORMAT2

FORMAT1

FORMAT0

ADS1174/ADS1178

AGND

(PowerPADOutline)

NOTE:(1) pinnamesarefor only;Boldface ADS1178

seepindescriptions.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

PAP PACKAGE

HTQFP-64

(TOP VIEW)

NAME NO. FUNCTION DESCRIPTION

AGND Analog ground Analog ground; connect to DGND using a single plane. AINP1 3 Analog input

AINP2 1 Analog input AINP3 63 Analog input ADS1178: AINP[8:1] Positive analog input, channels 8 through 1. AINP4 61 Analog input AINP5 51 Analog input ADS1174: AINP[8:5] Connected to internal ESD rails. The inputs may float. AINP6 49 Analog input AINP7 47 Analog input

6, 43, 54,

58, 59

AINP8 45 Analog input

ADS1174/ADS1178 PIN DESCRIPTIONS

AINP[4:1] Positive analog input, channels 4 through 1.

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ADS1174 ADS1178

SBAS373 – OCTOBER 2007

NAME NO. FUNCTION DESCRIPTION

AINN1 4 Analog input AINN2 2 Analog input AINN3 64 Analog input ADS1178: AINN[8:1] Negative analog input, channels 8 through 1. AINN4 62 Analog input AINN5 52 Analog input ADS1174: AINN[8:5] Connected to internal ESD rails. The inputs may float. AINN6 50 Analog input AINN7 48 Analog input AINN8 46 Analog input

AVDD 5, 44, 53, 60 Analog power supply Analog power supply (4.75V to 5.25V).

VCOM 55 Analog output AVDD/2 Unbuffered analog output. VREFN 57 Analog input Negative reference input. VREFP 56 Analog input Positive reference input.

CLK 27 Digital input Master clock input (maximum 27MHz).

CLKDIV 10 Digital input

DGND 7, 21, 24, 25 Digital ground Digital ground power supply.

DIN 12 Digital input Daisy-chain data input. DOUT1 20 Digital output DOUT1 is TDM data output (TDM mode). DOUT2 19 Digital output DOUT3 18 Digital output ADS1178: DOUT[8:1] Data output for channels 8 through 1. DOUT4 17 Digital output DOUT5 16 Digital output ADS1174: DOUT[8:5] Internally connected to active circuitry; outputs are driven. DOUT6 15 Digital output DOUT7 14 Digital output DOUT8 13 Digital output

DRDY/

FSYNC

DVDD 26 Digital power supply Digital core power supply (+1.65V to +1.95V). FORMAT0 32 Digital input FORMAT1 31 Digital input outputs, fixed/dynamic position TDM data, and modulator mode/normal operating FORMAT2 30 Digital input

IOVDD 22, 23, 33 Digital power supply I/O power supply (+1.65V to +3.6V).

MODE 34 Digital input

MODE1 33 Digital input PWDN1 42 Digital input PWDN2 41 Digital input PWDN3 40 Digital input ADS1178: PWDN[8:1] Power-down control for channels 8 through 1. PWDN4 39 Digital input PWDN5 38 Digital input ADS1174: PWDN[8:5] must = 0V. PWDN6 37 Digital input PWDN7 36 Digital input PWDN8 35 Digital input

SCLK 28 Digital input Serial clock input.

SYNC 11 Digital input Synchronize input (all channels). TEST0 8 Digital input TEST[1:0] Test mode select: TEST1 9 Digital input

29 Digital input/output Frame-Sync protocol: frame clock input; SPI protocol: data ready output.

ADS1174/ADS1178 PIN DESCRIPTIONS (continued)

AINN[4:1] Negative analog input, channels 4 through 1.

CLK input divider control: 1 = 27MHz

0 = 13.5MHz (high-speed) / 5.4MHz (low-power)

DOUT[4:1] Data output for channels 4 through 1.

FORMAT[2:0] Selects between Frame-Sync/SPI protocol, TDM/discrete data mode.

MODE: 0 = High-Speed mode

1 = Low-Power mode.

PWDN[4:1] Power-down control for channels 4 through 1.

00 = normal operation 11 = boundary scan test mode

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CLK

CPW

CLK

CPW

DIST

DOHD

SPW

Bit15(MSB) Bit14 Bit13

SPW

DOPD

MSBPD

DIHD

· · ·

CONV

DRDY

SCLK

DOUT

DIN

For TA= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

CONV

(2)

MSBPD

(2)

(3)

SPW

(2) (4)

DOHD

(2)

DOPD

DIST

(4)

DIHD

(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (f (2) Load on DRDY and DOUT = 20pF. (3) For best performance, use f (4) t

DOHD

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.

CLK period (1/f

CLK

CLK positive or negative pulse width 15 ns Conversion period (1/f Falling edge of CLK to falling edge of DRDY 22 ns Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 CLK period DRDY falling edge to DOUT MSB valid (propagation delay) 12 ns Falling edge of SCLK to rising edge of DRDY 18 ns SCLK period t SCLK positive or negative pulse width 0.4t SCLK falling edge to new DOUT invalid (hold time) 10 ns SCLK falling edge to new DOUT valid (propagation delay) 31 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

SCLK

SBAS373 – OCTOBER 2007

TIMING CHARACTERISTICS: SPI FORMAT

TIMING REQUIREMENTS: SPI FORMAT

) 37 10,000 ns

(1)

)

DATA

CLK

ratios of 1, 1/2, 1/4, 1/8, etc.

CLK

(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

DIHD

DATA

256 2560 CLK periods

CLK CLK

0.6t

CLK

ADS1174 ADS1178

ns ns

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SCLK

FSYNC

DOUT

DIN

DOHD

FPW

SPW

FRAME

FPW

DIHD

MSBPD

DIST

Bit15(MSB) Bit14 Bit13

DOPD

CLK

CPW

CLK

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

For TA= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

FRAME

FPW

SPW

(3) (4)

DOHD

(3)

DOPD

MSBPD

DIST

(4)

DIHD

(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (f (2) t

DOHD

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns. (3) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f (4) Load on DOUT = 20pF.

CLK period (1/f CLK positive or negative pulse width 15 ns Falling edge of CLK to falling edge of SCLK – 0.35 t Frame period (1/f FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns Rising edge of SCLK to rising edge of FSYNC 5 ns SCLK period

(2)

SCLK positive or negative pulse width 0.4 t SCLK falling edge to old DOUT invalid (hold time) 6 ns SCLK falling edge to new DOUT valid (propagation delay) 28 ns FSYNC rising edge to DOUT MSB valid (propagation delay) 28 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

) 37 10,000 ns

CLK

(1)

)

DATA

(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

DIHD

CLK

DATA

CLK

256 2560 CLK periods

CLK

SCLK

0.35 t

0.6 t

CLK

SCLK

ns ns

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Modulator1

Digital Filter1

VREFP

IN1

VREFN

REF

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN

(1)

[4:1]/[8:1]

CLKDIV

MODE

DRDY/FSYNC

SCLK

DOUT[4:1]/[8:1]

(1)

DIN

SPI and

Frame-Sync

Interface

Control

Logic

AINP1

AINN1

VCOM

Modulator2

Digital Filter2

IN2

AINP2

AINN2

Modulator4/8

(1)

Digital

Filter4/8

(1)

IN4/8

AINP4/8

(1)

AINN4/8

(1)

DVDDAVDD

AGND DGND

IOVDD

NOTE:(1)TheADS1174hasfourchannels;theADS1178haseightchannels.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

OVERVIEW

The ADS1174 (quad) and ADS1178 (octal) are 16-bit, delta-sigma ADCs. They offer the combination of excellent linearity, low noise, and low power consumption. Figure 1 shows the block diagram. Note that both devices are the same, except the ADS1174 In High-Speed mode, the data rate is 52kSPS, and in has four ADCs, and the ADS1178 has eight ADCs. Low-Power mode, the power dissipation is only The pinout and package of the ADS1178 is 8mW/channel at 10.5kSPS. compatible with the ADS1174, permitting drop-in expandability. The converters are comprised of either four (ADS1174) or eight (ADS1178) advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters. The modulators measure the differential input signal, V

(AINP – AINN), against the differential reference, V

= (VREFP – VREFN). The digital filters receive

REF

the modulator signal and provide a low-noise digital output.

To allow tradeoffs between speed and power, two modes of operation are supported: High-Speed and Low-Power. Table 1 summarizes the performance of each mode.

The ADS1174/78 is configured by simply setting the appropriate I/O pins — there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1174/78 has a daisy-chainable output and the

ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels.

MODE (SPS) (Hz) (dB) (LSB

High-Speed 52,734 23,889 97 1 32 Low-Power 10,547 4,536 97 1 8

(1) Measured with all channels operating.

Figure 1. ADS1174/ADS1178 Block Diagram

Table 1. Operating Mode Performance Summary

DATA RATE PASSBAND SNR NOISE PER CHANNEL

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) (mW)

POWER DISSIPATION

(1)

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ADS1174 ADS1178

SBAS373 – OCTOBER 2007

FUNCTIONAL DESCRIPTION

The ADS1174 and ADS1178 are delta/sigma ADCs consisting of independent converters that digitize input signals in parallel. The ADS1174 consists of four independent converters, while the ADS1178 has eight independent converters.

The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1's density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced.

In operation, the signal inputs and reference inputs ADS1174/78 channels. are sampled by the modulator at a high rate (typically 64x higher than the final output data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. This process results in very low levels of noise within the signal passband.

Because the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. This high sampling rate greatly relaxes the requirement of external antialiasing filters allowing very low passband phase errors.

SAMPLING APERTURE MATCHING

The converters of the ADS1174/78 operate from the same CLK input. The CLK input controls the timing of the modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling aperture match, between channels is controlled to within 200ps. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. This design results in excellent phase match among the

The phase match of one four-channel ADS1174 to that of another ADS1174 may not have the same degree of sampling match (the same is true for the 8-channel ADS1178). As a result of manufacturing variations, differences in internal propagation delay of the internal CLK signal coupled with differences of the arrival of the external CLK signal to each device may cause larger sampling match errors. Equal length CLK traces or external clock distribution devices can be used to control the arrival of the CLK signals to help reduce the sampling match error.

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FREQUENCY RESPONSE

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

NormalizedInputFrequency(f /f

IN TDA A

)

Amplitude(dB)

0.45 0.47 0.49 0.51 0.53 0.55

-20

-40

-60

-80

-100

-120

-140

0.4

NormalizedInputFrequency(fIN/f

DATA

)

Amplitude(dB)

0 0.2 0.6 0.8 1.0

-20

-40

-60

-80

-100

-120

-140

-160

InputFrequency(f /f

IN DATA

)

Gain(dB)

0 16 32 48 64

0.02

-0.02

-0.04

-0.06

-0.08

-0.10

0.2

NormalizedInputFrequency(f /f

IN DATA

)

Amplitude(dB)

0 0.1 0.3 0.4 0.5 0.6

The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: f both High-Speed and Low-Power modes.

Figure 2 shows the frequency response of the

ADS1174/78 normalized to f

DATA

passband ripple. The transition from passband to stop band is illustrated in Figure 4 . The overall frequency response repeats at 64x multiples of the modulator frequency f

, as shown in Figure 5 .

MOD

) is 64 for

DATA

. Figure 3 shows the

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

Figure 4. Transition Band Response

Figure 2. Frequency Response

Figure 3. Passband Response

Figure 5. Frequency Response Out to f

MOD

These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. Table 2 lists the degree of image rejection versus external antialiasing filter order. The stop band of the ADS1174/78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to f

MOD

Placing an antialiasing, low-pass filter in front of the ADS1174/78 inputs is recommended to limit possible high-amplitude, out-of-band signals and noise.

Table 2. Antialiasing Filter Order Image Rejection

ANTIALIASING FILTER IMAGE REJECTION (dB)

ORDER (f

1 39 2 75 3 111

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at f

– 3dB

)

DATA

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) V

REF

215* 1

* V

REF

215* 1

REF

215* 1

100

Settling(%)

Conversions(1/f

DATA

)

0 2010 4030 6050 8070

FullySettledData

at76Conversions

InitialValue

FinalValue

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

PHASE RESPONSE DATA FORMAT

The ADS1174/78 incorporates a multiple stage, linear The ADS1174/78 outputs 16 bits of data in two ’ s phase digital filter. Linear phase filters exhibit complement format. constant delay time versus input frequency (constant group delay), which means the time delay from any instant of the input signal to the same instant of the output data is constant, and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.

SETTLING TIME

As with frequency and phase response, the digital filter also determines settling time. Figure 6 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given in units of conversion. Note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. The output data is fully settled after 76 conversion periods.

A positive full-scale input produces an ideal output code of 7FFFh, and the negative full-scale input produces an ideal output code of 8000h. The output clips at these codes for signals exceeding full-scale.

Table 3 summarizes the ideal output codes for

different input signals.

Table 3. Ideal Output Code versus Input Signal

INPUT SIGNAL V

(AINP – AINN) IDEAL OUTPUT CODE

≥ +V

0 0000h

REF

7FFFh

0001h

FFFFh

(1)

Figure 6. Step Response

8000h

(1) Excludes effects of noise, INL, offset, and gain errors.

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PRODUCTPREVIEW

ANALOG INPUTS (AINP, AINN)

ESDProtection

AVDDAGND

AVDD

AINP

9pF

AINN

AGND

OFF

SAMPLE MOD

=1/f

AINP

AINN

Z =14k

eff MO

W ´ (6.75MHz/fD)

The ADS1174/78 measures each differential input signal V differential reference V most positive measurable differential input is +V which produces the most positive digital output code of 7FFFh. Likewise, the most negative measurable differential input is – V negative digital output code of 8000h.

For optimum performance, the inputs of the ADS1174/78 are intended to be driven differentially. For single-ended input applications, one of the inputs (AINP or AINN) can be driven while the other input is fixed (typically, to AGND or +2.5V); fixing the input to +2.5V permits bipolar operation, thereby using the full range of the converter.

While the ADS1174/78 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is:

– 0.1V < (AINN or AINP) < AVDD + 0.1V If either input is taken below – 0.4V or above (AVDD +

0.4), ESD protection diodes on the inputs may turn on.

If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe levels (see Absolute Selection

Maximum Ratings table ).

The ADS1174/78 is a high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1174/78 inputs. See the Applications Information section for the recommended circuits.

The ADS1174/78 uses switched-capacitor circuitry to The average load presented by the switched measure the input voltage. Internal capacitors are capacitor input can be modeled with an effective charged by the inputs and then discharged. Figure 7 differential impedance, as shown in Figure 9 . Note shows a conceptual diagram of these circuits. Switch that the effective impedance is a function of f S

represents the net effect of the modulator circuitry

in discharging the sampling capacitor; the actual implementation is different. The timing for switches S and S (t

SAMPLE

frequency (f CLKDIV input, and frequency of CLK, as shown in

Table 4 .

= (AINP – AINN) against the common

is shown in Figure 8 . The sampling time

= (VREFP – VREFN). The

REF

, which produces the most

REF

) is the inverse of modulator sampling

) and is a function of the mode, the

MOD

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

REF

Figure 7. Equivalent Analog Input Circuitry

Figure 8. S

Table 4. Modulator Frequency (f

MODE SELECTION CLKDIV f

and S

High-Speed

Low-Power

Switch Timing for Figure 7

) versus Mode

MOD

1 f 0 f 1 f 0 f

MOD

CLK

/40

CLK

MOD

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Figure 9. Effective Input Impedances

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PRODUCTPREVIEW

ESD

Protection

AVDDAVDD

VREFN

VREFP

AGND

VREFP VREFN

Z =

eff

´ (6.75MHz/f )

MOD

5.2kW

N =numberofactivechannels.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

VOLTAGE REFERENCE INPUTS (VREFP, VREFN) clamp diodes or series resistors may be required to

The voltage reference for the ADS1174/78 ADC is the differential voltage between VREFP and VREFN: V

= (VREFP – VREFN). The voltage reference is Note that the valid operating range of the reference

REF

common to the four channels. The reference inputs inputs is limited to the following: use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 10 . As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in

Figure 11 . However, the reference input impedance

depends on the number of active (enabled) channels in addition to f

. As a result of the change of

MOD

reference input impedance caused by enabling and disabling channels, the regulation and settling time of the external reference should be noted, so as not to affect the readings of other channels.

Figure 10. Equivalent Reference Input Circuitry

If these conditions are possible, external Schottky limit the input current to safe levels (see Absolute

Maximum Ratings table ).

– 0.1V ≤ VREFN ≤ VREFP – 0.5V VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V A high-quality reference voltage with the appropriate

drive strength is essential for achieving the best performance from the ADS1174/78. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits.

CLOCK INPUT (CLK)

The ADS1174/78 requires a clock input for operation. Each ADS1174/78 converter operates from the same clock input. At the maximum data rate, the clock input can be either 27MHz or 13.5MHz (5.4MHz, low power), determined by the setting of the CLKDIV input. The selection of the external clock frequency (f

) does not affect the resolution (the oversampling

CLK

ratio, OSR, remains fixed) or power dissipation of the ADS1174/78. However, using a slower f reduce the power consumption of an external clock driver. The output data rate scales with clock frequency, down to a minimum clock frequency of f

= 100kHz. Table 5 summarizes the ratio of clock

CLK

input frequency (f

) to data rate (f

CLK

DATA

data rate and corresponding maximum clock input for the two operating modes.

CLK

), maximum

can

ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4V, and likewise do not exceed AVDD by

0.4V.

Figure 11. Effective Reference Impedance

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Table 5. Clock Input Options

MODE f

SELECTION (MHz) CLKDIV f

High-Speed 52,734

Low-Power 10,547

CLK

27 1 512

13.5 0 256 27 1 2,560

5.4 0 512

CLK

DATA RATE

DATA

(SPS)

As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 50 Ω series resistor, placed close to the source end, often helps.

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PRODUCTPREVIEW

MODE[1:0]

Pins

ADS1174/78

Mode

NewMode

ValidDataReady

DRDY

SPI

Protocol

Frame-Sync

Protocol

NDR-SPI

DOUT

NewMode

ValidDataonDOUT

NDR-FS

Mode

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

MODE SELECTION (MODE) SYNCHRONIZATION ( SYNC)

The ADS1174/78 supports two modes of operation: The ADS1174/78 can be synchronized by pulsing the High-Speed and Low-Power. These modes offer SYNC pin low and then returning the pin high. When optimization of speed or power. The mode selection the pin goes low, the conversion process stops, and is determined by the status of the digital input MODE the internal counters used by the digital filter are pins, as shown in Table 6 . The ADS1174/78 reset. When the SYNC pin returns high, the constantly monitors the status of the MODE pin conversion process restarts. Synchronization allows during operation. the conversion to be aligned with an external event,

such as a reference timing pulse.

Table 6. Mode Selection

MODE MODE SELECTION MAX f

0 High-Speed 52,734 1 Low-Power 10,547 synchronization with each other. The sampling

(1) f

= 27MHz (CLKDIV = 1).

CLK

(1)

DATA

When using the SPI protocol, DRDY is held high after a mode change occurs until settled (or valid) data are ready, as shown in Figure 12 and Table 7 .

In Frame-Sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready, as shown in Figure 12 and Table 7 . Data can be read from the device to detect when DOUT changes to logic 1, indicating valid data.

Since the converters of the ADS1174/78 operate in parallel from the same master clock and use the same SYNC input control, they are, by default, in

aperture match among the channels is 200ps (typical). However, the synchronization of multiple ADS1174/78s is somewhat different. At device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing.

The SYNC pin can be used to synchronize multiple ADS1174/78s to within the same CLK cycle.

Figure 13 illustrates the timing requirement of SYNC

and CLK in SPI format. See Figure 14 for the Frame-Sync format timing

requirement.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

NDR-SPI

NDR-FS

Time for new data to be ready (SPI) 129 Conversions (1/f Time for new data to be ready (Frame-Sync) 127 128 Conversions (1/f

Figure 12. Mode Change Timing

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Table 7. Mode Change

)

DATA

)

DATA

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PRODUCTPREVIEW

CLK

DRDY

SYNC

NDR

SYN

SCSU

CSHD

FSYNC

ValidData

DOUT

SYNC

NDR

SYN

CLK

CSHD

SCSU

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

After synchronization, indication of valid data In the Frame-Sync format, DOUT goes low as soon depends on the whether SPI or Frame-Sync format as SYNC is taken low; see Figure 14 . After SYNC is was used. returned high, DOUT stays low while the digital filter

In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 13 . After SYNC is returned high, DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low.

Figure 13. Synchronization Timing for SPI Protocol

is settling. Once valid data are ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC high, and must then remain running.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

CSHD

SCSU

SYN

NDR

CLK to SYNC hold time 10 ns SYNC to CLK setup time 5 ns Synchronize pulse width 1 CLK periods Time for new data to be ready 129 Conversions (1/f

Figure 14. Synchronization Timing for Frame-Sync Protocol

SYMBOL DESCRIPTION MIN TYP MAX UNITS

CSHD

SCSU

SYN

NDR

CLK to SYNC hold time 10 ns SYNC to CLK setup time 5 ns Synchronize pulse width 1 CLK periods Time for new data to be ready 127 128 Conversions (1/f

Table 8. SPI Protocol

Table 9. Frame-Sync Protocol

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)

DATA

)

DATA

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PRODUCTPREVIEW

POWER-DOWN ( PWDN)

NOTE:(1)InSPIprotocol,thetimingoccursonthefallingedgeof /FSYNC.Poweringdownallchannelsforces /FSYNChigh.DRDY DRDY

CLK

DRDY/FSYNC

(1)

DOUT

(DiscreteDataOutputMode)

· · ·· · ·

PWDN

NDR

PDWN

P -UpDataostPower

DOUT1

(TDMMode,DynamicPosition)

NormalPosition

NormalPositionDataShiftPosition

NormalPosition

NormalPositionDataRemaininPosition

DOUT1

(TDMMode,FixedPosition)

The ADS1174/78 measurement channels can be independently powered down by use of the PWDN

2. Wait for 129/f high.

inputs. To enter the power-down mode, take the 3. Detect for non-zero data in the powered-up respective PWDN pin low. Power-down occurs after channel. two f against false transitions caused by external noise. To exit power-down, return the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1174/78 enters a microwatt ( μ W) power state where all internal biasing is powered-down. In this event, the TEST[1:0] input pins must be driven; all other input pins can float (the ADS1174/78 outputs remain driven).

As shown in Figure 15 and Table 10 , a maximum of 129 conversion cycles must elapse before reading data after exiting power-down. The data from channels already running are not affected. The user software can perform the required delay time in the following ways:

1. Count the number of data conversions after

cycles have elapsed. This delay guards

CLK

taking the PWDN pin high.

After powering-up one or more channels, the channels are synchronized to each other. It is not necessary to use the SYNC pin to synchronize them.

When a channel is powered down in TDM data format, the data for the powered-down channel will either be forced to zero (fixed-position TDM data mode) or be replaced by shifting the data from the next channel into the vacated data position (dynamic-position TDM data mode).

In discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. See the Data Format section for details.

after taking the PWDN pins

DATA

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

Figure 15. Power-Down Timing

Table 10. Power-Down Timing

SYMBOL DESCRIPTION MIN TYP MAX UNITS

PDWN

NDR

PDWN pulse width to enter Power-Down mode 2 CLK periods Time for new data to be ready (SPI) 129 130 Conversions (1/f Time for new data to be ready (Frame-Sync) 128 129 Conversions (1/f

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)

DATA

)

DATA

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PRODUCTPREVIEW

DRDY

SCLK

1/f

DATA

1/f

CLK

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

FORMAT[2:0]

Data can be read from the ADS1174/78 with two serial interface protocols (SPI or Frame-Sync) and several options of data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select among the options. Table 11 lists the available options. See the DOUT Modes section for details of the DOUT modes and data positions.

Table 11. Data Output Format

FORMAT[2:0] PROTOCOL MODE POSITION

000 SPI TDM Dynamic 001 SPI TDM Fixed 010 SPI Discrete — 011 Frame-Sync TDM Dynamic 100 Frame-Sync TDM Fixed 101 Frame-Sync Discrete —

INTERFACE DOUT DATA

SERIAL INTERFACE PROTOCOLS

Data are retrieved from the ADS1174/78 using the serial interface. Two protocols are available: SPI and Frame-Sync. The same pins are used for both interfaces: SCLK, DRDY/FSYNC, DOUT[4:1] (or DOUT[8:1] for the ADS1178), and DIN. The FORMAT[2:0] pins select the desired interface protocol.

SPI SERIAL INTERFACE

The SPI-compatible format is a simple read-only interface. Data ready for retrieval are indicated by the falling DRDY output and are shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple ADS1174/78s. See the Daisy-Chaining section for more information.

recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. For best performance, use f

SCLK

ratios of 1, 1/2, 1/4, 1/8,

CLK

etc. NOTE: One CLK period is required after DRDY falls, to start shifting data (see Timing Requirements:

SPI Format ).

DRDY/FSYNC (SPI Format)

In the SPI format, this pin functions as the DRDY output. It goes low when data are ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data are not retrieved (that is, SCLK is held low), DRDY will pulse high just before the next conversion data are ready, as shown in

Figure 16 . The new data are loaded within one CLK

cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten.

Figure 16. DRDY Timing with No Readback

DOUT

In Discrete Data Output mode, the conversion data are output on the individual DOUT pins (DOUT1, DOUT2, etc.), whereas in TDM mode, data are output only on DOUT1. The MSB data are valid on DOUT[4:1]/[8:1] when DRDY goes low. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining (TDM mode), the data shifted in using DIN will appear on DOUT1 after all channel data have been shifted out.

SCLK

The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user typically shifts this data in on the rising edge. Even though the SCLK input has hysteresis, it is

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DIN

This input is used when multiple ADS1174/78s are to be daisy-chained together. The DOUT1 pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1174/78, tie DIN low. See the

Daisy-Chaining section for more information.

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ADS1174 ADS1178

SBAS373 – OCTOBER 2007

FRAME-SYNC SERIAL INTERFACE

Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion — the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified. When using Frame-Sync format, the FSYNC and SCLK inputs must be continuously running with the required relationships shown in the

Frame-Sync Timing Requirements .

SCLK

The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. The number of SCLKs within a frame period (FSYNC clock) can be any power of two ratio of clock cycles (1, 1/2, 1/4, etc.), as long as the number of cycles is sufficient to shift the data output from all channels within one data frame.

DRDY/FSYNC (Frame-Sync Format)

In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period which must be same as the data rate. The required number of f

cycles to each FSYNC period

CLK

depends on the mode selection and the CLKDIN input. Table 5 indicates the number of CLK cycles to each frame (f

CLK

). If the FSYNC period is not

DATA

the proper value, data readback will be corrupted.

DOUT

In Discrete Data Output mode, the conversion data are shifted out on the individual DOUT pins (DOUT1, DOUT2, etc.), whereas in TDM mode, data are output only on DOUT1. The MSB data become valid on DOUT[4:1]/[8:1] on the SCLK rising edge prior to FSYNC going high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining (TDM mode), the data shifted in using DIN will appear on DOUT1 after all channel data have been shifted out (that is, 4 channels × 16 bits per channel = 64 bits for the ADS1174, and 8 channels × 16 bits per channel = 128 bits for the ADS1178).

DIN

This input is used when multiple ADS1174/78s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1174/78, tie DIN low. See the Daisy-Chaining section for more information.

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PRODUCTPREVIEW

CH1

DOUT1

( )ADS1174

SCLK

DRDY

(SPI)

FSYNC

(Frame-Sync)

1 2

16 1715 32 3331

4947 64 6563 6766

CH1

DOUT1

( )ADS1178

113

CH2

CH3

CH4

DIN

CH5

127

CH8 DIN

128 129 130 131

CH1

DOUT1

( )ADS1174

CH2 CH3 DINCH4

SCLK

DRDY

(SPI)

FSYNC

(Frame-Sync)

1 2

16 1715 32 3331 48 4947 64

63 66

CH1

DOUT1

( )ADS1178

CH2 CH3 CH5CH4

113

CH8 DIN

127 128

129

130 131

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

DOUT MODES

For both SPI and Frame-Sync interface protocols, either the data are shifted out through individual channel DOUT pins in a parallel data format (Discrete mode), or the data for all channels are shifted out in series through common pin DOUT1 (TDM mode).

TDM Mode

In TDM (time division multiplexed) data output mode, the data for all channels are shifted out, in series, on a single pin (DOUT1). As shown in Figure 17 , the data from channel 1 are shifted out first, followed by channel 2 data, etc. After the data from the last channel are shifted out (channel 4 for the ADS1174 or channel 8 for the ADS1178), the data from the DIN input follow. The DIN is used to daisy-chain the data

output from another ADS1174, ADS1178, or other compatible device. Note that when all channels of the ADS1174/78 are powered-down, the interface is powered-down, rendering the DIN input powered-down as well. When one or more channels of the device are powered-down, the data format of the TDM mode can be fixed or dynamic.

TDM Mode, Fixed-Position Data

In this TDM data output mode, the data position of the channels remains fixed, regardless of whether channels are disabled. If a channel is powered-down, data are forced to zero but occupies the same position within the data stream. Figure 18 shows the data stream with channel 1 and channel 3 powered-down.

Figure 18. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered-Down)

Figure 17. TDM Mode (All Channels Enabled)

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PRODUCTPREVIEW

CH2

DOUT1

( )ADS1174

CH4 DIN

SCLK

DRDY

(SPI)

FSYNC

(Frame-Sync)

1 2

16 1715 32 3331

34 35

CH2

DOUT1

( )ADS1178

CH4 CH5

CH8 DIN

80 81 95 96 97 98

CH1DOUT1

CH2DOUT2

CH3DOUT3

CH4DOUT4

SCLK

DRDY

(SPI)

FSYNC

(Frame-Sync)

1 2 14 15 16

CH5DOUT5

CH6DOUT6

CH7DOUT7

CH8DOUT8

ADS1178 Only

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

TDM Mode, Dynamic Position Data Discrete Data Output Mode

In this TDM data output mode, when a channel is In Discrete data output mode, the channel data are powered-down, the data from higher channels shift shifted out in parallel using individual channel data one position in the data stream to fill the vacated data output pins DOUT[4:1] for the ADS1174, or slot. Figure 19 shows the data stream with channel 1 DOUT[8:1] for the ADS1178. After the 16th SCLK, and channel 3 powered-down. the channel data are forced to zero. The data are

also forced to zero for powered-down channels.

Figure 20 depicts the data format.

Figure 19. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered-Down)

Figure 20. Discrete Data Output Mode

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PRODUCTPREVIEW

SYNC

CLK

SYNC

DIN DOUT1

SCLK SCLK

ADS1178

SYNC

DIN

CLK CLK

DOUT1

DRDY

SerialDatafromDevices1and2

DRDY OutputfromDevice1

SCLK

ADS1178

DIN2

CH1,U1DOUT1 CH2,U1 CH3,U1 CH4,U1 CH5,U1 CH1,U2 CH2,U2 DIN2

SCLK

DRDY

(SPI)

FSYNC

(Frame-Sync)

1 2

17 3318 34 49 50 65 66

129 130 145 146 257 258

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

DAISY-CHAINING

Multiple ADS1174/78s can be daisy-chained together to simplify the serial interface connections. The DOUT1 data output pin of one ADS1174/78 is connected to the DIN of the next ADS1174/78. As

Figure 21 illustrates, the DOUT1 pin of device 1

provides the output data to a controller, and the DIN of device 2 is grounded. Figure 22 describes the data format when reading data back in a daisy-chain configuration.

Figure 21. Daisy-Chaining of Two ADS1178s, SPI Protocol (FORMAT[2:0] = 011 or 100)

The maximum number of channels that may be daisy-chained in this way is limited by the frequency of f The frequency of f

, the mode selection, and the CLKDIV input.

SCLK

must be high enough to

SCLK

completely shift the data out from all channels within one f of daisy-chained channels when f

period. Table 12 lists the maximum number

DATA

= f

SCLK

CLK

Table 12. Maximum Channels in a Daisy-Chain (f

MODE SELECTION CLKDIV MAXIMUM NUMBER OF CHANNELS

High-Speed

Low-Power

Figure 22. Daisy-Chain Data Format of Figure 21

1 32 0 16 1 160 0 32

= f

SCLK

)

CLK

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PRODUCTPREVIEW

SYNC

DIN

DOUT1

SYNC

SCLK

FSYNC

SCLK

ADS1178

SYNC

DIN

CLK

FSYNC

DOUT1

SCLK

ADS1178

SYNC

DOUT1

SCLK

ADS1178

SYNC

DIN

FSYNC

DOUT1

SCLK

ADS1178

CLK CLK CLK

FSYNC

DIN

FSYNC

Serial Data from Devices 1and2

Serial Data from Devices 3and4

U4 U3 U2 U1

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

To increase the number of data channels possible in Whether the interface protocol is SPI or Frame-Sync, a chain, a segmented DOUT scheme may be used, it is recommended to synchronize all devices by tying producing two data streams. Figure 23 illustrates four the SYNC inputs together. When synchronized in SPI ADS1178s, with a pair of ADS1178s daisy-chained protocol, it is only necessary to monitor the DRDY together. The channel data of each daisy-chained output of one ADS1178. pair is shifted out in parallel and is received by the processor through independent data channels.

In Frame-Sync interface protocol, the data from all devices are ready on the rising edge of FSYNC.

Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time for DIN. Minimize the skew in SCLK to avoid timing violations.

Figure 23. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 000 or 001)

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PRODUCTPREVIEW

DRDY

(SPI)

DOUT

(Frame-Sync)

InternalReset

CLK

1VNom

(1)

IOVDD

1VNom

(1)

DVDD

3.5VNom

(1)

AVDD

ValidData

CLK

128

DATA

NOTE:(1)Thepower-supplyresetthresholdsareapproximate.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

POWER-UP SEQUENCE

The ADS1174/78 has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply. The IOVDD and DVDD power supplies can be tied together if desired. To achieve rated performance, it is critical that the power supplies are bypassed with 0.1 μ F and +10 μ F capacitors placed as close as possible to the supply pins. A single 1 μ F ceramic capacitor may be substituted in place of the two capacitors.

Figure 24 shows the power-up sequence of the

ADS1174/78. The power supplies can be sequenced in any order. Each supply has an internal reset circuit where the outputs are summed together to generate an internal global power-on reset. After the supplies have exceeded the reset thresholds, 2

cycles

CLK

are counted before the converter initiates the conversion process. After all the f

cycles are

CLK

counted, the data for 128 conversions is suppressed by the ADS1174/78 to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero. The power supplies should be applied before any analog or digital pin is driven.

Figure 24. Power-Up Sequence

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PRODUCTPREVIEW

NOTE:BufferisrequiredifVCOMisusedforanypurpose.

OPA350

0.1 Fm

VCOM VDD/2)(A»

ADS1174/ADS1178

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

BOUNDARY SCAN TEST[1:0] INPUTS

The Boundary Scan test mode feature of the ADS1174/78 allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 13 . Note that some of the digital input pins become outputs.

Table 13. Test Mode Pin Map (TEST[1:0] = 11)

TEST MODE PIN MAP

INPUT PINS OUTPUT PINS

PWDN1 DOUT1 PWDN2 DOUT2 PWDN3 DOUT3

PWDN4 DOUT4 PWDN5 PWDN6 PWDN7 PWDN8

FORMAT0 CLKDIV FORMAT1 DRDY/FSYNC FORMAT2 SCLK

(1) The CLK input does not have a test output; SYNC = 1 and is

an output.

(2) ADS1178 only.

(2) (2) (2) (2)

MODE DIN

(1)

(2)

DOUT5

(2)

DOUT6

(2)

DOUT7

(2)

DOUT8

Therefore, if using boundary scan tests, the ADS1174/78 digital I/O should connect to a JTAG-compatible device. The analog input, power supply, and ground pins remain connected as normal. The test mode is engaged by the setting the pins TEST[1:0] = 11. For normal converter operation, set TEST[1:0] = 00.

VCOM OUTPUT

The VCOM pin is an analog output of approximately AVDD/2. This voltage may be used to set the common-mode voltage of the input buffers. However, the pin must be buffered. A 0.1 μ F capacitor to AGND is recommended to reduce noise pick-up.

Figure 25. VCOM Output

Product Folder Link(s): ADS1174 ADS1178

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PRODUCTPREVIEW

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

To obtain the specified performance from the ADS1174/78, the following layout and component guidelines should be considered.

1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The range for DVDD is 1.65V to 1.95V; the range of IOVDD is 1.65V to 3.6V; and AVDD is restricted to 4.75V to 5.25V. For all supplies, use a 10 μ F tantalum capacitor, bypassed with a

0.1 μ F ceramic capacitor, placed close to the device pins. Alternatively, a single 10 μ F ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply source is used, the voltage ripple should be low (< 2mV) and the switching frequency outside the passband of the converter. A 1nF to 10nF capacitor should be used directly The power supplies may be sequenced in any across the analog input pins, AINP and AINN. A order. low-k dielectric (such as COG or film type) should

2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter.

3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50 Ω series resistors. The resistors should be placed close to the driving end of the digital source (oscillator, logic gates, DSP, etc.) This placement helps to reduce ringing on the digital lines, which may lead to degraded ADC performance.

4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk.

APPLICATION INFORMATION

5. Reference Inputs: It is recommended to use a minimum 10 μ F tantalum with a 0.1 μ F ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3 μ V higher than this, external reference filtering may be necessary.

6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (for ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks.

be used to maintain low THD. Capacitors from each analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the AC common-mode performance.

7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components.

Figure 26 to Figure 28 illustrate basic connections

and interfaces that can be used with the ADS1174/78.

in-band noise. For references with noise

RMS

Product Folder Link(s): ADS1174 ADS1178

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PRODUCTPREVIEW

Input1

AINP1

AINN1

Input2

AINP2

AINN2

Input3

AINP3

AINN3

Input4

+3.3V

AINP4

AINN4

AVDD

DVDD

VREFP

VREFN

VCOM

TEST0 TEST1 DIN AGND DGND

IOVDD

CLK

DRDY/FSYNC

DVDD(I/O)

CLKOUT(27MHz)

McBSP

PORT

SCLK

DOUT1

CVDD

(CORE)

DOUT2

DOUT3

DOUT4

SYNC

PWDN1

I/O

PWDN2

PWDN3

PWDN4

CLKDIV

MODE

FORMAT2 FORMAT1

FORMAT0

10 Fm

(1)

10 Fm

(1)

10 Fm

OPA350

0.1 Fm

(1)

0.1 Fm

(1)

100 Fm

0.1 Fm

(1)

100W1kW

REF1004

+5V

10 Fm

(1)

50W

+3.3V (27MHzclockinputselected)

(Low-Power,Frame-Sync,TDM, andFixed-Positiondataselected.)

+3.3V

ADS1174 TMS320VC5509

200MHz

+1.6V

OPA1632

2.2nF

(2)

2.2nF

(2)

2.2nF

(2)

2.2nF

(2)

JTAG

Device

(3)

(1)Indicatesceramiccapacitors. (2)IndicatesCOGceramiccapacitors. (3)Optional.Forboundaryscantest,theADS1174digitalI/OshouldconnecttoaJTAG-compatibledevice.

+1.8V

OPA350

Buffered

VCOM Output

47W

100W

20kW

+15V

(1)

NOTES:

(1)Bypasswith10 Fand0.1 Fcapacitors.m m (2)15nFforLow-Speedmode.

-15V

(1)

49.9W

AINP

OPA1632

AINN

OCM

0.1 Fm

1kW1kW

49.9W

2.7nF

(2)

2.7nF

(2)

Buffered

VCOM Output

+15V

(1)

NOTES:

(1)Bypasswith10 Fand0.1 Fcapacitors.m m (2)56nFforLow-Speedmode.

-15V

(1)

Buffered

VCOM Output

OPA1632

49.9W

AINP

AINN

V =0.25 V´

INO DIFF

V =V

O COMM REF

OCM

0.1 Fm

249W1kW

49.9W

10nF

(2)

10nF

(2)

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

Figure 26. ADS1174 Basic Connection Drawing

Product Folder Link(s): ADS1174 ADS1178

Figure 27. Basic Differential Input Signal Interface

Figure 28. Basic Single-Ended Input Signal

Interface

www.ti.com

PRODUCTPREVIEW

ICDie

WireBond WireBond

LeadframeDiePad

ExposedatBaseofPackage

DieAttachEpoxy

(thermallyconductive)

Leadframe

MoldCompount

(Epoxy)

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

PowerPAD THERMALLY-ENHANCED

die pad to be attached to the PCB using standard

PACKAGING flow soldering techniques. This soldering allows

The PowerPAD concept is implemented in standard epoxy resin package material. The integrated circuit is attached to the leadframe die pad using thermally conductive epoxy. The package is molded so that the leadframe die pad is exposed at a surface of the package. This exposure provides an extremely low thermal resistance to the path between the IC junction and the exterior case. The external surface of the leadframe die pad is located on the printed Figure 29 illustrates a cross-section view of a circuit board (PCB) side of the package, allowing the PowerPAD package.

efficient attachment to the PCB and permits the board structure to be used as a heat-sink for the package. Using a thermal pad identical in size to the die pad and vias connected to the PCB ground plane, the board designer can now implement power packaging without additional thermal hardware (for example, external heat sinks) or the need for specialized assembly instructions.

Figure 29. Cross-Section View of a PowerPAD Thermally-Enhanced Package

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PRODUCTPREVIEW

13mils(0.33mm)

Package

ThermalPad

Component

Traces

ThermalVia

Component(top)Side

GroundPlane

PowerPlane

Solder(bottom)Side

ThermalIsolation (powerplaneonly)

Package

ThermalPad

(bottomtrace)

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

PowerPAD PCB Layout Considerations for the ADS1174/78

Figure 30 shows the recommended layer structure for

thermal management when using a PowerPad package on a 4-layer PCB design. Note that the thermal pad is placed on both the top and bottom sides of the board. The ground plane is used as the heat-sink, while the power plane is thermally isolated from the thermal vias.

Figure 31 shows the required thermal pad etch

pattern for the 64-lead HTQFP package used for the ADS1174/78. Nine 13mil (0.33mm) thermal vias plated with one ounce of copper are placed within the thermal pad area for the purpose of connecting the pad to the ground plane layer. The ground plane is used as a heatsink in this application. It is very important that the thermal via diameter be no larger than 13mils in order to avoid solder wicking during the reflow process. Solder wicking results in thermal voids that reduce heat dissipation efficiency and hamper heat flow away from the IC die.

The via connections to the thermal pad and internal ground plane should be plated completely around the hole, as opposed to the typical web or spoke thermal relief connection. Plating entirely around the thermal via provides the most efficient thermal connection to the ground plane.

Additional PowerPAD Package Information

Texas Instruments publishes the PowerPAD Thermally Enhanced Package Application Report (TI

literature number SLMA002 ), available for download at www.ti.com , which provides a more detailed discussion of PowerPAD design and layout considerations. Before attempting a board layout with the ADS1174/78, it is recommended that the hardware engineer and/or layout designer be familiar with the information contained in this document .

Figure 30. Recommended PCB Structure for a 4-Layer Board

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PRODUCTPREVIEW

40mils(1mm)

118mils(3mm)

40mils(1mm)

118mils(3mm)

ThermalVia

13mils(0.33mm)

316mils(8mm)

ThermalPad

PackageOutline

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

Figure 31. Thermal Pad Etch and Via Pattern for the 64-Lead HTQFP Package

Product Folder Link(s): ADS1174 ADS1178

PACKAGE OPTION ADDENDUM

www.ti.com

8-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

ADS1174IPAPR PREVIEW HTQFP PAP 64 1000 TBD Call TI Call TI ADS1174IPAPT PREVIEW HTQFP PAP 64 250 TBD Call TI Call TI ADS1178IPAPR PREVIEW HTQFP PAP 64 1000 TBD Call TI Call TI ADS1178IPAPT PREVIEW HTQFP PAP 64 250 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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TEXAS INSTRUMENTS ADS1174, ADS1178 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual