TEXAS INSTRUMENTS ADS1174, ADS1178 Technical data

    

ADS1174

ADS1178

PRODUCTPREVIEW

VREFP VREFN AVDD DVDD

TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[8:1] CLKDIV

Control

Logic

SPI and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC SCLK DOUT[8:1] DIN

Input2

Input1

Input4

Input3

Input6

Input5

Input8

Input7

PWDN[4:1]

ADS1178

Four Digital Filters

AVDD DVDD

TEST[1:0] FORMAT[2:0] CLK SYNC

CLKDIV

Control

Logic

SPI and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC SCLK DOUT[4:1] DIN

ADS1174

MODE

Eight Digital Filters

VREFP VREFN

Input2

Input1

Input4

Input3

查询ADS1174供应商

Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters

FEATURES

234

• Synchronously Sample Four/Eight Channels

• Selectable Operating Modes:

High-Speed: 52kSPS Data Rate, 30mW/ch Low-Power: 10kSPS Data Rate, 8mW/ch

• AC Performance:

25kHz Bandwidth 97dB SNR – 105dB THD

• Digital Filter:

Linear Phase Response Passband Ripple: ± 0.005dB Stop Band Attenuation: 100dB

• Selectable SPI™ or Frame Sync Serial

Interface

• Simple Pin-Driven Control

• Low Sampling Aperture Error

• Specified from – 40 ° C to +105 ° C

• Analog Supply: 5V

• I/O Supply: 1.8V to 3.3V

• Digital Core Supply: 1.8V

APPLICATIONS

• 3-Phase Power Monitors

• Defibrillators and ECG Monitors

• Coriolis Flow Meters

• Vibration/Modal Analysis

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

DESCRIPTION

The ADS1174 (quad) and ADS1178 (octal) are multiple delta-sigma ( Δ Σ ) analog-to-digital converters (ADCs) with data rates up to 52k samples-per-second (SPS), which allow synchronous sampling of four and eight channels. These devices use identical packages, permitting drop-in expandability.

The delta-sigma architecture offers near ideal 16-bit ac performance (97dB SNR, – 105dB THD, 1LSB linearity) combined with 0.005dB passband ripple, and linear phase response.

The high-order, chopper- stabilized modulator achieves very low drift (4 μ V/ ° C offset, 4ppm/ ° C gain) and low noise (1LSB response (FIR) filter provides a usable signal bandwidth up to 90% of the Nyquist rate with 100dB of stop band attenuation while suppressing modulator and signal out-of-band noise.

Two operating modes allow for optimization of speed and power: High-speed mode (32mW/Ch at 52kSPS), and Low-power mode (8mW/Ch at 10kSPS).

A SYNC input control pin allows the device conversions to be started and synchronized to an external event. SPI and Frame-Sync serial interfaces are supported. The device is fully specified over the extended industrial range ( – 40 ° C to +105 ° C) and is available in an HTQFP-64 PowerPAD™ package.

). The on-chip finite impulse

2 PowerPAD is a trademark of Texas Instruments. 3 SPI is a trademark of Motorola, Inc. 4 All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

PRODUCTPREVIEW

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

AVDD to AGND – 0.3 to +6.0 V DVDD, IOVDD to DGND – 0.3 to +3.6 V AGND to DGND – 0.3 to +0.3 V

Input Current

Analog Input to AGND – 0.3 to AVDD + 0.3 V Digital Input or Output to DGND – 0.3 to DVDD + 0.3 V Maximum Junction Temperature +150 ° C Operating Temperature Range – 40 to +105 ° C Storage Temperature Range – 60 to +150 ° C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(1)

ADS1174, ADS1178 UNIT

100, Momentary mA

10, Continuous mA

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

ELECTRICAL CHARACTERISTICS

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f VREFN = 0V, and all channels active, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage (FSR Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 V Common-mode input voltage VCM= (AINP + AINN)/2 2.5 V

Differential input impedance

DC PERFORMANCE

Resolution No missing codes 16 Bits

Data rate (f

Integral nonlinearity (INL) Differential input 0.5 TBD LSB Offset error 0.150 TBD mV Offset drift 1.8 μ V/ ° C Offset match TBD mV Gain error 0.1 TBD % Gain drift 2 ppm/ ° C Gain match TBD % Noise Shorted input 1 TBD LSB Common-mode rejection fCM= 60Hz 100 dB

Power-supply rejection

AC PERFORMANCE

Crosstalk VIN= 1kHz, – 0.5dBFS 107 dB Sampling aperture match 200 ps Signal-to-noise ratio (SNR) (unweighted) 97 dB Total harmonic distortion (THD) Spurious-free dynamic range – 108 dB Passband ripple ± 0.005 dB Passband 0.453 f – 3dB Bandwidth 0.49 f Stop band attenuation 100 dB Stop band 0.547 f Group delay 38/f Settling time (latency) Complete settling 76/f

)

DATA

(1) FSR = full-scale range = 2V (2) THD includes the first nine harmonics of the input signal.

(1)

) VIN= (AINP – AINN) ± V

High-Speed mode 28 k Ω Low-Power mode 140 k Ω

High-Speed mode 52,734 SPS Low-Power mode 10,547 SPS

AVDD f = 60Hz 80 dB DVDD f = 60Hz 80 dB

(2)

High-Speed mode VIN= 1kHz, – 0.5dBFS – 105 dB

REF

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

= 27MHz, VREFP = 2.5V,

CLK

ADS1174, ADS1178

REF

DATA DATA

DATA

63.453 f

DATA DATA DATA

Hz Hz

s s

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= – 40 ° C to +105 ° C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f VREFN = 0V, and all channels active, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOLTAGE REFERENCE INPUTS

Reference input voltage (V Negative reference input (VREFN) AGND – 0.1 VREFP – 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V

ADS1174 Reference Input impedance

ADS1178 Reference Input impedance

DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)

Input leakage 0 < V Master clock rate (f

POWER SUPPLY

AVDD 4.75 5 5.25 V DVDD 1.65 1.8 1.95 V IOVDD 1.65 3.3 3.6 V

ADS1174 AVDD current

ADS1178 AVDD current

ADS1174 DVDD current

ADS1178 DVDD current

ADS1174 IOVDD current

ADS1178 IOVDD current

ADS1174 Power dissipation

ADS1178 Power dissipation

CLK

) V

REF

) 0.1 27 MHz

= 27MHz, VREFP = 2.5V,

CLK

ADS1174, ADS1178

= VREFP – VREFN 0.5 2.5 3.1 V

REF

High-Speed mode 2.6 k Ω Low-Power mode 13 k Ω High-Speed mode 1.3 Low-Power mode 6.5

0.7 IOVDD IOVDD V DGND 0.3 IOVDD V

IOH= 5mA 0.8 IOVDD IOVDD V IOL= 5mA DGND 0.2 IOVDD V

< IOVDD ± 10 μ A

IN DIGITAL

High-Speed mode 22 TBD mA Low-Power mode 5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 40 TBD mA Low-Power mode 9 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 9 TBD mA Low-Power mode 2.5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 17 TBD mA Low-Power mode 4.5 TBD mA Power-Down mode 1 TBD μ A High-Speed mode 100 TBD μ A Low-Power mode 100 TBD μ A Power-Down mode 1 TBD μ A High-Speed mode 150 TBD μ A Low-Power mode 150 TBD μ A Power-Down mode 1 TBD μ A High-Speed mode 125 TBD mW Low-Power mode 32 TBD mW High-Speed mode 225 TBD mW Low-Power mode 60 TBD mW

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

ADS1174/ADS1178 PIN ASSIGNMENTS

AINN7

(1)

AINP7

(1)

AINN8

(1)

AINP8

(1)

AVDD

AGND

PWDN1

PWDN2

PWDN3

PWDN4

PWDN5

(1)

PWDN6

(1)

PWDN7

(1)

PWDN8

(1)

MODE

IOVDD

AINP2

AINN2

AINP1

AINN1

AVDD

AGND

DGND

TEST0

TEST1

CLKDIV

SYNC

DIN

DOUT8

(1)

DOUT7

(1)

DOUT6

(1)

DOUT5

(1)

AINN3

AINP3

AINN4

AINP4

AVDD

AGND

VREFN

VREFP

VCOM

AGND

AVDD

AINP5

(1)

AINN6

(1)

AINP6

(1)

AINN5

(1)

DOUT4

DOUT3

DOUT2

DOUT1

DGND

IOVDD

DGND

DVDD

CLK

SCLK

DRDY

/FSYNC

FORMAT2

FORMAT1

FORMAT0

ADS1174/ADS1178

AGND

(PowerPADOutline)

NOTE:(1) pinnamesarefor only;Boldface ADS1178

seepindescriptions.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

PAP PACKAGE

HTQFP-64

(TOP VIEW)

NAME NO. FUNCTION DESCRIPTION

AGND Analog ground Analog ground; connect to DGND using a single plane. AINP1 3 Analog input

AINP2 1 Analog input AINP3 63 Analog input ADS1178: AINP[8:1] Positive analog input, channels 8 through 1. AINP4 61 Analog input AINP5 51 Analog input ADS1174: AINP[8:5] Connected to internal ESD rails. The inputs may float. AINP6 49 Analog input AINP7 47 Analog input

6, 43, 54,

58, 59

AINP8 45 Analog input

ADS1174/ADS1178 PIN DESCRIPTIONS

AINP[4:1] Positive analog input, channels 4 through 1.

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

NAME NO. FUNCTION DESCRIPTION

AINN1 4 Analog input AINN2 2 Analog input AINN3 64 Analog input ADS1178: AINN[8:1] Negative analog input, channels 8 through 1. AINN4 62 Analog input AINN5 52 Analog input ADS1174: AINN[8:5] Connected to internal ESD rails. The inputs may float. AINN6 50 Analog input AINN7 48 Analog input AINN8 46 Analog input

AVDD 5, 44, 53, 60 Analog power supply Analog power supply (4.75V to 5.25V).

VCOM 55 Analog output AVDD/2 Unbuffered analog output. VREFN 57 Analog input Negative reference input. VREFP 56 Analog input Positive reference input.

CLK 27 Digital input Master clock input (maximum 27MHz).

CLKDIV 10 Digital input

DGND 7, 21, 24, 25 Digital ground Digital ground power supply.

DIN 12 Digital input Daisy-chain data input. DOUT1 20 Digital output DOUT1 is TDM data output (TDM mode). DOUT2 19 Digital output DOUT3 18 Digital output ADS1178: DOUT[8:1] Data output for channels 8 through 1. DOUT4 17 Digital output DOUT5 16 Digital output ADS1174: DOUT[8:5] Internally connected to active circuitry; outputs are driven. DOUT6 15 Digital output DOUT7 14 Digital output DOUT8 13 Digital output

DRDY/

FSYNC

DVDD 26 Digital power supply Digital core power supply (+1.65V to +1.95V). FORMAT0 32 Digital input FORMAT1 31 Digital input outputs, fixed/dynamic position TDM data, and modulator mode/normal operating FORMAT2 30 Digital input

IOVDD 22, 23, 33 Digital power supply I/O power supply (+1.65V to +3.6V).

MODE 34 Digital input

MODE1 33 Digital input PWDN1 42 Digital input PWDN2 41 Digital input PWDN3 40 Digital input ADS1178: PWDN[8:1] Power-down control for channels 8 through 1. PWDN4 39 Digital input PWDN5 38 Digital input ADS1174: PWDN[8:5] must = 0V. PWDN6 37 Digital input PWDN7 36 Digital input PWDN8 35 Digital input

SCLK 28 Digital input Serial clock input.

SYNC 11 Digital input Synchronize input (all channels). TEST0 8 Digital input TEST[1:0] Test mode select: TEST1 9 Digital input

29 Digital input/output Frame-Sync protocol: frame clock input; SPI protocol: data ready output.

ADS1174/ADS1178 PIN DESCRIPTIONS (continued)

AINN[4:1] Negative analog input, channels 4 through 1.

CLK input divider control: 1 = 27MHz

0 = 13.5MHz (high-speed) / 5.4MHz (low-power)

DOUT[4:1] Data output for channels 4 through 1.

FORMAT[2:0] Selects between Frame-Sync/SPI protocol, TDM/discrete data mode.

MODE: 0 = High-Speed mode

1 = Low-Power mode.

PWDN[4:1] Power-down control for channels 4 through 1.

00 = normal operation 11 = boundary scan test mode

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

CLK

CPW

CLK

CPW

DIST

DOHD

SPW

Bit15(MSB) Bit14 Bit13

SPW

DOPD

MSBPD

DIHD

· · ·

CONV

DRDY

SCLK

DOUT

DIN

For TA= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

CONV

(2)

MSBPD

(2)

(3)

SPW

(2) (4)

DOHD

(2)

DOPD

DIST

(4)

DIHD

(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (f (2) Load on DRDY and DOUT = 20pF. (3) For best performance, use f (4) t

DOHD

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.

CLK period (1/f

CLK

CLK positive or negative pulse width 15 ns Conversion period (1/f Falling edge of CLK to falling edge of DRDY 22 ns Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 CLK period DRDY falling edge to DOUT MSB valid (propagation delay) 12 ns Falling edge of SCLK to rising edge of DRDY 18 ns SCLK period t SCLK positive or negative pulse width 0.4t SCLK falling edge to new DOUT invalid (hold time) 10 ns SCLK falling edge to new DOUT valid (propagation delay) 31 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

SCLK

SBAS373 – OCTOBER 2007

TIMING CHARACTERISTICS: SPI FORMAT

TIMING REQUIREMENTS: SPI FORMAT

) 37 10,000 ns

(1)

)

DATA

CLK

ratios of 1, 1/2, 1/4, 1/8, etc.

CLK

(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

DIHD

DATA

256 2560 CLK periods

CLK CLK

0.6t

CLK

ADS1174 ADS1178

ns ns

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

SCLK

FSYNC

DOUT

DIN

DOHD

FPW

SPW

FRAME

FPW

DIHD

MSBPD

DIST

Bit15(MSB) Bit14 Bit13

DOPD

CLK

CPW

CLK

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

For TA= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

CLK

CPW

FRAME

FPW

SPW

(3) (4)

DOHD

(3)

DOPD

MSBPD

DIST

(4)

DIHD

(1) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (f (2) t

DOHD

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns. (3) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f (4) Load on DOUT = 20pF.

CLK period (1/f CLK positive or negative pulse width 15 ns Falling edge of CLK to falling edge of SCLK – 0.35 t Frame period (1/f FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns Rising edge of SCLK to rising edge of FSYNC 5 ns SCLK period

(2)

SCLK positive or negative pulse width 0.4 t SCLK falling edge to old DOUT invalid (hold time) 6 ns SCLK falling edge to new DOUT valid (propagation delay) 28 ns FSYNC rising edge to DOUT MSB valid (propagation delay) 28 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

) 37 10,000 ns

CLK

(1)

)

DATA

(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

DIHD

CLK

DATA

CLK

256 2560 CLK periods

CLK

SCLK

0.35 t

0.6 t

CLK

SCLK

ns ns

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

Modulator1

Digital Filter1

VREFP

IN1

VREFN

REF

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN

(1)

[4:1]/[8:1]

CLKDIV

MODE

DRDY/FSYNC

SCLK

DOUT[4:1]/[8:1]

(1)

DIN

SPI and

Frame-Sync

Interface

Control

Logic

AINP1

AINN1

VCOM

Modulator2

Digital Filter2

IN2

AINP2

AINN2

Modulator4/8

(1)

Digital

Filter4/8

(1)

IN4/8

AINP4/8

(1)

AINN4/8

(1)

DVDDAVDD

AGND DGND

IOVDD

NOTE:(1)TheADS1174hasfourchannels;theADS1178haseightchannels.

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

OVERVIEW

The ADS1174 (quad) and ADS1178 (octal) are 16-bit, delta-sigma ADCs. They offer the combination of excellent linearity, low noise, and low power consumption. Figure 1 shows the block diagram. Note that both devices are the same, except the ADS1174 In High-Speed mode, the data rate is 52kSPS, and in has four ADCs, and the ADS1178 has eight ADCs. Low-Power mode, the power dissipation is only The pinout and package of the ADS1178 is 8mW/channel at 10.5kSPS. compatible with the ADS1174, permitting drop-in expandability. The converters are comprised of either four (ADS1174) or eight (ADS1178) advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters. The modulators measure the differential input signal, V

(AINP – AINN), against the differential reference, V

= (VREFP – VREFN). The digital filters receive

REF

the modulator signal and provide a low-noise digital output.

To allow tradeoffs between speed and power, two modes of operation are supported: High-Speed and Low-Power. Table 1 summarizes the performance of each mode.

The ADS1174/78 is configured by simply setting the appropriate I/O pins — there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1174/78 has a daisy-chainable output and the

ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels.

MODE (SPS) (Hz) (dB) (LSB

High-Speed 52,734 23,889 97 1 32 Low-Power 10,547 4,536 97 1 8

(1) Measured with all channels operating.

Figure 1. ADS1174/ADS1178 Block Diagram

Table 1. Operating Mode Performance Summary

DATA RATE PASSBAND SNR NOISE PER CHANNEL

Product Folder Link(s): ADS1174 ADS1178

) (mW)

POWER DISSIPATION

(1)

www.ti.com

PRODUCTPREVIEW

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

FUNCTIONAL DESCRIPTION

The ADS1174 and ADS1178 are delta/sigma ADCs consisting of independent converters that digitize input signals in parallel. The ADS1174 consists of four independent converters, while the ADS1178 has eight independent converters.

The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1's density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced.

In operation, the signal inputs and reference inputs ADS1174/78 channels. are sampled by the modulator at a high rate (typically 64x higher than the final output data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. This process results in very low levels of noise within the signal passband.

Because the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. This high sampling rate greatly relaxes the requirement of external antialiasing filters allowing very low passband phase errors.

SAMPLING APERTURE MATCHING

The converters of the ADS1174/78 operate from the same CLK input. The CLK input controls the timing of the modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling aperture match, between channels is controlled to within 200ps. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. This design results in excellent phase match among the

The phase match of one four-channel ADS1174 to that of another ADS1174 may not have the same degree of sampling match (the same is true for the 8-channel ADS1178). As a result of manufacturing variations, differences in internal propagation delay of the internal CLK signal coupled with differences of the arrival of the external CLK signal to each device may cause larger sampling match errors. Equal length CLK traces or external clock distribution devices can be used to control the arrival of the CLK signals to help reduce the sampling match error.

Product Folder Link(s): ADS1174 ADS1178

www.ti.com

PRODUCTPREVIEW

FREQUENCY RESPONSE

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

NormalizedInputFrequency(f /f

IN TDA A

)

Amplitude(dB)

0.45 0.47 0.49 0.51 0.53 0.55

-20

-40

-60

-80

-100

-120

-140

0.4

NormalizedInputFrequency(fIN/f

DATA

)

Amplitude(dB)

0 0.2 0.6 0.8 1.0

-20

-40

-60

-80

-100

-120

-140

-160

InputFrequency(f /f

IN DATA

)

Gain(dB)

0 16 32 48 64

0.02

-0.02

-0.04

-0.06

-0.08

-0.10

0.2

NormalizedInputFrequency(f /f

IN DATA

)

Amplitude(dB)

0 0.1 0.3 0.4 0.5 0.6

The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: f both High-Speed and Low-Power modes.

Figure 2 shows the frequency response of the

ADS1174/78 normalized to f

DATA

passband ripple. The transition from passband to stop band is illustrated in Figure 4 . The overall frequency response repeats at 64x multiples of the modulator frequency f

, as shown in Figure 5 .

MOD

) is 64 for

DATA

. Figure 3 shows the

ADS1174 ADS1178

SBAS373 – OCTOBER 2007

Figure 4. Transition Band Response

Figure 2. Frequency Response

Figure 3. Passband Response

Figure 5. Frequency Response Out to f

MOD

These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. Table 2 lists the degree of image rejection versus external antialiasing filter order. The stop band of the ADS1174/78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to f

MOD

Placing an antialiasing, low-pass filter in front of the ADS1174/78 inputs is recommended to limit possible high-amplitude, out-of-band signals and noise.

Table 2. Antialiasing Filter Order Image Rejection

ANTIALIASING FILTER IMAGE REJECTION (dB)

ORDER (f

1 39 2 75 3 111

Product Folder Link(s): ADS1174 ADS1178

at f

– 3dB

)

DATA

+ 24 hidden pages

TEXAS INSTRUMENTS ADS1174, ADS1178 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual