TEXAS INSTRUMENTS ADS1146, ADS1147, ADS1148 Technical data

ADS1146

ADS1147

ADS1148

Input

Mux

3rdOrder

DS

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0
AIN1

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

Input

Mux

3rdOrder

DS

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC
AIN1/IEXC

AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

V

BIAS

GPIO

CLK

ADS1148 Only

ADS1147
ADS1148

PGA

System
Monitor

Adjustable

Digital

Filter

Dual
Current
DACs

VREFMux

ADS1148 Only

V

BIAS

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ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

16-Bit Analog-to-Digital Converters for Temperature Sensors

Check for Samples: ADS1146, ADS1147, ADS1148

1

FEATURES

23

• 16 Bits, No Missing Codes

• Data Output Rates Up to 2kSPS

• Single-Cycle Settling for All Data Rates

• Simultaneous 50/60Hz Rejection at 20SPS

DESCRIPTION

The ADS1146, ADS1147, and ADS1148 are
highly-integrated, precision, 16-bit analog-to-digital
converters (ADCs). The ADS1146/7/8 feature an
onboard, low-noise, programmable gain amplifier
(PGA), a precision delta-sigma ADC with a

• 4 Differential/7 Single-Ended Inputs (ADS1148) single-cycle settling digital filter, and an internal

• 2 Differential/3 Single-Ended Inputs (ADS1147)

• Matched Current Source DACs

• Internal Voltage Reference

• Sensor Burnout Detection

• 4/8 General-Purpose I/Os (ADS1147/8)

• Internal Temperature Sensor

• Power Supply and V

Monitoring

REF

(ADS1147/8)

• Self and System Calibration

• SPI™-Compatible Serial Interface

• Analog Supply Operation:
+2.7V to +5.25V Unipolar, ±2.5V Bipolar

• Digital Supply: +2.7V to +5.25V

• Operating Temperature –40°C to +125°C

APPLICATIONS

• Temperature Measurement
– RTDs, Thermocouples, and Thermistors

• Pressure Measurement

• Industrial Process Control

oscillator. The ADS1147 and ADS1148 also provide a
built-in voltage reference with 10mA output capacity,
and two matched programmable current
digital-to-analog converters (DACs). The
ADS1146/7/8 provide a complete front-end solution
for temperature sensor applications including thermal
couples, thermistors, and resistance temperature
detectors (RTDs).

An input multiplexer supports four differential inputs
for the ADS1148, two for the ADS1147, and one for
the ADS1146. In addition, the multiplexer has a
sensor burnout detect, voltage bias for
thermocouples, system monitoring, and
general-purpose digital I/Os (ADS1147 and
ADS1148). The onboard, low-noise PGA provides
selectable gains of 1 to 128. The delta-sigma
modulator and adjustable digital filter settle in only
one cycle, for fast channel cycling when using the
input multiplexer, and support data rates up to
2kSPS. For data rates of 20SPS or less, both 50Hz
and 60Hz interference are rejected by the filter.

The ADS1146 is offered in a small TSSOP-16
package, the ADS1147 is available in a TSSOP-20
package, and the ADS1148 in a TSSOP-28 package.
All three devices operate over the extended specified
temperature range of –40°C to +105°C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc.
3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009–2010, Texas Instruments Incorporated

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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PACKAGE/ORDERING INFORMATION

PRODUCT RESOLUTION INPUTS REFERENCE SOURCES LEAD

ADS1246 24 bits or External NO TSSOP-16

ADS1247 24 bits or Internal or External YES TSSOP-20

ADS1248 24 bits or Internal or External YES TSSOP-28

ADS1146 16 bits or External NO TSSOP-16

ADS1147 16 bits or Internal or External YES TSSOP-20

ADS1148 16 bits or Internal or External YES TSSOP-28

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

NUMBER OF VOLTAGE CURRENT PACKAGE-

1 Differential

1 Single-Ended

2 Differential

3 Single-Ended

4 Differential

7 Single-Ended

1 Differential

1 Single-Ended

2 Differential

3 Single-Ended

4 Differential

7 Single-Ended

(1)

DUAL SENSOR

EXCITATION

Over operating free-air temperature range, unless otherwise noted.

ADS1146, ADS1147, ADS1148 UNIT

AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +5.5 V

Input current

Analog input voltage to AVSS AVSS – 0.3 to AVDD + 0.3 V
Digital input voltage to DGND –0.3 to DVDD + 0.3 V
Maximum junction temperature +150 °C
Operating temperature range –40 to +125 °C
Storage temperature range –60 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

100, momentary mA

10, continuous mA

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ADS1146
ADS1147
ADS1148

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THERMAL INFORMATION

THERMAL METRIC

q

JA

q

JC(top)

q

JB

y

JT

y

JB

q

JC(bottom)

Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1146,
ADS1147,

ADS1148

UNITS

PW

28

79.5

31.8

40.9

3.0

°C/W

41.1
n/a

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(V )(Gain)

IN

2

AVSS 0.1V+ +

AVDD 0.1V- -

(V )(Gain)

IN

2

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at
AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, V
noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage
(VIN= ADCINP – ADCINN)

Common-mode input range V
Differential input current 100 pA

PGA gain settings
Burnout current source 0.5, 2, or 10 mA

Bias voltage (AVDD + AVSS)/2 V
Bias voltage output impedance 400 Ω

Mux leakage current

SYSTEM PERFORMANCE

Resolution No missing codes 16 Bits

Data rate 160, 320, 640, SPS

Integral nonlinearity (INL) Differential input, end point fit, PGA = 1 ±0.5 ±1 LSB
Offset error After calibration 1 LSB

Offset drift

Gain error Excluding V

Gain drift

ADC conversion time Single-cycle settling See Table 15
Noise See Table 5 and Table 6
Normal-mode rejection See Table 8

Common-mode rejection

Power-supply rejection AVDD, DVDD at dc 100 dB

VOLTAGE REFERENCE INPUT

Voltage reference input (AVDD – AVSS)
(V

= V

– V

REF

REFP

Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V
Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V
Reference input current 30 nA

ON-CHIP VOLTAGE REFERENCE

Output voltage 2.038 2.048 2.058 V
Output current
Load regulation 50 mV/mA

(2)

Drift
Startup time See Table 9 ms

) – 1

REFN

(1)

(1) Do not exceed this loading on the internal voltage reference.
(2) Specified by the combination of design and final production test.

PGA = 1 100 nV/°C
PGA = 128 15 nV/°C

errors ±0.5 %

REF

PGA = 1, excludes V
PGA = 128, excludes V

At dc, PGA = 1 90 dB
At dc, PGA = 32 100 dB

TA= –40°C to +105°C 20 50 ppm/°C

REF

REF

= +2.048V, and oscillator frequency = 4.096MHz, unless otherwise

REF

ADS1146, ADS1147, ADS1148

±V

/PGA 2.7/PGA V

REF

1, 2, 4, 8, 16, 32,

64, 128

5, 10, 20, 40, 80,

1000, 2000

drift 1 ppm/°C

drift –3.5 ppm/°C

0.5 V

±10 mA

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pA
pA

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ADS1146
ADS1147
ADS1148

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ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All
specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, V

4.096MHz, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

CURRENT SOURCES (IDACS)

Output current 500, 750, 1000, mA

Voltage compliance All currents AVDD – 0.7 V
Initial error All currents, each IDAC –6 ±1.0 6 % of FS
Initial mismatch All currents, between IDACs ±0.03 %of FS
Temperature drift Each IDAC 200 ppm/°C
Temperature drift matching Between IDACs 10 ppm/°C

SYSTEM MONITORS

Temperature
sensor reading

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

Logic levels

DIGITAL INPUT/OUTPUT (other than GPIO)

Logic levels

Input leakage DGND < V
Clock input

(CLK)
Internal oscillator frequency 3.89 4.096 4.3 MHz

POWER SUPPLY

DVDD 2.7 5.25 V
AVSS –2.5 0 V
AVDD AVSS + 2.7 AVSS + 5.25 V

DVDD current Normal mode, DVDD = 3.3V,

AVDD current

Power dissipation

TEMPERATURE RANGE

Specified –40 +105 °C
Operating –40 +125 °C
Storage –60 +150 °C

Voltage TA= +25°C 118 mV
Drift 405 mV/°C

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

V

OH

V

OL

Frequency 1 4.5 MHz
Duty cycle 25 75 %

IOH= 1mA 0.8AVDD V
IOL= 1mA AVSS 0.2 AVDD V

IOH= 1mA 0.8DVDD V
IOL= 1mA DGND 0.2 DVDD V

< DVDD ±10 mA

DIGITAL IN

Normal mode, DVDD = 5V,
data rate = 20SPS, internal oscillator

data rate = 20SPS, internal oscillator
Sleep mode 0.2 µA
Converting, AVDD = 5V,

data rate = 20SPS, external reference
Converting, AVDD = 3.3V,

data rate = 20SPS, external reference
Sleep mode 0.1 µA
Additional current with internal reference

enabled
AVDD = DVDD = 5V, data rate = 20SPS,

external reference, internal oscillator
AVDD = DVDD = 3.3V, data rate = 20SPS,

external reference, internal oscillator

REF

ADS1146, ADS1147, ADS1148

0.7AVDD AVDD V
AVSS 0.3AVDD V

0.7DVDD DVDD V

DGND 0.3DVDD V

SBAS453C –JULY 2009–REVISED APRIL 2010

= +2.048V, and oscillator frequency =

50, 100, 250,

1500

230 mA

210 mA

225 µA

212 µA

180 mA

2.3 mW

1.4 mW

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DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

REFP1

REFN1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

IEXC1

IEXC2

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

AIN7/IEXC/GPIO7

AIN6/IEXC/GPIO6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS1148

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

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PIN CONFIGURATIONS

PW PACKAGE

TSSOP-28

(TOP VIEW)

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SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1148 (TSSOP-28) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.

REFP0/GPIO0 5

REFN0/GPIO1 6
REFP1 7 Analog input Positive external reference 1 input

REFN1 8 Analog input Negative external reference 1 input
VREFOUT 9 Analog output Positive internal reference voltage output

VREFCOM 10 Analog output
AIN0/IEXC 11 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 12 Analog input Analog input 1, optional excitation current output
AIN4/IEXC/GPIO4 13

AIN5/IEXC/GPIO5 14

AIN6/IEXC/GPIO6 15

AIN7/IEXC/GPIO7 16

AIN2/IEXC/GPIO2 17

AIN3/IEXC/GPIO3 18
IEXC2 19 Analog output Excitation current output 2

IEXC1 20 Analog output Excitation current output 1
AVSS 21 Analog Negative analog power supply
AVDD 22 Analog Positive analog power supply
START 23 Digital input Conversion start. See text for complete description.
CS 24 Digital input Chip select (active low)
DRDY 25 Digital output Data ready (active low)

DOUT/DRDY 26 Digital output
DIN 27 Digital input Serial data input

SCLK 28 Digital input Serial clock input

Analog input Positive external reference input 0, or
Digital in/out general-purpose digital input/output pin 0

Analog input Negative external reference 0 input, or
Digital in/out general-purpose digital input/output pin 1

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.

Analog input Analog input 4, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 4

Analog input Analog input 5, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 5

Analog input Analog input 6, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 6

Analog input Analog input 7, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 7

Analog input Analog input 2, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 2

Analog input Analog input 3, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 3

Serial data out output, or
data out combined with data ready (active low when DRDY function enabled)

ADS1146
ADS1147
ADS1148

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DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

ADS1147

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

PW PACKAGE

TSSOP-20

(TOP VIEW)

ADS1147 (TSSOP-20) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.

REFP0/GPIO0 5

REFN0/GPIO1 6
VREFOUT 7 Analog output Positive internal reference voltage output
VREFCOM 8 Analog output
AIN0/IEXC 9 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 10 Analog input Analog input 1, optional excitation current output
AIN2/IEXC/GPIO2 11

AIN3/IEXC/GPIO3 12
AVSS 13 Analog Negative analog power supply

AVDD 14 Analog Positive analog power supply
START 15 Digital input Conversion start. See text for description of use.
CS 16 Digital input Chip select (active low)
DRDY 17 Digital output Data ready (active low)

DOUT/DRDY 18 Digital output
DIN 19 Digital input Serial data input

SCLK 20 Digital input Serial clock input

Analog input Positive external reference input, or
Digital in/out general-purpose digital input/output pin 0

Analog input Negative external reference input, or
Digital in/out general-purpose digital input/output pin 1

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.

Analog input Analog input 2, optional excitation current output, or
Digital in/out general-purpose digital input/output pin 2

Analog input Analog input 3, with or without excitation current output, or
Digital in/out general-purpose digital input/output pin 3

Serial data out output, or
data out combined with data ready (active low when DRDY function enabled)

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DVDD

DGND

CLK

RESET

REFP

REFN

AINP

AINN

SCLK

DIN

DOUT/DRDY

DRDY

CS

START

AVDD

AVSS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADS1146

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SBAS453C –JULY 2009–REVISED APRIL 2010

PW PACKAGE

TSSOP-16

(TOP VIEW)

ADS1146 (TSSOP-16) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
REFP 5 Analog input Positive external reference input
REFN 6 Analog input Negative external reference input
AINP 7 Analog input Positive analog input
AINN 8 Analog input Negative analog input
AVSS 9 Analog Negative analog power supply
AVDD 10 Analog Positive analog power supply
START 11 Digital input Conversion start. See text for description of use.
CS 12 Digital input Chip select (active low)
DRDY 13 Digital output Data ready (active low)

DOUT/DRDY 14 Digital output
DIN 15 Digital input Serial data input

SCLK 16 Digital input Serial clock input

Serial data out output, or
data out combined with data ready (active low when DRDY function enabled)

ADS1146
ADS1147
ADS1148

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SCLK

DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]

DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]

CS

DOUT/

(1)

DRDY

DIN

t

CSSC

t

DIST

t

DIHD

t

SCLK

t

SCCS

t

CSDO

t

DOPD

t

SPWL

t

SPWH

t

DOHD

SCLK

(3)

1 2 3 87654

DRDY

t

STD

t

DTS

t

PWH

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

TIMING DIAGRAMS

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Figure 1. Serial Interface Timing

Table 1. Timing Characteristics for Figure 1

(1)

SYMBOL DESCRIPTION MIN MAX UNIT

t

CSSC

t

SCCS

t

DIST

t

DIHD

t

DOPD

t

DOHD

t

SCLK

t

SPWH

t

SPWL

t

CSDO

CS low to first SCLK high (set up time) 10 ns
SCLK low to CS high (hold time) 7 t
DIN set up time 5 ns
DIN hold time 5 ns
SCLK rising edge to new data valid 30 ns
DOUT hold time 0 ns

SCLK period

500 ns

64 conversions
SCLK pulse width high 0.25 0.75 t
SCLK pulse width low 0.25 0.75 t
CS high to DOUT high impedance 10 ns

(1) DRDY MODE bit = 0.
(2) t

OSC

= 1/f

. The default clock frequency f

CLK

= 4.096MHz.

CLK

OSC

SCLK
SCLK

(2)

t

PWH

t

S TD

t

DTS

(3) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during t
(4) SCLK should only be sent in multiples of eight during partial retrieval of output data.

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Figure 2. SPI Interface Timing to Allow Conversion Result Loading

(3) (4)

Table 2. Timing Characteristics for Figure 2

SYMBOL DESCRIPTION MIN MAX UNIT

DRDY pulse width high 3 t
SCLK low prior to DRDY low 5 t
DRDY falling edge to SCLK rising edge 30 ns

Product Folder Link(s): ADS1146 ADS1147 ADS1148

STD

when CS is high.

OSC
OSC

t

START

START

SCLK

CS

RESET

t

RESET

t

RHSC

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SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 3. Minimum START Pulse Width

Table 3. Timing Characteristics for Figure 3

SYMBOL DESCRIPTION MIN MAX UNIT

t

START

START pulse width high 3 t

Figure 4. Reset Pulse Width and SPI Communication After Reset

ADS1146
ADS1147
ADS1148

OSC

Table 4. Timing Characteristics for Figure 4

SYMBOL DESCRIPTION MIN MAX UNIT

t

RESET

t

RHSC

(1) For f

= 4.096MHz, scales proportionately with f

OSC

RESET pulse width low 4 t
RESET high to SPI communication start 0.6

frequency.

OSC

(1)

OSC

ms

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ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

NOISE PERFORMANCE

The ADS1146/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the
averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value
reduces the input-referred noise, particularly useful when measuring low-level signals. Table 5 and Table 6
summarize noise performance of the ADS1146/7/8. The data are representative of typical noise performance at
T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured
with the inputs shorted together.

Table 5 lists the input-referred noise in units mVPP. In many of the settings, especially at lower data rates, the

inherent device noise is less than 1LSB. For these cases, the noise is rounded up to 1LSB. Table 6 lists the
corresponding data in units of ENOB (effective number of bits) where:

ENOB = ln(Full-Scale Range/Noise)/ln(2) (1)

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DATA RATE

At V

Table 5. Noise in mV

= 2.048V, AVDD = 5V, and AVSS = 0V

REF

PGA SETTING

PP

(SPS) 1 2 4 8 16 32 64 128

5 62.50
10 62.50
20 62.50
40 62.50
80 62.50

160 62.50
320 62.50

(1)
(1)
(1)
(1)
(1)
(1)
(1)

31.25

31.25

31.25

31.25

31.25

31.25

(1)
(1)
(1)
(1)
(1)
(1)

15.63

15.63

15.63

15.63

15.63

15.63

(1)
(1)
(1)
(1)
(1)
(1)

7.81

7.81

7.81

7.81

7.81

7.81

(1)
(1)
(1)
(1)
(1)
(1)

3.91

3.91

3.91

3.91

3.91

3.91

(1)
(1)
(1)
(1)
(1)
(1)

1.95

1.95

1.95

1.95

1.95

1.95

(1)
(1)
(1)
(1)
(1)
(1)

(1)

0.98

(1)

0.98

(1)

0.98

(1)

0.98

1.09 0.98

1.88 1.57

35.30 17.52 8.86 4.35 3.03 2.44 2.34

640 93.06 45.20 18.73 12.97 6.51 4.20 3.69 3.50
1000 284.59 129.77 61.30 33.04 16.82 9.08 5.42 4.65
2000 273.39 130.68 67.13 36.16 19.22 9.87 6.93 6.48

(1) Peak-to-peak noise rounded up to 1LSB.

Table 6. Effective Number of Bits From Peak-to-Peak Noise

At V

DATA RATE

(SPS) 1 2 4 8 16 32 64 128

5 16 16 16 16 16 16 16 16
10 16 16 16 16 16 16 16 16
20 16 16 16 16 16 16 16 15.8
40 16 16 16 16 16 16 16 15.4
80 16 16 16 16 16 16 15.8 15.0

160 16 16 16 16 16 16 15.1 14.3
320 16 15.8 15.8 15.8 15.8 15.4 14.7 13.7

640 15.4 15.5 15.7 15.3 15.3 14.9 14.1 13.2
1000 13.8 13.9 14.0 13.9 13.9 13.8 13.5 12.7
2000 13.9 13.9 13.9 13.8 13.7 13.7 13.2 12.3

= 2.048V, AVDD = 5V, and AVSS = 0V

REF

PGA SETTING

0.49

0.49

0.55

0.75

(1)
(1)

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800

700

600

500

400

300

200

100

0

Temperature( C)°

AnalogCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

330

310

290

270

250

230

210

190

Temperature( C)°

DigitalCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

DVDD=5V

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991

AVDD(V)

NormalizedOutputCurrent

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

750 Am

250 Am

1.5mA

500 Am

100 Am

1mA

50 Am

IDACCurrentSettings

0.004

0.003

0.002

0.001

0

-0.001

-0.002

-0.003

-0.004

Temperature( C)°

IEXC1 IEXC2(- mA)

-40 -20 0 20 40 60 80 100 120

1.5mASetting,10Units

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At TA= +25°C, AVDD = 5V, V

ANALOG CURRENT DIGITAL CURRENT

SBAS453C –JULY 2009–REVISED APRIL 2010

TYPICAL CHARACTERISTICS

= 2.5V, and AVSS = 0V, unless otherwise noted.

REF

vs TEMPERATURE vs TEMPERATURE

Figure 5. Figure 6.

ADS1146
ADS1147
ADS1148

IDAC LINE REGULATION IDAC DRIFT

Figure 7. Figure 8.

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Input

Mux

3rdOrder

DS

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0
AIN1

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

V

BIAS

Input

Mux

3rdOrder

DS

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC
AIN1/IEXC

AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

CS

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

V

BIAS

GPIO

CLK

ADS1148 Only

ADS1147
ADS1148

PGA

System
Monitor

Adjustable

Digital

Filter

Dual
Current
DACs

VREFMux

ADS1148 Only

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

GENERAL DESCRIPTION

OVERVIEW

The ADS1146, ADS1147 and ADS1148 are highly input multiplexer with system monitoring capability
integrated 24-bit data converters. Each device and general-purpose I/O settings, a very low-drift
includes a low-noise, high-impedance programmable voltage reference, and two matched current sources
gain amplifier (PGA), a delta-sigma (ΔΣ) ADC with an for sensor excitation. Figure 9 and Figure 10 show
adjustable single-cycle settling digital filter, internal the various functions incorporated into each device.
oscillator, and a simple but flexible SPI-compatible
serial interface.

The ADS1147 and ADS1148 also include a flexible

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Figure 9. ADS1146 Diagram

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Figure 10. ADS1147, ADS1148 Diagram

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SystemMonitors

Temperature
Diode

VREFP

VREFN

VREFP1/4

VREFN1/4

VREFP0/4

VREFN0/4

AVDD/4

AVSS/4

DVDD/4

DGND/4

ADS1148Only

ADS1147/8Only

VBIAS

AIN0

AIN1

VBIAS

AIN2

VBIAS

AIN3

VBIAS

AIN4

VBIAS

AIN5

VBIAS

AIN6

VBIAS

AIN7

AVDD

IDAC1

IDAC2

AVDD

VBIAS

PGA

AIN

P

AVSS

AVDD

BurnoutCurrentSource
(0.5 A,2 A,10m m mA)

BurnoutCurrentSource
(0.5 A,2 A,10m m mA)

AIN

N

To
ADC

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD AVDD

ADS1146
ADS1147
ADS1148

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ADC INPUT AND MULTIPLEXER Any analog input pin can be selected as the positive

The ADS1146/7/8 ADC measures the input signal
through the onboard PGA. All analog inputs are
connected to the internal AINPor AINNanalog inputs
through the analog multiplexer. A block diagram of
the analog input multiplexer is shown in Figure 11.

The input multiplexer connects to eight (ADS1148),
four (ADS1147), or two (ADS1146) analog inputs that
can be configured as single-ended inputs, differential
inputs, or in a combination of single-ended and
differential inputs. The multiplexer also allows the
on-chip excitation current and/or bias voltage to be On the ADS1147 and ADS1148, the analog inputs
selected to a specific channel. can also be configured as general-purpose

input or negative input through the MUX0 register.
The ADS1146/7/8 have a true fully differential mode,
meaning that the input signal range can be from
–2.5V to +2.5V (when AVDD = 2.5V and AVSS =
–2.5V).

Through the input multiplexer, the ambient
temperature (internal temperature sensor), AVDD,
DVDD, and external reference can all be selected for
measurement. Refer to the System Monitor section
for details.

inputs/outputs (GPIOs). See the General-Purpose

Digital I/O section for more details.

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 11. Analog Input Multiplexer Circuit

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REFN1REFP1

ADC

ADS1148 Only

REFN0REFP0

V

REFN

V

REFP

VREFCOMVREFOUT

ReferenceMultiplexer

Internal
Voltage

Reference

ADS1146
ADS1147
ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ESD diodes protect the ADC inputs. To prevent these As with the analog inputs, REFP0 and REFN0 can be
diodes from turning on, make sure the voltages on configured as digital I/Os on the ADS1147 and
the input pins do not go below AVSS by more than ADS1148.
100mV, and do not exceed AVDD by more than
100mV, as shown in Equation 2. Note that the same
caution is true if the inputs are configured to be
GPIOs.

AVSS – 100mV < (AINX) < AVDD + 100mV (2)

Settling Time for Channel Multiplexing

The ADS1146/7/8 is a true single-cycle settling ΔΣ
converter. The first data available after the start of a
conversion are fully settled and valid for use. The
time required to settle is roughly equal to the inverse
of the data rate. The exact time depends on the
specific data rate and the operation that resulted in
the start of a conversion; see Table 15 for specific
values.

Figure 12. Reference Input Multiplexer

VOLTAGE REFERENCE INPUT

The voltage reference for the ADS1146/7/8 is the
differential voltage between REFP and REFN:

V

REF

= V

REFP

– V

REFN

In the case of the ADS1146, these pins are dedicated
inputs. For the ADS1147 and ADS1148, there is a
multiplexer that selects the reference inputs, as
shown in Figure 12. The reference input uses a buffer
to increase the input impedance.

The reference input circuit has ESD diodes to protect
the inputs. To prevent the diodes from turning on,
make sure the voltage on the reference input pin is
not less than AVSS – 100mV, and does not exceed
AVDD + 100mV, as shown in Equation 3:

AVSS – 100mV < (V

REFP

or V

) < AVDD + 100mV (3)

REFN

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