TEXAS INSTRUMENTS ADS1146, ADS1147, ADS1148 Technical data

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ADS1146

ADS1147

ADS1148

Input

Mux

3rdOrder

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0 AIN1

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

Input

Mux

3rdOrder

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC AIN1/IEXC

AIN2/IEXC/GPIO2 AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4 AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6 AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

BIAS

GPIO

CLK

ADS1148 Only

ADS1147 ADS1148

PGA

System Monitor

Adjustable

Digital

Filter

Dual Current DACs

VREFMux

ADS1148 Only

BIAS

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ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

16-Bit Analog-to-Digital Converters for Temperature Sensors

Check for Samples: ADS1146, ADS1147, ADS1148

FEATURES

• 16 Bits, No Missing Codes

• Data Output Rates Up to 2kSPS

• Single-Cycle Settling for All Data Rates

• Simultaneous 50/60Hz Rejection at 20SPS

DESCRIPTION

The ADS1146, ADS1147, and ADS1148 are highly-integrated, precision, 16-bit analog-to-digital converters (ADCs). The ADS1146/7/8 feature an onboard, low-noise, programmable gain amplifier (PGA), a precision delta-sigma ADC with a

• 4 Differential/7 Single-Ended Inputs (ADS1148) single-cycle settling digital filter, and an internal

• 2 Differential/3 Single-Ended Inputs (ADS1147)

• Matched Current Source DACs

• Internal Voltage Reference

• Sensor Burnout Detection

• 4/8 General-Purpose I/Os (ADS1147/8)

• Internal Temperature Sensor

• Power Supply and V

Monitoring

REF

(ADS1147/8)

• Self and System Calibration

• SPI™-Compatible Serial Interface

• Analog Supply Operation: +2.7V to +5.25V Unipolar, ±2.5V Bipolar

• Digital Supply: +2.7V to +5.25V

• Operating Temperature –40°C to +125°C

APPLICATIONS

• Temperature Measurement – RTDs, Thermocouples, and Thermistors

• Pressure Measurement

• Industrial Process Control

oscillator. The ADS1147 and ADS1148 also provide a built-in voltage reference with 10mA output capacity, and two matched programmable current digital-to-analog converters (DACs). The ADS1146/7/8 provide a complete front-end solution for temperature sensor applications including thermal couples, thermistors, and resistance temperature detectors (RTDs).

An input multiplexer supports four differential inputs for the ADS1148, two for the ADS1147, and one for the ADS1146. In addition, the multiplexer has a sensor burnout detect, voltage bias for thermocouples, system monitoring, and general-purpose digital I/Os (ADS1147 and ADS1148). The onboard, low-noise PGA provides selectable gains of 1 to 128. The delta-sigma modulator and adjustable digital filter settle in only one cycle, for fast channel cycling when using the input multiplexer, and support data rates up to 2kSPS. For data rates of 20SPS or less, both 50Hz and 60Hz interference are rejected by the filter.

The ADS1146 is offered in a small TSSOP-16 package, the ADS1147 is available in a TSSOP-20 package, and the ADS1148 in a TSSOP-28 package. All three devices operate over the extended specified temperature range of –40°C to +105°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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PACKAGE/ORDERING INFORMATION

PRODUCT RESOLUTION INPUTS REFERENCE SOURCES LEAD

ADS1246 24 bits or External NO TSSOP-16

ADS1247 24 bits or Internal or External YES TSSOP-20

ADS1248 24 bits or Internal or External YES TSSOP-28

ADS1146 16 bits or External NO TSSOP-16

ADS1147 16 bits or Internal or External YES TSSOP-20

ADS1148 16 bits or Internal or External YES TSSOP-28

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

NUMBER OF VOLTAGE CURRENT PACKAGE-

1 Differential

1 Single-Ended

2 Differential

3 Single-Ended

4 Differential

7 Single-Ended

1 Differential

1 Single-Ended

2 Differential

3 Single-Ended

4 Differential

7 Single-Ended

(1)

DUAL SENSOR

EXCITATION

Over operating free-air temperature range, unless otherwise noted.

ADS1146, ADS1147, ADS1148 UNIT

AVDD to AVSS –0.3 to +5.5 V AVSS to DGND –2.8 to +0.3 V DVDD to DGND –0.3 to +5.5 V

Input current

Analog input voltage to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V Maximum junction temperature +150 °C Operating temperature range –40 to +125 °C Storage temperature range –60 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

100, momentary mA

10, continuous mA

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146 ADS1147 ADS1148

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THERMAL INFORMATION

THERMAL METRIC

JC(top)

JC(bottom)

Junction-to-ambient thermal resistance Junction-to-case(top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case(bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1146, ADS1147,

ADS1148

UNITS

79.5

31.8

40.9

3.0

°C/W

41.1 n/a

Product Folder Link(s): ADS1146 ADS1147 ADS1148

(V )(Gain)

AVSS 0.1V+ +

AVDD 0.1V- -

(V )(Gain)

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, V noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage (VIN= ADCINP – ADCINN)

Common-mode input range V Differential input current 100 pA

PGA gain settings Burnout current source 0.5, 2, or 10 mA

Bias voltage (AVDD + AVSS)/2 V Bias voltage output impedance 400 Ω

Mux leakage current

SYSTEM PERFORMANCE

Resolution No missing codes 16 Bits

Data rate 160, 320, 640, SPS

Integral nonlinearity (INL) Differential input, end point fit, PGA = 1 ±0.5 ±1 LSB Offset error After calibration 1 LSB

Offset drift

Gain error Excluding V

Gain drift

ADC conversion time Single-cycle settling See Table 15 Noise See Table 5 and Table 6 Normal-mode rejection See Table 8

Common-mode rejection

Power-supply rejection AVDD, DVDD at dc 100 dB

VOLTAGE REFERENCE INPUT

Voltage reference input (AVDD – AVSS) (V

= V

– V

REF

REFP

Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V Reference input current 30 nA

ON-CHIP VOLTAGE REFERENCE

Output voltage 2.038 2.048 2.058 V Output current Load regulation 50 mV/mA

(2)

Drift Startup time See Table 9 ms

) – 1

REFN

(1)

(1) Do not exceed this loading on the internal voltage reference. (2) Specified by the combination of design and final production test.

PGA = 1 100 nV/°C PGA = 128 15 nV/°C

errors ±0.5 %

REF

PGA = 1, excludes V PGA = 128, excludes V

At dc, PGA = 1 90 dB At dc, PGA = 32 100 dB

TA= –40°C to +105°C 20 50 ppm/°C

REF

= +2.048V, and oscillator frequency = 4.096MHz, unless otherwise

REF

ADS1146, ADS1147, ADS1148

±V

/PGA 2.7/PGA V

REF

1, 2, 4, 8, 16, 32,

64, 128

5, 10, 20, 40, 80,

1000, 2000

drift 1 ppm/°C

drift –3.5 ppm/°C

0.5 V

±10 mA

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pA pA

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146 ADS1147 ADS1148

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ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, V

4.096MHz, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

CURRENT SOURCES (IDACS)

Output current 500, 750, 1000, mA

Voltage compliance All currents AVDD – 0.7 V Initial error All currents, each IDAC –6 ±1.0 6 % of FS Initial mismatch All currents, between IDACs ±0.03 %of FS Temperature drift Each IDAC 200 ppm/°C Temperature drift matching Between IDACs 10 ppm/°C

SYSTEM MONITORS

Temperature sensor reading

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

Logic levels

DIGITAL INPUT/OUTPUT (other than GPIO)

Logic levels

Input leakage DGND < V Clock input

(CLK) Internal oscillator frequency 3.89 4.096 4.3 MHz

POWER SUPPLY

DVDD 2.7 5.25 V AVSS –2.5 0 V AVDD AVSS + 2.7 AVSS + 5.25 V

DVDD current Normal mode, DVDD = 3.3V,

AVDD current

Power dissipation

TEMPERATURE RANGE

Specified –40 +105 °C Operating –40 +125 °C Storage –60 +150 °C

Voltage TA= +25°C 118 mV Drift 405 mV/°C

Frequency 1 4.5 MHz Duty cycle 25 75 %

IOH= 1mA 0.8AVDD V IOL= 1mA AVSS 0.2 AVDD V

IOH= 1mA 0.8DVDD V IOL= 1mA DGND 0.2 DVDD V

< DVDD ±10 mA

DIGITAL IN

Normal mode, DVDD = 5V, data rate = 20SPS, internal oscillator

data rate = 20SPS, internal oscillator Sleep mode 0.2 µA Converting, AVDD = 5V,

data rate = 20SPS, external reference Converting, AVDD = 3.3V,

data rate = 20SPS, external reference Sleep mode 0.1 µA Additional current with internal reference

enabled AVDD = DVDD = 5V, data rate = 20SPS,

external reference, internal oscillator AVDD = DVDD = 3.3V, data rate = 20SPS,

external reference, internal oscillator

REF

ADS1146, ADS1147, ADS1148

0.7AVDD AVDD V AVSS 0.3AVDD V

0.7DVDD DVDD V

DGND 0.3DVDD V

SBAS453C –JULY 2009–REVISED APRIL 2010

= +2.048V, and oscillator frequency =

50, 100, 250,

1500

230 mA

210 mA

225 µA

212 µA

180 mA

2.3 mW

1.4 mW

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

REFP1

REFN1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

IEXC1

IEXC2

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

AIN7/IEXC/GPIO7

AIN6/IEXC/GPIO6

ADS1148

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

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PIN CONFIGURATIONS

PW PACKAGE

TSSOP-28

(TOP VIEW)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

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SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1148 (TSSOP-28) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

REFP0/GPIO0 5

REFN0/GPIO1 6 REFP1 7 Analog input Positive external reference 1 input

REFN1 8 Analog input Negative external reference 1 input VREFOUT 9 Analog output Positive internal reference voltage output

VREFCOM 10 Analog output AIN0/IEXC 11 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 12 Analog input Analog input 1, optional excitation current output AIN4/IEXC/GPIO4 13

AIN5/IEXC/GPIO5 14

AIN6/IEXC/GPIO6 15

AIN7/IEXC/GPIO7 16

AIN2/IEXC/GPIO2 17

AIN3/IEXC/GPIO3 18 IEXC2 19 Analog output Excitation current output 2

IEXC1 20 Analog output Excitation current output 1 AVSS 21 Analog Negative analog power supply AVDD 22 Analog Positive analog power supply START 23 Digital input Conversion start. See text for complete description. CS 24 Digital input Chip select (active low) DRDY 25 Digital output Data ready (active low)

DOUT/DRDY 26 Digital output DIN 27 Digital input Serial data input

SCLK 28 Digital input Serial clock input

Analog input Positive external reference input 0, or Digital in/out general-purpose digital input/output pin 0

Analog input Negative external reference 0 input, or Digital in/out general-purpose digital input/output pin 1

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar supply, or to the midvoltage of the power supply when using a bipolar supply.

Analog input Analog input 4, optional excitation current output, or Digital in/out general-purpose digital input/output pin 4

Analog input Analog input 5, optional excitation current output, or Digital in/out general-purpose digital input/output pin 5

Analog input Analog input 6, optional excitation current output, or Digital in/out general-purpose digital input/output pin 6

Analog input Analog input 7, optional excitation current output, or Digital in/out general-purpose digital input/output pin 7

Analog input Analog input 2, optional excitation current output, or Digital in/out general-purpose digital input/output pin 2

Analog input Analog input 3, optional excitation current output, or Digital in/out general-purpose digital input/output pin 3

Serial data out output, or data out combined with data ready (active low when DRDY function enabled)

ADS1146 ADS1147 ADS1148

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

ADS1147

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

PW PACKAGE

TSSOP-20

(TOP VIEW)

ADS1147 (TSSOP-20) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

REFP0/GPIO0 5

REFN0/GPIO1 6 VREFOUT 7 Analog output Positive internal reference voltage output VREFCOM 8 Analog output AIN0/IEXC 9 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 10 Analog input Analog input 1, optional excitation current output AIN2/IEXC/GPIO2 11

AIN3/IEXC/GPIO3 12 AVSS 13 Analog Negative analog power supply

AVDD 14 Analog Positive analog power supply START 15 Digital input Conversion start. See text for description of use. CS 16 Digital input Chip select (active low) DRDY 17 Digital output Data ready (active low)

DOUT/DRDY 18 Digital output DIN 19 Digital input Serial data input

SCLK 20 Digital input Serial clock input

Analog input Positive external reference input, or Digital in/out general-purpose digital input/output pin 0

Analog input Negative external reference input, or Digital in/out general-purpose digital input/output pin 1

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar supply, or to the midvoltage of the power supply when using a bipolar supply.

Analog input Analog input 2, optional excitation current output, or Digital in/out general-purpose digital input/output pin 2

Analog input Analog input 3, with or without excitation current output, or Digital in/out general-purpose digital input/output pin 3

Serial data out output, or data out combined with data ready (active low when DRDY function enabled)

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Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP

REFN

AINP

AINN

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

ADS1146

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SBAS453C –JULY 2009–REVISED APRIL 2010

PW PACKAGE

TSSOP-16

(TOP VIEW)

ADS1146 (TSSOP-16) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply DGND 2 Digital Digital ground CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator. RESET 4 Digital input Chip reset (active low). Returns all register values to reset values. REFP 5 Analog input Positive external reference input REFN 6 Analog input Negative external reference input AINP 7 Analog input Positive analog input AINN 8 Analog input Negative analog input AVSS 9 Analog Negative analog power supply AVDD 10 Analog Positive analog power supply START 11 Digital input Conversion start. See text for description of use. CS 12 Digital input Chip select (active low) DRDY 13 Digital output Data ready (active low)

DOUT/DRDY 14 Digital output DIN 15 Digital input Serial data input

SCLK 16 Digital input Serial clock input

Serial data out output, or data out combined with data ready (active low when DRDY function enabled)

ADS1146 ADS1147 ADS1148

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SCLK

DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]

DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]

DOUT/

(1)

DRDY

DIN

CSSC

DIST

DIHD

SCLK

SCCS

CSDO

DOPD

SPWL

SPWH

DOHD

SCLK

(3)

1 2 3 87654

DRDY

STD

DTS

PWH

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

TIMING DIAGRAMS

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Figure 1. Serial Interface Timing

Table 1. Timing Characteristics for Figure 1

(1)

SYMBOL DESCRIPTION MIN MAX UNIT

CSSC

SCCS

DIST

DIHD

DOPD

DOHD

SCLK

SPWH

SPWL

CSDO

CS low to first SCLK high (set up time) 10 ns SCLK low to CS high (hold time) 7 t DIN set up time 5 ns DIN hold time 5 ns SCLK rising edge to new data valid 30 ns DOUT hold time 0 ns

SCLK period

500 ns

64 conversions SCLK pulse width high 0.25 0.75 t SCLK pulse width low 0.25 0.75 t CS high to DOUT high impedance 10 ns

(1) DRDY MODE bit = 0. (2) t

OSC

= 1/f

. The default clock frequency f

CLK

= 4.096MHz.

CLK

OSC

SCLK SCLK

(2)

PWH

S TD

DTS

(3) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during t (4) SCLK should only be sent in multiples of eight during partial retrieval of output data.

Figure 2. SPI Interface Timing to Allow Conversion Result Loading

(3) (4)

Table 2. Timing Characteristics for Figure 2

SYMBOL DESCRIPTION MIN MAX UNIT

DRDY pulse width high 3 t SCLK low prior to DRDY low 5 t DRDY falling edge to SCLK rising edge 30 ns

Product Folder Link(s): ADS1146 ADS1147 ADS1148

STD

when CS is high.

OSC OSC

START

SCLK

RESET

RHSC

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SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 3. Minimum START Pulse Width

Table 3. Timing Characteristics for Figure 3

SYMBOL DESCRIPTION MIN MAX UNIT

START

START pulse width high 3 t

Figure 4. Reset Pulse Width and SPI Communication After Reset

ADS1146 ADS1147 ADS1148

OSC

Table 4. Timing Characteristics for Figure 4

SYMBOL DESCRIPTION MIN MAX UNIT

RESET

RHSC

(1) For f

= 4.096MHz, scales proportionately with f

OSC

RESET pulse width low 4 t RESET high to SPI communication start 0.6

frequency.

OSC

(1)

OSC

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

NOISE PERFORMANCE

The ADS1146/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, particularly useful when measuring low-level signals. Table 5 and Table 6 summarize noise performance of the ADS1146/7/8. The data are representative of typical noise performance at T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured with the inputs shorted together.

Table 5 lists the input-referred noise in units mVPP. In many of the settings, especially at lower data rates, the

inherent device noise is less than 1LSB. For these cases, the noise is rounded up to 1LSB. Table 6 lists the corresponding data in units of ENOB (effective number of bits) where:

ENOB = ln(Full-Scale Range/Noise)/ln(2) (1)

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DATA RATE

At V

Table 5. Noise in mV

= 2.048V, AVDD = 5V, and AVSS = 0V

REF

PGA SETTING

(SPS) 1 2 4 8 16 32 64 128

5 62.50 10 62.50 20 62.50 40 62.50 80 62.50

160 62.50 320 62.50

(1) (1) (1) (1) (1) (1) (1)

31.25

(1) (1) (1) (1) (1) (1)

15.63

(1) (1) (1) (1) (1) (1)

7.81

(1) (1) (1) (1) (1) (1)

3.91

(1) (1) (1) (1) (1) (1)

1.95

(1) (1) (1) (1) (1) (1)

(1)

0.98

(1)

0.98

(1)

0.98

(1)

0.98

1.09 0.98

1.88 1.57

35.30 17.52 8.86 4.35 3.03 2.44 2.34

640 93.06 45.20 18.73 12.97 6.51 4.20 3.69 3.50 1000 284.59 129.77 61.30 33.04 16.82 9.08 5.42 4.65 2000 273.39 130.68 67.13 36.16 19.22 9.87 6.93 6.48

(1) Peak-to-peak noise rounded up to 1LSB.

Table 6. Effective Number of Bits From Peak-to-Peak Noise

At V

DATA RATE

(SPS) 1 2 4 8 16 32 64 128

5 16 16 16 16 16 16 16 16 10 16 16 16 16 16 16 16 16 20 16 16 16 16 16 16 16 15.8 40 16 16 16 16 16 16 16 15.4 80 16 16 16 16 16 16 15.8 15.0

160 16 16 16 16 16 16 15.1 14.3 320 16 15.8 15.8 15.8 15.8 15.4 14.7 13.7

640 15.4 15.5 15.7 15.3 15.3 14.9 14.1 13.2 1000 13.8 13.9 14.0 13.9 13.9 13.8 13.5 12.7 2000 13.9 13.9 13.9 13.8 13.7 13.7 13.2 12.3

= 2.048V, AVDD = 5V, and AVSS = 0V

REF

PGA SETTING

0.49

0.55

0.75

(1) (1)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

800

700

600

500

400

300

200

100

Temperature( C)°

AnalogCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

330

310

290

270

250

230

210

190

Temperature( C)°

DigitalCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

DVDD=5V

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991

AVDD(V)

NormalizedOutputCurrent

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

750 Am

250 Am

1.5mA

500 Am

100 Am

1mA

50 Am

IDACCurrentSettings

0.004

0.003

0.002

0.001

-0.001

-0.002

-0.003

-0.004

Temperature( C)°

IEXC1 IEXC2(- mA)

-40 -20 0 20 40 60 80 100 120

1.5mASetting,10Units

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At TA= +25°C, AVDD = 5V, V

ANALOG CURRENT DIGITAL CURRENT

SBAS453C –JULY 2009–REVISED APRIL 2010

TYPICAL CHARACTERISTICS

= 2.5V, and AVSS = 0V, unless otherwise noted.

REF

vs TEMPERATURE vs TEMPERATURE

Figure 5. Figure 6.

ADS1146 ADS1147 ADS1148

IDAC LINE REGULATION IDAC DRIFT

Figure 7. Figure 8.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

Input

Mux

3rdOrder

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0 AIN1

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

BIAS

Input

Mux

3rdOrder

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC AIN1/IEXC

AIN2/IEXC/GPIO2 AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4 AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6 AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

BIAS

GPIO

CLK

ADS1148 Only

ADS1147 ADS1148

PGA

System Monitor

Adjustable

Digital

Filter

Dual Current DACs

VREFMux

ADS1148 Only

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

GENERAL DESCRIPTION

OVERVIEW

The ADS1146, ADS1147 and ADS1148 are highly input multiplexer with system monitoring capability integrated 24-bit data converters. Each device and general-purpose I/O settings, a very low-drift includes a low-noise, high-impedance programmable voltage reference, and two matched current sources gain amplifier (PGA), a delta-sigma (ΔΣ) ADC with an for sensor excitation. Figure 9 and Figure 10 show adjustable single-cycle settling digital filter, internal the various functions incorporated into each device. oscillator, and a simple but flexible SPI-compatible serial interface.

The ADS1147 and ADS1148 also include a flexible

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Figure 9. ADS1146 Diagram

Figure 10. ADS1147, ADS1148 Diagram

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SystemMonitors

Temperature Diode

VREFP

VREFN

VREFP1/4

VREFN1/4

VREFP0/4

VREFN0/4

AVDD/4

AVSS/4

DVDD/4

DGND/4

ADS1148Only

ADS1147/8Only

VBIAS

AIN0

AIN1

VBIAS

AIN2

VBIAS

AIN3

VBIAS

AIN4

VBIAS

AIN5

VBIAS

AIN6

VBIAS

AIN7

AVDD

IDAC1

IDAC2

AVDD

VBIAS

PGA

AIN

AVSS

AVDD

BurnoutCurrentSource (0.5 A,2 A,10m m mA)

AIN

To ADC

AVSS

AVDD

AVDD AVDD

ADS1146 ADS1147 ADS1148

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ADC INPUT AND MULTIPLEXER Any analog input pin can be selected as the positive

The ADS1146/7/8 ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINPor AINNanalog inputs through the analog multiplexer. A block diagram of the analog input multiplexer is shown in Figure 11.

The input multiplexer connects to eight (ADS1148), four (ADS1147), or two (ADS1146) analog inputs that can be configured as single-ended inputs, differential inputs, or in a combination of single-ended and differential inputs. The multiplexer also allows the on-chip excitation current and/or bias voltage to be On the ADS1147 and ADS1148, the analog inputs selected to a specific channel. can also be configured as general-purpose

input or negative input through the MUX0 register. The ADS1146/7/8 have a true fully differential mode, meaning that the input signal range can be from –2.5V to +2.5V (when AVDD = 2.5V and AVSS = –2.5V).

Through the input multiplexer, the ambient temperature (internal temperature sensor), AVDD, DVDD, and external reference can all be selected for measurement. Refer to the System Monitor section for details.

inputs/outputs (GPIOs). See the General-Purpose

Digital I/O section for more details.

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 11. Analog Input Multiplexer Circuit

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REFN1REFP1

ADC

ADS1148 Only

REFN0REFP0

REFN

REFP

VREFCOMVREFOUT

ReferenceMultiplexer

Internal Voltage

Reference

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ESD diodes protect the ADC inputs. To prevent these As with the analog inputs, REFP0 and REFN0 can be diodes from turning on, make sure the voltages on configured as digital I/Os on the ADS1147 and the input pins do not go below AVSS by more than ADS1148. 100mV, and do not exceed AVDD by more than 100mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs.

AVSS – 100mV < (AINX) < AVDD + 100mV (2)

Settling Time for Channel Multiplexing

The ADS1146/7/8 is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 15 for specific values.

Figure 12. Reference Input Multiplexer

VOLTAGE REFERENCE INPUT

The voltage reference for the ADS1146/7/8 is the differential voltage between REFP and REFN:

REF

= V

REFP

– V

REFN

In the case of the ADS1146, these pins are dedicated inputs. For the ADS1147 and ADS1148, there is a multiplexer that selects the reference inputs, as shown in Figure 12. The reference input uses a buffer to increase the input impedance.

The reference input circuit has ESD diodes to protect the inputs. To prevent the diodes from turning on, make sure the voltage on the reference input pin is not less than AVSS – 100mV, and does not exceed AVDD + 100mV, as shown in Equation 3:

AVSS – 100mV < (V

REFP

or V

) < AVDD + 100mV (3)

REFN

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(V )(Gain)

AVSS+0.1V +

£ V

CMI

()

(V )(Gain)

AVDD 0.1V- -

ADC

454W

7.5pF

AIN

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LOW-NOISE PGA

The ADS1146/7/8 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, or 128 by register SYS0. A simplified diagram of the PGA is shown in Figure 13.

Figure 13. Simplified Diagram of the PGA

The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter, as shown in Figure 13. Note that as with any PGA, it is necessary to ensure that the input voltage stays within the specified common-mode input range specified in the Electrical Characteristics. The common-mode input (V range shown in Equation 4:

) must be within the

CMI

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

(4)

MODULATOR

A third-order modulator is used in the ADS1146/7/8. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. To save power, the modulator clock runs from 32kHz up to 512kHz for different data rates, as shown in Table 7.

DIGITAL FILTER

The ADS1146/7/8 use linear-phase finite impulse response (FIR) digital filters that can be adjusted for different output data rates. The digital filter always settles in a single cycle.

Table 8 shows the exact data rates when an external

oscillator equal to 4.096MHz is used. Also shown is the signal –3dB bandwidth, and the 50Hz and 60Hz attenuation. For good 50Hz or 60Hz rejection, use a data rate of 20SPS or slower.

The frequency responses of the digital filter are shown in Figure 14 to Figure 24. Figure 17 shows a detailed view of the filter frequency response from 48Hz to 62Hz for a 20SPS data rate. All filter plots are generated with 4.096MHz external clock.

Table 7. Modulator Clock Frequency for Different

Data Rates

DATA RATE f

(SPS) (kHz)

5, 10, 20 32

40, 80, 160 128

320, 640, 1000 256

2000 512

MOD

Table 8. Digital Filter Specifications

DATA RATE –3dB BANDWIDTH fIN= 50Hz ±0.3Hz fIN= 60Hz ±0.3Hz fIN= 50Hz ±1Hz fIN= 60Hz ±1Hz

5SPS 2.26Hz –106dB –74dB –81dB –69dB 10SPS 4.76Hz –106dB –74dB –80dB –69dB 20SPS 14.8Hz –71dB –74dB –66dB –68dB 40SPS 9.03Hz 80SPS 19.8Hz

160SPS 118Hz 320SPS 154Hz

(1) Values shown for f

640SPS 495Hz 1000SPS 732Hz 2000SPS 1465Hz

= 4.096MHz.

OSC

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(1)

ATTENUATION

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

50 52 54 56 58 60

-60

-70

-80

-90

-100

-110

-120

Frequency(Hz)

Magnitude(dB)

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Magnitude(dB)

800 1000 1200 1400 1600 1800 2000

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Magnitude(dB)

800 1000 1200 1400 1600 1800 2000

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 14. Filter Profile with Data Rate = 5SPS Figure 17. Detailed View of Filter Profile with Data

Rate = 20SPS between 48Hz and 62Hz

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Figure 15. Filter Profile with Data Rate = 10SPS

Figure 18. Filter Profile with Data Rate = 40SPS

Figure 16. Filter Profile with Data Rate = 20SPS

Figure 19. Filter Profile with Data Rate = 80SPS

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200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Magnitude(dB)

800 1000 1200 1400 1600 1800 2000

-20

-40

-60

-80

-100

-120

0 2 3

Frequency(kHz)

Magnitude(dB)

4 5 6 7 8 9 10

500

-20

-40

-60

-80

-100

-120

0 1000 1500

Frequency(Hz)

Magnitude(dB)

2000 2500 3000 3500 4000 4500 5000

-20

-40

-60

-80

-100

-120

0 4 6

Frequency(kHz)

Magnitude(dB)

8 10 12 14 16 18 20

500

-20

-40

-60

-80

-100

-120

0 1000 1500

Frequency(Hz)

Magnitude(dB)

2000 2500 3000 3500 4000 4500 5000

ADS1146 ADS1147 ADS1148

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Figure 20. Filter Profile with Data Rate = 160SPS Figure 23. Filter Profile with Data Rate = 1kSPS

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 21. Filter Profile with Data Rate = 320SPS Figure 24. Filter Profile with Data Rate = 2kSPS

CLOCK SOURCE

The ADS1146/7/8 can use either the internal oscillator or an external clock. Connect the CLK pin to DGND before power-on or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator, with the device then operating on the external clock. After the device switches to the external clock, it cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device.

Figure 22. Filter Profile with Data Rate = 640SPS

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SBAS453C –JULY 2009–REVISED APRIL 2010

INTERNAL VOLTAGE REFERENCE EXCITATION CURRENT SOURCE DACS

The ADS1147 and ADS1148 include an onboard The ADS1147 and ADS1148 provide two matched voltage reference with a low temperature coefficient. excitation current sources for RTD applications. For The output of the voltage reference is 2.048V with the three- or four-wire RTD applications, the matched capability of both sourcing and sinking up to 10mA of current sources can be used to cancel the errors current. caused by sensor lead resistance. The output current

The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance should be in the range of 1mF to 47mF. Large values provide more filtering of The two matched current sources can be connected the reference; however, the turn-on time increases to dedicated current output pins IOUT1 and IOUT2 with capacitance, as shown in Table 9. For stability (ADS1148 only), or to any AIN pin (ADS1147 and reasons, VREFCOM must have a path with an ADS1148); refer to the ADS1147/48 Detailed impedance less than 10Ω to ac ground nodes, such Register Definitions section for more information. It is as AVSS (for a 0V to 5V analog power supply), or possible to connect both current sources to the same GND (for a ±2.5V analog power supply). In case this pin. Note that the internal reference must be turned impedance is higher than 10Ω, a capacitor of at least on and properly compensated when using the

0.1mF should be connected between VREFCOM and excitation current source DACs. an ac ground node (for example, GND). Note that because it takes time for the voltage reference to settle to the final voltage, care must be taken when the device is turned off between conversions. Allow adequate time for the internal reference to fully settle.

Table 9. Internal Reference Settling Time

VREFOUT SETTLING TIME TO REACH THE

CAPACITOR ERROR SETTLING ERROR

1mF

4.7mF

47mF

±0.5% 70ms ±0.1% 110ms ±0.5% 290ms ±0.1% 375ms ±0.5% 2.2ms ±0.1% 2.4ms

The onboard reference is controlled by the registers; by default, it is off after startup (see the ADS1147/48

Detailed Register Definitions section for more details).

Therefore, the internal reference must first be turned on and then connected via the internal reference multiplexer. Because the onboard reference is used to generate the current reference for the excitation current sources, it must be turned on before the excitation currents become available.

of the current source DACs can be programmed to 50mA, 100mA, 250mA, 500mA, 750mA, 1000mA, or 1500mA.

SENSOR DETECTION

The ADS1146/7/8 provide a selectable current (0.5mA, 2mA, or 10mA) to help detect a possible sensor malfunction.

When enabled, two burnout current sources flow through the selected pair of analog inputs to the sensor. One sources the current to the positive input channel, and the other sinks the same current from the negative input channel.

When the burnout current sources are enabled, a full-scale reading may indicate an open circuit in the front-end sensor, or that the sensor is overloaded. It may also indicate that the reference voltage is absent. A near zero reading may indicate a short-circuit in the sensor.

BIAS VOLTAGE GENERATION

A selectable bias voltage is provided for use with ungrounded thermocouples. The bias voltage is (AVDD + AVSS)/2 and can applied to any analog input channel through internal input multiplexer. The bias voltage turn-on times for different sensor capacitances are listed in Table 10.

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Table 10. Bias Voltage Settling Time

SENSOR CAPACITANCE SETTLING TIME

0.1mF 220ms 1mF 2.2ms

10mF 22ms

200mF 450ms

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IOCFG

AINx/GPIOx

ToAnalogMux

DIOWRITE

IODIR

DIOREAD

REFx0/GPIOx

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ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

GENERAL-PURPOSE DIGITAL I/O

The ADS1148 has eight pins and the ADS1147 has four pins that serve a dual purpose as either analog inputs or general-purpose digital inputs/outputs (GPIOs).

Figure 25 shows a diagram of how these functions

are combined onto a single pin. Note that when the pin is configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the ADS1147 and ADS1148 are operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken loading the GPIO pins when used as outputs because large currents can cause droop or noise on the analog supplies.

Figure 25. Analog/Data Interface Pin

SYSTEM MONITOR

The ADS1147 and ADS1148 provide a system monitor function. This function can measure the analog power supply, digital power supply, external voltage reference, or ambient temperature. Note that the system monitor function provides a coarse result. When the system monitor is enabled, the analog inputs are disconnected.

Power-Supply Monitor

The system monitor can measure the analog or digital power supply. When measuring the power supply, the resulting conversion is approximately 1/4 of the actual power supply voltage.

Conversion result = (VSP/4)/V

REF

(5)

Where VSPis the selected supply to be measured.

External Voltage Reference Monitor

The ADS1146/7/8 can be selected to measure the external voltage reference. In this configuration, the monitored external voltage reference is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage.

Conversion result = (V

Where V

is the external reference to be

REX

/4)/V

REF

(6)

monitored. NOTE: The internal reference voltage must be

enabled when measuring an external voltage reference using the system monitor.

Ambient Temperature Monitor

On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118mV at +25°C with a temperature coefficient of 405mV/°C.

Note that when the onboard temperature monitor is selected, the PGA is automatically set to '1'. However, the PGA register bits in are not affected and the PGA returns to its set value when the temperature monitor is turned off.

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ADC

OFC

Final Output

OutputData

Clippedto16Bits

FSCRegister

400000h

FinalOutputData= (Input OFC[2:1])- ´

FSC[2:0]

400000h

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

CALIBRATION Note that while the offset calibration register value

The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 26, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC). A digital clipping circuit ensures the output code does not The full-scale or gain calibration is a 24-bit word exceed 16 bits. Equation 7 shows the scaling. composed of three 8-bit registers. The full-scale

Figure 26. Calibration Block Diagram

(7)

The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically by calibration commands.

Offset Calibration Register: OFC[2:0]

The offset calibration is a 24-bit word, composed of three 8-bit registers. The upper 16 bits, OFC[2:1], are the most important for calibration and can correct offsets ranging from –FS to +FS, as shown in

Table 11. The lower eight bits, OFC[0], provide

sub-LSB correction and are used by the ADS1146/7/8 calibration commands. If an ADS1146/7/8 calibration command is issued and the offset register is then read for storage and re-use later, it is recommended that all 24 bits of the OFC be used. When the calibration commands are not used and the offset is corrected by writing a user-calculated value to the OFC register, it is recommended that only that only OFC[2:1] be used and that OFC[0] be left as all zeros.

Table 11. Final Output Code versus Offset

Calibration Register Setting

FINAL OUTPUT CODE WITH

OFFSET REGISTER VIN= 0

7FFFFFh 8000000h 000001h FFFFFFh 000000h 000000h

FFFFFFh 000000h

8000000h 7FFFFFh

1. Excludes effects of noise and inherent offset errors.

can correct offsets ranging from –FS to +FS (as shown in Table 11), make sure to avoid overloading the analog inputs.

Full-Scale Calibration Register: FSC[2:0]

calibration value is 24-bit, straight binary, normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the full-scale register. Note that while the full-scale calibration register can correct gain errors > 1 (with gain scaling < 1), make sure to avoid overloading the analog inputs. The default or reset value of FSC depends on the PGA setting. A different factory-trimmed FSC Reset value is stored for each PGA setting which provides outstanding gain accuracy over all the ADS1146/7/8 input ranges. Note: The factory-trimmed FSC reset value loads automatically loaded whenever the PGA setting changes.

Table 12. Gain Correction Factor versus

Full-Scale Calibration Register Setting

FULL-SCALE REGISTER GAIN SCALING

800000h 2.0 400000h 1.0 200000h 0.5 000000h 0

Calibration Commands

The ADS1146/7/8 provide commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is needed, it is recommended that calibration be performed after power on, a change in temperature, a change of PGA and in some cases a change in channel. At the completion of calibration, the DRDY signal goes low indicating the calibration is finished. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the devices goes to sleep after completing calibration.

System Gain Calibration

System gain calibration corrects for gain error in the signal path. The system gain calibration is initiated by sending the SYSGCAL command while applying a full-scale input to the selected analog inputs. Afterwards the full-scale calibration register (FSC) is updated. When a system gain calibration command is issued, the ADS1146/7/8 stop the current conversion and start the calibration procedure immediately.

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CalibrationTime=

OSC

MOD

DATA

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ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

System Offset and Self Offset Calibration

System offset calibration corrects both internal and external offset errors. The system offset calibration is initiated by sending the SYSOCAL command while applying a zero differential input (VIN= 0) to the selected analog inputs. The self offset calibration is initiated by sending the SELFOCAL command. During self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero differential signal is applied internally. With both offset calibrations the offset calibration register (OFC) is updated afterwards. When either offset calibration command is issued, the ADS1146/7/8 stop the current conversion and start the calibration procedure immediately.

Calibration Timing

When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This provides a more accurate calibration value. The time required for calibration is shown in Table 13 and can be calculated using Equation 8:

(8)

Table 13. Calibration Time versus Data Rate

DATA RATE (SPS) CALIBRATION TIME (ms)

5 3201.01 10 1601.01 20 801.012 40 400.26 80 200.26

160 100.14 320 50.14

640 25.14 1000 16.14 2000 8.07

ADC SLEEP MODE

Power consumption can be dramatically reduced by placing the ADS1146/7/8 into sleep mode. There are two ways to put the device into sleep mode: the sleep command (SLEEP) and through the START pin.

During sleep mode, the internal reference status depends on the setting of the VREFCON bits in the MUX1 register; see the Register Descriptions section for details.

ADC CONTROL

ADC Conversion Control

The START pin provides easy and precise control of conversions. Pulse the START pin high to begin a conversion, as shown in Figure 27 and Table 14. The conversion completion is indicated by the DOUT/DRDY pin going low. When the conversion completes, the ADS1146/7/8 automatically shuts down to save power. During shutdown, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays shut down until the START pin is once again taken high to begin a new conversion. When the START pin is taken back high again, the decimation filter is held in a reset state for 32 modulator clock cycles internally to allow the analog circuits to settle.

The ADS1146/7/8 can be configured to convert continuously by holding the START pin high, as shown in Figure 28. With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low.

The START pin can also be used to perform the synchronized measurement for the multi-channel applications by pulsing the START pin.

1. For f

= 4.096MHz.

OSC

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Converting

START

DOUT/DRDY

SCLK

DRDY

ADS1146/7/8

Status

Shutdown

1 2 3 16

CONV

START

Converting Converting Converting Converting

START

DOUT/DRDY

ADS1146/7/8

Status

DataReady DataReady DataReady

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 27. Timing for Single Conversion Using START Pin

Table 14. START Pin Conversion Times for Figure 27

SYMBOL DESCRIPTION DATA RATE (SPS) VALUE UNIT

5 200.295 ms 10 100.644 ms 20 50.825 ms 40 25.169 ms

CONV

Time from START pulse to DRDY and

DOUT/DRDY going low

80 12.716 ms

160 6.489 ms 320 3.247 ms

640 1.692 ms 1000 1.138 ms 2000 0.575 ms

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NOTE: SCLK held low in this example.

Figure 28. Timing for Conversion with START Pin High

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RESET The filter is reset two system clocks after the last bit

When the RESET pin goes low, the device is immediately reset. All the registers are restored to default values. The device stays in reset mode as long as the RESET pin stays low. When it goes high, the ADC comes out of reset mode and is able to convert data. After the RESET pin goes high, and when the system clock frequency is 4.096MHz, the digital filter and the registers are held in a reset state for 0.6ms when f

= 4.096MHz. Therefore, valid

OSC

SPI communication can only be resumed 0.6ms after the RESET pin goes high, as shown in Figure 4. When the RESET pin goes low, the clock selection is reset to the internal oscillator.

of the SYNC command is sent. The reset pulse created internally lasts for two multiplier clock cycles. If any write operation takes place in the MUX0 register, the filter is reset regardless of whether the value changed or not. Internally, the filter pulse lasts for two system clock periods. If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, the filter is reset as well, regardless of whether the value changed or not. The reset pulse lasts for 32 modulator clocks after the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.

Table 15 shows the conversion time after a filter

Digital Filter Reset Operation reset. Note that this time depends on the operation Apart from the RESET command and the RESET pin,

the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0

initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.

registers is performed, when a SYNC command is issued, or the START pin is taken high.

SBAS453C –JULY 2009–REVISED APRIL 2010

Table 15. Data Conversion Time

FIRST DATA CONVERSION TIME AFTER FILTER RESET

HARDWARE RESET, RESET

COMMAND, START PIN HIGH,

SYNC COMMAND, MUX0 MUX1, or SYS0 REGISTER CONVERSION TIME AFTER

NOMINAL EXACT DATA SYSTEM SYSTEM SYSTEM

DATA RATE RATE CLOCK CLOCK CLOCK

(SPS) (SPS) (ms)

5 5.019 199.264 816188 200.266 820290 199.250 816128 10 10.038 99.639 408124 100.641 412226 99.625 408064 20 20.075 49.827 204092 50.828 208194 49.812 204032 40 40.151 24.920 102076 25.172 103106 24.906 102016 80 80.301 12.467 51068 12.719 52098 12.453 51008

160 160.602 6.241 25564 6.492 26594 6.226 25504 320 321.608 3.124 12796 3.250 13314 3.109 12736

640 643.216 1.569 6428 1.695 6946 1.554 6368 1000 1000.000 1.014 4156 1.141 4674 1.000 4096 2000 2000.000 0.514 2108 0.578 2370 0.500 2048

(1) For f

= 4.096MHz.

OSC

(1)

NO. OF NO. OF NO. OF

CYCLES (ms)

WAKEUP COMMAND, VBIAS, SECOND AND SUBSEQUENT

(1)

CYCLES (ms) CYCLES

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Data Format

The ADS1146/7/8 output 16 bits of data in binary twos complement format. The least significant bit (LSB) has a weight of (V

/PGA)/(215– 1). The

REF

positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 16 summarizes the ideal output codes for different input signals.

Table 16. Ideal Output Code vs Input Signal

INPUT SIGNAL, V

(AINP– AINN) IDEAL OUTPUT CODE

≥ +V

REF

(+V

/PGA)/(215– 1) 0001h DIN

REF

0 0000h

(–V

/PGA)/(215– 1) FFFFh

REF

≤ –(V

/PGA) × (215/215– 1) 8000h

REF

/PGA 7FFFh

1. Excludes effects of noise, linearity, offset, and gain errors.

Digital Interface

The ADS1146/7/8 provide a standard SPI serial communication interface plus a data ready signal (DRDY). Communication is full-duplex with the exception of a few limitations in regards to the RREG command and the RDATA command. These limitations are explained in detail in the SPI

Commands section of this data sheet. For the basic

serial interface timing characteristics, see Figure 1 and Figure 2 of this document.

This pin is the chip select pin (active low). The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is independent of CS.

Taking CS high deactivates only the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

SCLK

This signal is the serial clock signal. SCLK provides the clock for serial communication. It is a Schmitt-trigger input, but it is highly recommended that SCLK be kept as clean as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK.

This pin is the data input pin. DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling edge of SCLK.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, it is important to make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is to be sent to the device when reading out data, the NOP command should be sent on DIN.

DRDY

This pin is the data ready pin. The DRDY pin goes low to indicate a new conversion is complete, and the conversion result is stored in the conversion result buffer. The SPI clock must be low in a short time frame around the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, no commands should be issued during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, it is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for '0' instead of waiting for a falling edge). If the DRDY pin is not taken high after it falls low, a short high pulse is created on it to indicate the next data are ready.

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SCLK

D[15]

1 2 14 1 2 815 163

D[14] D[13] D[2] D[1] D[0]

DOUT/

(1)

DRDY

SCLK

DIN

D[15] D[14]D[15]D[14] D[13]

NOP NOP

D[2] D[1] D[0] D[0]

3 14 15

DOUT/

(1)

DRDY

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DOUT/DRDY DOUT/DRDY goes low, the data can be clocked out

This pin has two modes: data out (DOUT) only, or by providing 16 SCLKs. In order to force data out (DOUT) combined with data ready (DRDY). DOUT/DRDY high (so that DOUT/DRDY can be The DRDY MODE bit determines the function of this polled for a '0' instead of waiting for a falling edge), a pin. In either mode, the DOUT/DRDY pin goes to a no operation command (NOP) or any other command high-impedance state when CS is taken high. that does not load the data output register can be

When the DRDY MODE bit is set to '0', this pin functions as DOUT only. Data are clocked out at rising edge of SCLK, MSB first (see Figure 29).

When the DRDY MODE bit is set to '1', this pin functions as both DOUT and DRDY. Data are shifted out from this pin, MSB first, at the rising edge of SCLK. This combined pin allows for the same control but with fewer pins.

When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low if it is high. If it is already low, then DOUT/DRDY goes high

sent after reading out the data. Because SCLKs can only be sent in multiples of eight, a NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first rising edge of SCLK after reading the conversion result completely (see Figure 31). The same condition also applies after an RREG command. After all the register bits have been read out, the rising edge of SCLK forces DOUT/DRDY high. Figure 32 illustrates an example where sending four NOP commands after an RREG command forces the DOUT/DRDY pin high.

and then goes low (see Figure 30). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After

SBAS453C –JULY 2009–REVISED APRIL 2010

(1) CS tied low.

Figure 29. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)

(1) CS tied low.

Figure 30. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)

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SCLK

DIN

D[15] D[14]D[15]D[14] D[13]

NOP NOP NOP

D[2] D[1] D[0] D[0]

3 14 15 16 1 2 8

DOUT/

(1)

DRDY

SCLK

DOUT/

(1)

DRDY

DIN NOP

reg[7] reg[1] reg[0]

2 1 2 7 87 8

NOP

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

(1) DRDY MODE bit enabled, CS tied low.

Figure 31. DOUT/DRDY Forced High After Retrieving the Conversion Result

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(1) DRDY MODE bit enabled, CS tied low.

Figure 32. DOUT/DRDY Forced High After Reading Register Data

The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.

SPI Reset

SPI communication can be reset in several ways. In order to reset the SPI interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low causes the SPI interface to be reset along with all the other digital functions. In this case, the registers and the conversion are reset.

SPI Communication During Sleep Mode

When the START pin is low or the device is in sleep mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during sleep mode. Other commands do not function because the internal clock is shut down to save power during sleep mode.

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REGISTER DESCRIPTIONS

ADS1146 REGISTER MAP

Table 17. ADS1146 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h BCS BCS1 BCS0 0 0 0 0 0 1 01h VBIAS 0 0 0 0 0 0 VBIAS1 VBIAS0 02h MUX1 CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0 03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0 04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0 05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8 06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

0Ah ID ID3 ID2 ID1 ID0 0 0 0

DRDY

MODE

SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1146 DETAILED REGISTER DEFINITIONS BCS—Burnout Current Source Register. These bits control the settling of the sensor burnout detect current

source.

BCS - ADDRESS 00h RESET VALUE = 01h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BCS1 BCS0 0 0 0 0 0 1

Bits[7:6] BCS[1:0]

These bits select the magnitude of the sensor burnout detect current source. 00 = Burnout current source off (default) 01 = Burnout current source on, 0.5mA 10 = Burnout current source on, 2mA 11 = Burnout current source on, 10mA

Bits[5:0] These bits must always be set to '000001'.

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ADS1146 DETAILED REGISTER DEFINITIONS (continued) VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs.

VBIAS - ADDRESS 01h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 0 0 VBIAS1 VBIAS0

Bits[7:2] These bits must always be set to '000000'. Bits[1:0] VBIAS[1:0]

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0 is for AIN0, and bit 1 is for AIN1. 0 = Bias voltage not enabled (default) 1 = Bias voltage is applied to the analog input

MUX—Multiplexer Control Register.

MUX - ADDRESS 02h RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0

Bit 7 CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used. 0 = Internal oscillator in use 1 = External oscillator in use

Bits[6:3] These bits must always be set to '0000'. Bits[2:0] MUXCAL[2:0]

These bits are used to select a system monitor. The MUXCAL selection supercedes selections from the VBIAS register. 000 = Normal operation (default) 001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to midsupply (AVDD + AVSS)/2. 010 = Gain calibration. The analog inputs are connected to the voltage reference. 011 = Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device.

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Table 18 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to

the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 18. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT

000 Set by SYS0 register Normal operation 001 Set by SYS0 register Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2 010 Forced to 1 Gain calibration: V 011 Forced to 1 Temperature measurement diode

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REFP

– V

REFN

(full-scale)

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ADS1146 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0.

SYS0 - ADDRESS 03h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0

Bit 7 These bits must always be set to '0'. Bits[6:4] PGA[2:0]

These bits determine the gain of the PGA. 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128

Bits[3:0] DOR[3:0]

These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the highest data rate of 2000SPS. 0000 = 5SPS (default) 0001 = 10SPS 0010 = 20SPS 0011 = 40SPS 0100 = 80SPS 0101 = 160SPS 0110 = 320SPS 0111 = 640SPS 1000 = 1000SPS 1001 to 1111 = 2000SPS

SBAS453C –JULY 2009–REVISED APRIL 2010

OFC[23:0]

These bits make up the offset calibration coefficient register of the ADS1148.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

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ADS1146 DETAILED REGISTER DEFINITIONS (continued) FSC[23:0]

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

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FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

ID—ID Register

IDAC0 - ADDRESS 0Ah RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ID3 ID2 ID1 ID0 DRDY MODE 0 0 0

Bits 7:4 ID3:0

Read-only, factory-programmed bits; used for revision identification.

Bit 3 DRDY MODE

This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY pin continues to indicate data ready, active low. 0 = DOUT/DRDY pin functions only as Data Out (default) 1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low

Bits 2:0 These bits must always be set to '000'.

(1)

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ADS1147 AND ADS1148 REGISTER MAP

Table 19. ADS1147 and ADS1148 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h MUX0 BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0 01h VBIAS VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0 02h MUX1 CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0 03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0 04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0 05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8 06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

0Ah IDAC0 ID3 ID2 ID1 ID0 IMAG2 IMAG1 IMAG0 0Bh IDAC1 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0

0Ch GPIOCFG IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0 0Dh GPIODIR IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0 0Eh GPIODAT IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0

DRDY

MODE

SBAS453C –JULY 2009–REVISED APRIL 2010

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SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected

on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

MUX0 - ADDRESS 00h RESET VALUE = 01h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0

Bits[7:6] BCS[1:0]

These bits select the magnitude of the sensor detect current source. 00 = Burnout current source off (default) 01 = Burnout current source on, 0.5mA 10 = Burnout current source on, 2mA 11 = Burnout current source on, 10mA

Bits[5:3] MUX_SP[2:0]

Positive input channel selection bits. 000 = AIN0 (default) 001 = AIN1 010 = AIN2 011 = AIN3 100 = AIN4 (ADS1148 only) 101 = AIN5 (ADS1148 only) 110 = AIN6 (ADS1148 only) 111 = AIN7 (ADS1148 only)

Bits[2:0] MUX_SN[2:0]

Negative input channel selection bits. 000 = AIN0 001 = AIN1 (default) 010 = AIN2 011 = AIN3 100 = AIN4 (ADS1148 only) 101 = AIN5 (ADS1148 only) 110 = AIN6 (ADS1148 only) 111 = AIN7 (ADS1148 only)

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VBIAS—Bias Voltage Register

VBIAS - ADDRESS 01h RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0 ADS1147 0 0 0 0 VBIAS3 VBIAS2 VBIAS1 VBIAS0

Bits[7:0] VBIAS[7:0]

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. 0 = Bias voltage not enabled (default) 1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) MUX1—Multiplexer Control Register 1

MUX1 - ADDRESS 02h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0

Bit 7 CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used. 0 = Internal oscillator in use 1 = External oscillator in use

Bits[6:5] VREFCON[1:0]

These bits control the internal voltage reference. These bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. Note that the internal reference is required for operation of the IDAC functions. 00 = Internal reference is always off (default) 01 = Internal reference is always on 10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the device receives a shutdown opcode or the START pin is taken low

Bits[4:3] REFSELT[1:0]

These bits select the reference input for the ADC. 00 = REF0 input pair selected (default) 01 = REF1 input pair selected (ADS1148 only) 10 = Onboard reference selected 11 = Onboard reference selected and internally connected to REF0 input pair

Bits[2:0] MUXCAL[2:0]

These bits are used to select a system monitor. The MUXCAL selection supercedes selections from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS). 000 = Normal operation (default) 001 = Offset measurement 010 = Gain measurement 011 = Temperature diode 100 = External REF1 measurement (ADS1148 only) 101 = External REF0 measurement 110 = AVDD measurement 111 = DVDD measurement

SBAS453C –JULY 2009–REVISED APRIL 2010

Table 20 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting

reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 20. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT

000 Set by SYS0 register Normal operation 001 Set by SYS0 register Inputs shorted to midsupply (AVDD + AVSS)/2 010 Forced to 1 V 011 Forced to 1 Temperature measurement diode 100 Forced to 1 (V 101 Forced to 1 (V 110 Forced to 1 (AVDD – AVSS)/4 111 Forced to 1 (DVDD – DVSS)/4

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REFP

– V

REFP1 REFP0

REFN

– V – V

(full-scale)

)/4

REFN1

)/4

REFN0

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0

SYS0 - ADDRESS 03h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0

Bit 7 This bit must always be set to '0' Bits[6:4] PGA[2:0]

These bits determine the gain of the PGA. 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128

Bits[3:0] DOR[3:0]

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OFC[23:0]

These bits make up the offset calibration coefficient register of the ADS1148.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) FSC[23:0]

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

IDAC0—IDAC Control Register 0

IDAC0 - ADDRESS 0Ah RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ID3 ID2 ID1 ID0 DRDY MODE IMAG2 IMAG1 IMAG0

Bits[7:4] ID[3:0]

Read-only, factory-programmed bits; used for revision identification.

Bit 3 DRDY MODE

Bits[2:0] IMAG[2:0]

The ADS1147 and ADS1148 have two programmable current source DACs that can be used for sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the internal reference to be on. 000 = off (default) 001 = 50mA 010 = 100mA 011 = 250mA 100 = 500mA 101 = 750mA 110 = 1000mA 111 = 1500mA

(1)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) IDAC1—IDAC Control Register 1

IDAC1 - ADDRESS 0Bh RESET VALUE = FFh

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0 ADS1147 0 0 I1DIR1 I1DIR0 0 0 I2DIR1 I2DIR0

The two IDACs on the ADS1147 and ADS1148 can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.

Bits[7:4] I1DIR[3:0]

These bits select the output pin for the first current source DAC. 0000 = AIN0 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 (ADS1148 only) 0101 = AIN5 (ADS1148 only) 0110 = AIN6 (ADS1148 only) 0111 = AIN7 (ADS1148 only) 10x0 = IEXT1 (ADS1148 only) 10x1 = IEXT2 (ADS1148 only) 11xx = Disconnected (default)

Bits[3:0] I2DIR[3:0]

These bits select the output pin for the second current source DAC. 0000 = AIN0 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 (ADS1148 only) 0101 = AIN5 (ADS1148 only) 0110 = AIN6 (ADS1148 only) 0111 = AIN7 (ADS1148 only) 10x0 = IEXT1 (ADS1148 only) 10x1 = IEXT2 (ADS1148 only) 11xx = Disconnected (default)

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Product Folder Link(s): ADS1146 ADS1147 ADS1148

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) GPIOCFG—GPIO Configuration Register. The GPIO and analog pins are shared as follows:

GPIO0 shared with REFP0 GPIO1 shared with REFN0 GPIO2 shared with AIN2 GPIO3 shared with AIN3 GPIO4 shared with AIN4 (ADS1148) GPIO5 shared with AIN5 (ADS1148) GPIO6 shared with AIN6 (ADS1148) GPIO7 shared with AIN7 (ADS1148)

GPIOCFG - ADDRESS 0Ch RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0 ADS1147 0 0 0 0 IOCFG3 IOCFG2 IOCFG1 IOCFG0

Bits[7:0] IOCFG[7:0]

These bits enable the GPIO because the GPIO pins are shared with the analog pins. Note that the ADS1148 uses all the IOCFG bits, whereas the ADS1147 uses only bits 3:0. 0 = The pin is used as an analog input (default) 1 = The pin is used as a GPIO pin

SBAS453C –JULY 2009–REVISED APRIL 2010

GPIODIR—GPIO Direction Register

GPIODIR - ADDRESS 0Dh RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0 ADS1147 0 0 0 0 IODIR3 IODIR2 IODIR1 IODIR0

Bits[7:0] IODIR[7:0]

These bits control the direction of the GPIO when enabled by the IOCFG bits. Note that the ADS1148 uses all the IODIR bits, whereas the ADS1147 uses only bits 3:0. 0 = The GPIO is an output (default) 1 = The GPIO is an input

GPIODAT—GPIO Data Register

GPIODAT - ADDRESS 0Eh RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0 ADS1147 0 0 0 0 IODAT3 IODAT2 IODAT1 IODAT0

Bits[7:0] IODAT[7:0]

If a GPIO pin is enabled in the GPIOCFG register and configured as an output in the GPIO Direction register (GPIODIR), the value written to this register appears on the appropriate GPIO pin. If a GPIO pin is configured as an input in GPIODIR, reading this register returns the value of the digital I/O pins. Note that the ADS1148 uses all eight IODAT bits, while the ADS1147 uses only bits 3:0.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

SPI COMMANDS

SPI COMMAND DEFINITIONS

The commands shown in Table 21 control the operation of the ADS1146/7/8. Some of the commands are stand-alone commands (for example, RESET), whereas others require additional bytes (for example, WREG requires command, count, and the data bytes).

Operands:

n = number of registers to be read or written (number of bytes – 1) r = register (0 to 15) x = don't care

Table 21. SPI Commands

COMMAND TYPE COMMAND DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE

WAKEUP Exit sleep mode 0000 000x (00h, 01h)

SLEEP Enter sleep mode 0000 001x (02h, 03h)

System Control SYNC Synchronize the A/D conversion 0000 010x (04h, 05h) 0000-010x (04,05h)

RESET Reset to power-up values 0000 011x (06h, 07h)

NOP No operation 1111 1111 (FFh)

RDATA Read data once 0001 001x (12h, 13h)

Data Read RDATAC Read data continuously 0001 010x (14h, 15h)

SDATAC Stop reading data continuously 0001 011x (16h, 17h)

Read Register RREG Read from register rrrr 0010 rrrr (2xh) 0000_nnnn

Write Register WREG Write to register rrrr 0100 rrrr (4xh) 0000_nnnn

SYSOCAL System offset calibration 0110 0000 (60h)

Calibration SYSGCAL System gain calibration 0110 0001 (61h)

SELFOCAL Self offset calibration 0110 0010 (62h)

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Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

SCLK

DRDY

Status

SLEEP

NormalMode SleepMode

FinishCurrentConversion

NormalMode

StartNewConversion

EighthSCLK

WAKEUP

0000001X 0000000X

Synchronization OccursHere

2t

OSC

SYNC

DIN

SCLK

0000010X 0000010X

SCLK

RESET

1 8

AnySPI

Command

DIN

0.6ms

ADS1146 ADS1147 ADS1148

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SYSTEM CONTROL COMMANDS WAKEUP—Wake up from sleep mode that is set by the SLEEP command.

Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the device wakes up on the rising edge of the eighth SCLK.

SLEEP—Set the device to sleep mode; issue the WAKEUP command to deactivate SLEEP mode.

This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the device completes the current conversion and then goes into sleep mode. Note that this command does not automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for each device for further details.

To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 33. SLEEP and WAKEUP Commands Operation

SYNC—Synchronize DRDY.

This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices simultaneously.

Figure 34. SYNC Command Operation

RESET—Reset the device to power-up state.

This command restores the registers to the respective power-up values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the wrong state, the device will not reset. The CS pin can be used to reset SPI interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the hardware reset. Therefore, SPI communication can be only be started 0.6ms after the RESET command is issued, as shown in Figure 35.

Figure 35. SPI Communication After an SPI Reset

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

DOUT

DRDY

RDATAC

SCLK

16Bits

NOP

0001010X

DIN

DRDY

0001011X

SDATAC

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

DATA RETRIEVAL COMMANDS RDATAC—Read data continuously.

The RDATAC command enables the automatic loading of a new conversion result into the output data register. In this mode, the conversion result can be received once from the device after the DRDY signal goes low by sending 16 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the command takes effect on the next DRDY.

Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge will occur.

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Figure 36. Read Data Continuously

SDATAC—Stop reading data continuously.

The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not automatically loaded into the output shift register when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

Figure 37. Stop Reading Data Continuously

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SCLK

DIN

DOUT

DRDY

MSB

0001001X

LSB

1 8 1 16

NOP NOP

RDATA

SCLK

DOUT

DIN

DRDY

NOPNOP NOP RDATA NOP NOP

D[15] D[6] D[1] D[1] D[0]D[9] D[8] D[7]D[14] D[15] D[14]

2 1 29 107 8 15 16 15 16

D[0]

ADS1146 ADS1147 ADS1148

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RDATA—Read data once.

The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result can be read out by sending 16 SCLKs, as shown in Figure 38. This command also works in RDATAC mode.

When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the SPI interface, as shown in Figure 39.

Figure 38. Read Data Once

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 39. Using RDATA in Full-Duplex Mode

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

DOUT

VBIAS

00100001 00000001

1st

Command

Byte

2nd

Command

Byte

MUX1

DataByte DataByte

DIN

01000010 00000001 MUX2 SYS0

1st

Command

2nd

Command

Data

Byte

Data

Byte

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

USER REGISTER READ AND WRITE COMMANDS RREG—Read from registers.

This command outputs the data from up to 16 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning.

1st Command Byte: 0010 rrrr, where rrrr is the address of the first register to read. 2nd Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.

It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in

Figure 40. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send

NOP through the DIN when reading out the register data.

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Figure 40. Read from Register

WREG—Write to registers.

This command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte.

1st Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written. 2nd Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1. Data Byte(s): data to be written to the registers.

Figure 41. Write to Register

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SCLK

DIN

DRDY

1 8

CAL

Calibration Command

Calibration

Starts

Calibration

Complete

ADS1146 ADS1147 ADS1148

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CALIBRATION COMMANDS

The ADS1146/7/8 provide system and offset calibration commands and a system gain calibration command. SYSOCAL—Offset system calibration.

This command initiates a system offset calibration. For a system offset calibration, the input should be externally set to zero. The OFC register is updated when this operation completes.

SYSGCAL—System gain calibration.

This command initiates the system gain calibration. For a system gain calibration, the input should be set to full-scale. The FSC register is updated after this operation.

SELFOCAL—Self offset calibration.

This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the calibration. The OFC register is updated after this operation.

SBAS453C –JULY 2009–REVISED APRIL 2010

Figure 42. Calibration Command

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

START

RESET

DRDY

SCLK

3 00 00 00

Conversionresult

forchannel1

Power-upsequence ADCinitialsetup Multiplexerchangeischannel2 DataRetrievalfor

Channel2Conversion

Initialsetting: AIN0isthepositivechannel, AIN1isthenegativechannel, internalreferenceselected, PGAgain=32, datarate=2kSPS, VBIASisconnectedtothe negativepinsAIN1andAIN3.

AIN2isthepositivechannel, AIN3isthenegativechannel.

Conversionresult

forchannel2

01 02 03

WREG WREG

DIN

DOUT

DRDY

0.513ms for

MUX0

Write

NOP

16ms

(1)

ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

APPLICATION INFORMATION

SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels

This section contains several examples of SPI communication with the ADS1146/7/8, including the power-up sequence.

Channel Multiplexing Example

This first example applies only to the ADS1147 and ADS1148. It explains a method to use the device with two sensors connected to two different analog channels. Figure 43 shows the sequence of SPI operations performed on the device. After power-up, 216system clocks are required before communication may be started. During the first 216system clock cycles, the devices are internally held in a reset state. In this example, one of the sensors is connected to channels AIN0 and AIN1 and the other sensor is connected to channels AIN2 and AIN3. The ADC is operated at a data rate of 2kSPS. The PGA gain is set to 32 for both sensors. VBIAS is connected to the

AIN1 and AIN3). All these settings can be changed by performing a block write operation on the first four registers of the device. After the DRDY pin goes low, the conversion result can be immediately retrieved by sending in 16 SPI clock pulses because the device defaults to RDATAC mode. As the conversion result is being retrieved, the active input channels can be switched to AIN2 and AIN3 by writing into the MUX0 register in a full-duplex manner, as shown in

Figure 43. The write operation is completed with an

additional eight SPI clock pulses. The time from the write operation into the MUX0 register to the next DRDY low transition is shown in Figure 43 and is

0.513ms in this case. After DRDY goes low, the conversion result can be retrieved and the active channel can be switched as before.

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(1) For f

= 4.096MHz.

OSC

Figure 43. SPI Communication Sequence for Channel Multiplexing

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

START

RESET

DRDY

SCLK

Conversionresult

forchannel1

Power-upsequence ADCinitialsetup

ADCisputtosleep

afterasingleconversion.

Dataareretrievedwhen

ADCissleeping.

ADCenters

power-saving

sleepmode

01 02 03

WREG

DIN

DOUT

DRDY

(0.575ms)

NOP

16ms

(1)

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ADS1146 ADS1147 ADS1148

SBAS453C –JULY 2009–REVISED APRIL 2010

Sleep Mode Example

This second example deals with performing one conversion after power-up and then entering into the power-saving sleep mode. In this example, a sensor is connected to input channels AIN0 and AIN1. Commands to set up the devices must occur at least 216system clock cycles after powering up the devices. The ADC operates at a data rate of 2kSPS. The PGA gain is set to 32 for both sensors. VBIAS is connected to the negative terminal of both the sensors (that is, channel AIN1). All these settings can

be changed by performing a block write operation on the first four registers of the device. After performing the block write operation, the START pin can be taken low. The device enters the power-saving sleep mode as soon as DRDY goes low 0.575ms after writing into the SYS0 register. The conversion result can be retrieved even after the device enters sleep mode by sending 16 SPI clock pulses.

(1) For f

= 4.096MHz.

OSC

Figure 44. SPI Communication Sequence for Entering Sleep Mode After a Conversion

Product Folder Link(s): ADS1146 ADS1147 ADS1148

PACKAGE OPTION ADDENDUM

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28-May-2010

PACKAGING INFORMATION

Orderable Device

ADS1146IPW ACTIVE TSSOP PW 16 90 Green (RoHS

ADS1146IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS

ADS1147IPW ACTIVE TSSOP PW 20 70 Green (RoHS

ADS1147IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS

ADS1148IPW ACTIVE TSSOP PW 28 50 Green (RoHS

ADS1148IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

& no Sb/Br)

(2)

Lead/

Ball Finish

CU NIPDAU Level-1-260C-UNLIM Request Free Samples

CU NIPDAU Level-1-260C-UNLIM Purchase Samples

CU NIPDAU Level-2-260C-1 YEAR Request Free Samples

CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

CU NIPDAU Level-2-260C-1 YEAR Request Free Samples

CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

MSL Peak Temp

(3)

Samples

(Requires Login)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

28-May-2010

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

ADS1146IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS1147IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 ADS1148IPWR TSSOP PW 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jul-2010

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1146IPWR TSSOP PW 16 2000 346.0 346.0 29.0 ADS1147IPWR TSSOP PW 20 2000 346.0 346.0 33.0 ADS1148IPWR TSSOP PW 28 2000 346.0 346.0 33.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30

0,19

4,50 4,30

PINS **

Seating Plane

0,15 0,05

DIM

6,60 6,20

0,10

0,15 NOM

0°–8°

2016

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TEXAS INSTRUMENTS ADS1146, ADS1147, ADS1148 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

ELECTRICAL CHARACTERISTICS

PIN CONFIGURATIONS

TIMING DIAGRAMS

NOISE PERFORMANCE

TYPICAL CHARACTERISTICS

GENERAL DESCRIPTION

OVERVIEW

ADC INPUT AND MULTIPLEXER Any analog input pin can be selected as the positive

Settling Time for Channel Multiplexing

VOLTAGE REFERENCE INPUT

LOW-NOISE PGA

MODULATOR

DIGITAL FILTER

CLOCK SOURCE

INTERNAL VOLTAGE REFERENCE EXCITATION CURRENT SOURCE DACS

SENSOR DETECTION

BIAS VOLTAGE GENERATION

GENERAL-PURPOSE DIGITAL I/O

SYSTEM MONITOR

Power-Supply Monitor

External Voltage Reference Monitor

Ambient Temperature Monitor

CALIBRATION Note that while the offset calibration register value

Offset Calibration Register: OFC[2:0]

Full-Scale Calibration Register: FSC[2:0]

Calibration Commands

Calibration Timing

ADC SLEEP MODE

ADC CONTROL

ADC Conversion Control

Digital Filter Reset Operation reset. Note that this time depends on the operation Apart from the RESET command and the RESET pin,

Data Format

Digital Interface

SPI Reset

SPI Communication During Sleep Mode

REGISTER DESCRIPTIONS

ADS1146 REGISTER MAP

ADS1147 AND ADS1148 REGISTER MAP

SPI COMMANDS

SPI COMMAND DEFINITIONS

CALIBRATION COMMANDS

APPLICATION INFORMATION

SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels

Channel Multiplexing Example

Sleep Mode Example