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ADC3422EVM
User Manual
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Texas Instruments ADC3224EVM, ADC3241EVM, ADC3242EVM, ADC3221EVM, ADC3243EVM User Manual

...
User's Guide
SLAU579D–June 2014–Revised August 2018

ADC3xxxEVM and ADC3xJxxEVM

Contents
1 Introduction ................................................................................................................... 3
1.1 EVM Block Diagram................................................................................................ 4
1.2 EVM Power Supply................................................................................................. 6
1.3 EVM Connectors and Jumpers ................................................................................... 8
1.4 EVM ADC Input Circuit Configurations......................................................................... 12
1.5 EVM DC-Coupling Configuration ............................................................................... 12
2 Software Control............................................................................................................ 15
2.1 Installation Instructions ........................................................................................... 15
2.2 Software Operation ............................................................................................... 15
3 Basic Test Procedure...................................................................................................... 24
3.1 Test Block Diagram with ADC32xx and ADC34xx............................................................ 24
3.2 Test Set-up Connection .......................................................................................... 25
3.3 ADC32/34xx and TSW1400 Setup Guide...................................................................... 25
3.4 Test Block Diagram with ADC32Jxx and ADC34Jxx ......................................................... 27
3.5 Test Set-up Connection (Onboard LMK04828 Clock)........................................................ 28
3.6 ADC32J/34Jxx and TSW14J56 Setup Guide.................................................................. 29
1 Simplified ADC344x EVM Block Diagram................................................................................ 4
2 Simplified ADC34J4x EVM Block Diagram............................................................................... 5
3 Simplified EVM Power Supply ............................................................................................. 6
4 ADC34Jxx EVM Connector and Jumper Locations ..................................................................... 8
5 ADC34xx EVM Connector and Jumper Locations ...................................................................... 9
6 ADC3xxxx ADC Input Circuit Options ................................................................................... 12
7 ADC34xx Clock Input Circuit ............................................................................................. 12
8 ADC32xxVM Input Coupling Configuration Resistors ................................................................ 13
9 ADC3xJxx Input Coupling Configuration Resistors ................................................................... 14
10 Common Tab ............................................................................................................... 16
11 ADC32xx Tab............................................................................................................... 17
12 ADC34xx Tab............................................................................................................... 19
13 ADC32Jxx Tab ............................................................................................................. 21
14 ADC34Jxx Tab ............................................................................................................. 23
15 ADC32xx/ADC34xx and TSW1400 Test Setup Block Diagram...................................................... 24
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List of Figures
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ADC3xxxEVM and ADC3xJxxEVM
1
16 Select ADC32xx or 34xx in the HSDC Pro GUI Program............................................................. 25
17 ADC3xxx Operating in 14-Bit Mode at 125 MSPS With a 10-MHz Input Signal................................... 26
18 ADC32Jxx/ADC34Jxx and TSW14J56 Test Setup Block Diagram.................................................. 27
19 Select ADC32Jxx or 34Jxx in the HSDC Pro GUI Program.......................................................... 29
20 ADC32Jxx Operating in 14-Bit Mode at 160 MSPS With a 10-MHz Input Signal ................................. 30
1 ADC3xxx Family of Devices and EVMs .................................................................................. 3
2 Power Supply Options ...................................................................................................... 7
3 ADC3xxxx EVM Connectors.............................................................................................. 10
4 ADC3xxxx EVM Jumper Options......................................................................................... 11
5 ADC3xxxx EVM LED Indicators.......................................................................................... 11
6 ADC32xxEVM AC-DC Coupling Resistor Swap ....................................................................... 13
7 ADC3xJxxEVM AC-DC Coupling Resistor Swap ...................................................................... 14
Trademarks
All trademarks are the property of their respective owners.
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List of Tables
2
ADC3xxxEVM and ADC3xJxxEVM
Copyright © 2014–2018, Texas Instruments Incorporated
SLAU579D–June 2014–Revised August 2018
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1 Introduction

The family of parts and 32 associated EVMs are categorized in Table 1.
Interface Number of Channels ADC Device Number of Bits Maximum MSPS EVM
sLVDS Dual
sLVDS Quad
Introduction
Table 1. ADC3xxx Family of Devices and EVMs
ADC3221 12 25 ADC3221EVM ADC3222 12 50 ADC3222EVM ADC3223 12 80 ADC3223EVM ADC3224 12 125 ADC3224EVM ADC3241 14 25 ADC3241EVM ADC3242 14 50 ADC3242EVM ADC3243 14 80 ADC3243EVM ADC3244 14 125 ADC3244EVM
ADC3421 12 25 ADC3421EVM ADC3422 12 50 ADC3422EVM ADC3423 12 80 ADC3423EVM ADC3424 12 125 ADC3424EVM ADC3441 14 25 ADC3441EVM ADC3442 14 50 ADC3442EVM ADC3443 14 80 ADC3443EVM ADC3444 14 125 ADC3444EVM
ADC32J22 12 50 ADC32J22EVM ADC32J23 12 80 ADC32J23EVM ADC32J24 12 125 ADC32J24EVM
JESD204B Dual
JESD204B Quad
ADC32J25 12 160 ADC32J25EVM ADC32J42 14 50 ADC32J42EVM ADC32J43 14 80 ADC32J43EVM ADC32J44 14 125 ADC32J44EVM ADC32J45 14 160 ADC32J45EVM
ADC34J22 12 50 ADC34J22EVM ADC34J23 12 80 ADC34J23EVM ADC34J24 12 125 ADC34J24EVM ADC34J25 12 160 ADC34J25EVM ADC34J42 14 50 ADC34J42EVM ADC34J43 14 80 ADC34J43EVM ADC34J44 14 125 ADC34J44EVM ADC34J45 14 160 ADC34J45EVM
There are three package sizes and pinouts for all of these parts. The sLVDS dual devices use a 7-mm × 7-mm, 48-pin QFN package. The sLVDS quad devices use an 8-mm × 8-mm, 56-pin QFN package. The dual and quad JESD204B device share the same package using a 7-mm × 7-mm, 48-pin QFN package
The dual ADCs comprise two buffered inputs, two ADC cores, and a common input clock circuit. The quad ADCs comprise four buffered inputs, four ADC cores, and a common input clock circuit. The sLVDS versions have a 2-wire interface per ADC (two pairs of p/n signals)—for the dual, this means two sets of 2­wire interfaces (four p/n pairs), the quad has four sets of 2-wire interfaces (eight p/n pairs). Each of these 2-wire interfaces can be operated in 1-wire mode (14x serialization), or 2-wire mode (7x serialization). For the 12-bit devices, this equates to 12x and 6x serialization. The JESD204B versions have one lane per ADC core. For the dual, this means there are two lanes per device, and four lanes per device for the quad. See the respective device data sheet for more information on sLVDS serialization and JESD204B lane configurations.
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ADC3xxxEVM and ADC3xJxxEVM
3
CLK IN
14bit
ADC
14bit
ADC
14bit
ADC
14bit
ADC
Digital
Block
+
Output
Formatter
DCLK
DAB P/M sLVDS
2
DCD P/M sLVDS
2
Power
Supply
Circuits
USB
To
SPI
5V
USB
ADC34xx
CH A
CH B
CH C
CH D
FCLK
Introduction

1.1 EVM Block Diagram

Figure 1 and Figure 2 show simplified block diagrams of the default configuration of the EVM. The two or
four analog inputs are supplied to the EVM through a single-ended SMA connection, then transformer coupled to turn the single-ended signal into a balanced differential signal, and then input to the ADC32xxx or ADC34xxx. A dual transformer input circuit is used for better phase and amplitude balance of the input signal than is typically produced by a single transformer input circuit.
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Figure 1. Simplified ADC344x EVM Block Diagram
4
ADC3xxxEVM and ADC3xJxxEVM
Copyright © 2014–2018, Texas Instruments Incorporated
SLAU579D–June 2014–Revised August 2018
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14bit
ADC
14bit
ADC
14bit
ADC
14bit
ADC
Digital
Block
+
Output
Formatter
SYNC
SERDES Lane 0,1
2
SERDES Lane 3,4
2
Power
Supply
Circuits
USB
To
SPI
5V
USB
ADC34Jxx
CLK IN
CH A
CH B
CH C
CH D
SYSREF
LMK04828
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Introduction
Figure 2. Simplified ADC34J4x EVM Block Diagram
The clock input is supplied by way of a single-ended signal to an SMA connector, and transformer coupled to produce a differential clock signal for the ADC32/34xx EVM. For the ADC32J/34Jxx EVM, the clock input can be generated onboard using the LMK04828.
Power to the ADC3xxx EVM is typically supplied from a 5-V bench supply using the onboard barrel connector and the provided cable, or from an appropriate 5-V, 3-A minimum power brick. All necessary voltages for the ADC EVM are derived from the 5-V input connection.
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ADC3xxxEVM and ADC3xJxxEVM
5
GND
5V
TPS62080
1
TPS7A4700
1.8V To ADC
4V to Amp
TPS2400
1
TPS7A4700
Overvoltage
Protection Circuit
DC/DC Converter
Low Noise LDO
Low Noise LDO
ADC32/34xx EVM
GND
5V
TPS62080
1
TPS7A4700
1.8V To ADC
4V to Amp
TPS2400
1
TPS7A4700
Overvoltage
Protection Circuit
DC/DC Converter
Low Noise LDO
Low Noise LDO
ADC32J/34Jxx EVM
TPS62080
1
TPS7A4700
3.3V to
LMK04828
1
Low Noise LDO
Introduction

1.2 EVM Power Supply

Figure 3 illustrates the power supply options available on the ADC3xxx EVM. Jumpers are used to choose
the power-supply options, with the default jumper positions indicated by the darker portion of the jumper that represents the presence of the jumper. See Table 2 for jumper and feedback resistor configuration.
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ADC3xxxEVM and ADC3xJxxEVM
Figure 3. Simplified EVM Power Supply
Copyright © 2014–2018, Texas Instruments Incorporated
SLAU579D–June 2014–Revised August 2018
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The default power path has an efficient, dual-output, DC/DC switching power supply to first step down the input supplies from 5 V to 4 V, and 2.8 V for the subsequent low-noise LDOs. The 4 V is used by an LDO to derive 3.3 V for the LMK04828 clock circuits on the ADC3xJxx EVMs. The 2.8 V is used by an LDO to derive a 1.8-V supply for the ADC and USB circuits.
The low-noise LDOs can be bypassed to allow the DC/DC power supply to directly provide the ADC power. Note that the feedback resistors of the DC/DC converter must be adjusted accordingly. See the respective ADC EVM user's guide schematic for details.
Introduction
Table 2. Power Supply Options
Device Description
ADC32xx
JP6: 1-2, JP7: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U4, install R79 for 1.8-V
switcher output
ADC34xx
JP6: 1-2, JP7: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U4, install R79 for 1.8-V
switcher output
ADC342J/34Jxx
JP9: 1-2, JP10: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U8, install R152 for 1.8-V
switcher output
JP12: 1-2, JP13: 1-2 Default connection for LDO 3.3 V for LMK04828 power and onboard SPI/CPLD, switch both to 2-3 to use
U11 switcher output, install R163 for 3.3-V switcher output
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Introduction

1.3 EVM Connectors and Jumpers

Figure 4 and Figure 5 show the locations of the connectors, jumpers, pushbutton switches, and LEDs.
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Figure 4. ADC34Jxx EVM Connector and Jumper Locations
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Introduction
Figure 5. ADC34xx EVM Connector and Jumper Locations
The EVM has a barrel connector for 5-V power. The SMA connectors connect the ADC input and ADC clock input to the ADC. Typically, the ADC inputs are transformer-coupled to accept single-ended connections. The input circuit can be configured to connect to two SMA connectors for differential signaling, if desired. Table 3 lists the connector information for the ADC3xxxx.
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Introduction
ADC32xx J1 AINP – positive input for A, Ch1 single ended input
ADC34xx J1 AINP – positive input for A, Ch1 single ended input
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Table 3. ADC3xxxx EVM Connectors
Device Connector Description
J2 AINM – negative input for A, DNI J3 BINM – negative input for B, DNI J4 BINP – positive input for B, Ch2 single ended input J9 CLK_INP – positive CLK input, single ended clock input J10 CLK_INM – negative CLK input, DNI J11 SYSREF_INP – positive input for SYSREF frame clock, single ended input J12 SYSREF_INM – negative SYSREF input, DNI J13A, B HSMC data connector to TSW1400 evaluation platform J14 Mini USB connector for SPI control J15 Power connector for 5-V adapter
J2 AINM – negative input for A, DNI J3 BINM – negative input for B, DNI J4 BINP – positive input for B, Ch2 single ended input J5 CINP – positive input for C, Ch3 single ended input J6 CINM – negative input for C, DNI J7 DINM – negative input for D, DNI J8 DINP – positive input for D, Ch4 single ended input J9 CLK_INP – positive CLK input, single ended clock input J10 CLK_INM – negative CLK input, DNI J11 SYSREF_INP – positive input for SYSREF frame clock, single ended input J12 SYSREF_INM – negative SYSREF input, DNI J13A, B HSMC data connector to TSW1400 evaluation platform J14 Mini USB connector for SPI control J15 Power connector for 5-V adapter
ADC32J/34Jxx J1 AIN_CH-AP – positive input for CHA, single ended input (DNI for ADC32Jxx)
J2 AIN_CH-AM – negative input, (DNI for ADC32Jxx and ADC34Jxx) J3 BIN_CH-BP – positive input for CHB (CHA input for ADC32Jxx), single ended input J4 BIN_CH-BM – negative input for CHB (CHA input for ADC32Jxx and ADC34Jxx) J5 CIN_CH-CP – positive input for CHC (CHB input for ADC32Jxx), single ended input J6 CIN_CH-CM – negative input for CHC (CHB input for ADC32Jxx and ADC34Jxx) J7 DIN_CH-DP – positive input for CHD, single ended input (DNI for ADC32Jxx) J8 DIN_CH-DM – negative input, (DNI for ADC32Jxx and ADC34Jxx) J9 EXT_ADC_CLK – external ADC clock connection for ADC, if needed J23 EXT SYSREF+ - external SYSREF connection for ADC, if needed (positive input) J24 EXT SYSREF– - external SYSREF connection for ADC, if needed (negative input) J10 LMK_CLKIN – external input clock for LMK use, if needed (for clock distribution mode) J13 DCLKOUT6P – LMK output test point, positive J14 DCLKOUT6N – LMK output test point, negative J15 DCLKOUT7P – LMK output test point, positive J16 DCLKOUT7N – LMK output test point, positive J20 5-V input power jack J18 Mini USB connector for SPI GUI control J19 CPLD JTAG port
10
ADC3xxxEVM and ADC3xJxxEVM
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The onboard jumper options allow configuration of onboard power supplies and ADC options. Many of the jumper selections that involve dc inputs or static control signals are by way of push-on square post jumpers. The jumper options listed in Table 4 show the default settings of the jumpers for the EVM as normally shipped.
There is a pushbutton on the ADC3xxxx EVM – SW1. At power up, the ADC can either accept a hardware reset by pressing SW1 or toggling the software reset switch on the ADC3xxxx EVM GUI. The default reset configuration of the ADC is given in its respective data sheet.
LED D1 on the ADC32/34xxx is lit to show the presence of the 5-V supply voltage to the EVM. On the ADC32J/34Jxx EVMs, LED D8 is used to show the presence of the 5-V supply voltage to the EVM.
Table 5 lists the description of each LED indicator.
Introduction
Table 4. ADC3xxxx EVM Jumper Options
Device Jumper Description
ADC32xx/ADC34xx JP1 3 pin Jumper – 2-3 Default connection, 1-2 to enable PwDn function
JP2, J3, JP4,JP5 2 pin Jumper - SPI access points, if needed – default should be installed JP6, JP7 3 pin , default 1-2 to use 1.8V LDO. Use pins 2-3 to bypass 1.8-V LDO
ADC32J/34Jxx JP1 3 pin Jumper – 2-3 Default connection, 1-2 to enable PwDn function
JP2, J3, JP4,JP5 2 pin Jumper - SPI access points, if needed – default should be installed JP6 2 pin, default is connected for powering onboard VCXO SJP1 3 pin, DNI, optional for VCXO that require enable on pin 2 JP8 3 pin, default 2-3 for USB SPI selection through CPLD, 1-2 used for FMC
connector based SPI port JP9, JP10 3 pin, default 1-2 to use 1.8V LDO. Use pins 2-3 to bypass LDO JP12, JP13 3 pin, default 1-2 to use 3.3V LDO. Use pins 2-3 to bypass LDO
Table 5. ADC3xxxx EVM LED Indicators
Device LED Description
ADC32xx/ADC34xx D1 5-V power indicator ADC32J/34Jxx D1, D2 Status LED from CLKin SEL0/1 on LMK
D3, D4 Status LED used to indicate LMK Lock or PLL Lock D5 Status LED for JESD SYNC D6, D7 Spare LED indicators for FMC connector D8 5-V power indicator
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