TEXAS INSTRUMENTS ADC0803, ADC0805 Technical data

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D

8-Bit Resolution

D

Ratiometric Conversion

D

100-µs Conversion Time

D

135-ns Access Time

D

Guaranteed Monotonicity

D

High Reference Ladder Impedance
8 kΩ Typical

D

No Zero Adjust Requirement

D

On-Chip Clock Generator

D

Single 5-V Power Supply

D

Operates With Microprocessor or as
Stand-Alone

D

Designed to Be interchangeable With
National Semiconductor and Signetics
ADC0803 and ADC0805

description

ADC0803, ADC0805

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

N PACKAGE

(TOP VIEW)

CS
RD

WR

CLK IN

INTR

IN+
IN–

ANLG GND

REF/2

DGTL GND

1
2
3
4
5
6
7
8
9
10

V

20

CLK OUT

19

DB0 (LSB)

18

DB1

17

DB2

16

DB3

15

DB4

14

DB5

13

DB6

12

DB7 (MSB)

11

(OR REF)

CC

DATA
OUTPUTS

The ADC0803 and ADC0805 are CMOS 8-bit, successive-approximation, analog-to-digital converters that use
a modified potentiometric (256R) ladder. These devices are designed to operate from common microprocessor
control buses with the 3-state output latches driving the data bus. The devices can be made to appear to the
microprocessor as a memory location or an I/O port. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.

A differential analog voltage input allows increased common-mode rejection and offset of the zero-input analog
voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller analog
voltage spans or to make use of an external reference, ratiometric conversion is possible with the REF/2 input
open. Without an external reference, the conversion takes place over a span from V

to ANLG GND. The

CC

devices can operate with an external clock signal or with an additional resistor and capacitor, using an on-chip
clock generator.

The ADC0803C and ADC0805C are characterized for operation from 0°C to 70°C. The ADC0803I and
ADC0805I are characterized for operation from –40°C to 85°C.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1986, Texas Instruments Incorporated

1

ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

functional block diagram (positive logic)

2

RD

Start

Flip-Flop

CS

1

WR

CLK
OUT

CLK IN

DGTL

GND

V

CC

REF/2

ANLG

GND

IN +
IN –

3

19

4

10

20

9

8

6
7

SAR

Latch

LE

1D

C1R

CLK B

8-Bit
Shift

Register

D

Interrupt
Flip-Flop

R

R

R

5

1D

C1CLK A

S

INTR

S

CLK A

CLK A

Clk

CLK

Gen

Clk Osc

Ladder

and

Decoder

V

CC

DAC

CLK B

CLK

Σ

Comp

ENLE

3-State
Output

Latch

2

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18
17
16
15
14
13
12
11

DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)

Operating free–air temperature, T

°C

ADC0803, ADC0805

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range: CS,
Output voltage range –0.3 V to V

Operating free-air temperature range: ADC080_C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range – 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together unless otherwise

noted.

recommended operating conditions

Supply voltage, V
Analog input voltage (see Note 2) –0.05 VCC = 0.05 V
Voltage at REF/2 (see Note 3), V
High-level input voltage at CS, RD, or WR, V
Low-level input voltage at CS, RD, or WR, V
Analog ground voltage (see Note 4) –0.05 0 1 V
Clock iput frequency (see Note 5), f
Duty cycle for f
Pulse durartion, clock input (high or low) for f
Pulse durartion, WR input low, tW(WR) 100 ns

p

NOTES: 2. When the differential input voltage (VI+ – VI–) is less than or equal to 0 V, the output code is 0000 0000.

CC

above 640 kHz (see Note 5) 40% 60%

clock

p

3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when REF/2
is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs. Thus, the
differential input voltage range when REF/2 is open and VCC = 5 V is 0 V to 5 V . V
(full-scale differential voltage of 3 V) is 1.5 V.

4. These values are with respect to DGTL GND.

5. Total unadjusted error is specified only at an f
For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should be observed for
an f

greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided t

clock

RD, WR –0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other inputs –0.3 V to V

ADC080_I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIN NOM MAX UNIT

4.5 5 6.3 V

REF/2

clock

A

IH

IL

below 640 kHz, tW(CLK) 275 781 ns

clock

ADC080_C 0 70
ADC080_I –40 85

for an input voltage range from 0.5 V to 3.5 V

REF/2

of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns to 937 ns).

clock

0.25 2.5 V
2 15 V

100 640 1460 kHz

remains within limits.

w(CLK)

0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

0.8 V

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3

ADC0803, ADC0805

VOHHigh-level output voltage

V

IOZOff-state output current

A

Total adusted error

ADC0803

With full-scale adjust

See Notes 7 and 8

LSB

Total unadjusted error

ADC0805

LSB

t

Conversion cycle time

73

8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

electrical characteristics over recommended range of operating free-air temperature, VCC = 5 V,

= 640 kHz, V

f

clock

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

OL

V

T+

V

T–

VT+–VT–Clock input hysteresis 0.6 1.3 2 V
I

IH

I

IL

I

OHS

I

OLS

I

CC

R

REF/2

C

i

C

o

NOTE 6: Resistance is calculated from the current drawn from a 5-V supply applied to ANLG GND and REF/2.

Low-level output voltage INTR output VCC = 4.75 V, IOL = 1 mA 0.4 V

Clock positive-going threshold voltage 2.7 3.1 3.5 V
Clock negative-going threshold voltage 1.5 1.8 2.1 V

High-level input current 0.005 1 µA
Low-level input current –0.005 –1 µA

p

Short-current output current Output high VO = 0, TA = 25°C –4.5 –6 mA
Short-circuit output current Output low VO = 5 V, TA = 25°C 9 16 mA
Supply current plus reference current V
Input resistance to reference ladder See Note 6 2.5 8 kΩ
Input capacitance (control) 5 7.5 pF
Output capacitance (DB) 5 7.5 pF

= 2.5 V (unless otherwise noted)

REF/2

p

All outputs VCC = 4.75 V, IOH = –360 µA 2.4
DB and INTR VCC = 4.75 V, IOH = –10 µA 4.5
Data outputs VCC = 4.75 V, IOL = 1.6 mA 0.4

CLK OUT VCC = 4.75 V, IOL = 360 µA 0.4

VO = 0 –3
VO = 5 V 3

REF/2

µ

= open, TA = 25°C, CS = 5 V 1.1 1.8 mA

operating characteristics over recommended operating free-air temperature, VCC = 5 V,
V

t
t
t

CR Free-running conversion rate INTR connected to WR, CS at 0 V 66 8770 conv/s

†
NOTES: 7. These parameters are specified over the recommended analog input voltage range.

= 2.5 V, f

REF/2

Supply-voltage-variation error VCC = 4.5 to 5.5 V, See Note 7 +1/16 ±1/8 LSB

DC common-mode error See Notes 7 and 8 ±1/16 ±1/8 LSB

en
dis
d(INTR)

conv

All typical values are at TA = 25°C.

Output enable time TA = 25°C, CL = 100 pF 135 200 ns
Output disable time TA = 25°C, CL = 10 pF, RL = 10 kΩ 125 200 ns
Delay time to reset INTR TA = 25°C 300 450 nx

8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristics.

9. Although internal conversion is completed in 64 clock periods, a CS
before conversion starts. After conversion is complete, part of another clock period is required before a high-to-low transition of INTR
completes the cycle.

= 640 kHz (unless otherwise noted)

clock

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

,

V

= 2.5 V, See Notes 7 and 8 ±1/2

REF/2

V

open, See Notes 7 and 8 ±1

REF/2

f

= 100 kHz to 1.46 MHz,

clock

TA = 25°C, See Note 9

or WR low-to-high transition is followed by 1 to 8 clock periods

±1/4
±1/2

clock

cycles

4

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ADC0803, ADC0805

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

PARAMETER MEASUREMENT INFORMATION

CS

8 Clock Periods (Min)

RD

INTR

DATA

OUTPUTS

CS

WR

t

d(INTR)

50%

50%

t

d(INTR)

t

en

50%

50%

90%
10%

Figure 1. Read Operation Timing Diagram

50%50%

1 to 8
Clock Periods

t

w(WR)

50%

t

dis

High-Impedance State

64% Clock Periods

V

OH

V

OL

INTR

t

CONV

Figure 2. Write Operation Timing Diagram

50%50%

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5

ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

PRINCIPLES OF OPERATION

The ADC0803 and ADC0805 each contain a circuit equivalent to 256-resistor network. Analog switches are
sequenced by successive-approximation logic to match an analog differential input voltage (V
corresponding tap on the 256R network. The most significant bit (MSB) is tested first. After eight spelled out
comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is transferred to an output latch and
the interrupt (INTR
output to the write (WR) input and holding the conversion start (CS) input at a low level. To ensure start up under all
conditions, a low-level WR
a conversion in process.

) output goes low. The device can be operated in a free-running mode by connecting the INTR

input is required during the power-up cycle. T aking CS low any time after that will interrupt

– VI–) to a

I+

When WR
as both CS
after CS

When CS
pulse transfers a logic high to the output of the start flip-flop. The logic high is ANDed with the next clock pulse, placing
a logic high on the reset input of the start flip-flop. If either CS
is removed, causing it to be reset. A logic high is placed on the D input of the eight-bit shift register and the conversion
process is started. If CS
This action allows for wide CS
the inputs goes high.

When the logic high input has been clocked through the 8-bit shift register, which completes the SAR search, it is
applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next clock pulse, the digital
word is transferred to the 3-state output latches and the interrupt flip-flop is set. The output of the interrupt flip-flop
is inverted to provide an INTR

When a low is at both CS
reset. When either CS
high-impedance state). The interrupt flip-flop remains reset.

goes low, the internal successive-approximation register (SAR) and 8-bit shift register are reset. As long

and WR remain low, the analog-to-digital converter remains in a reset state. One to eight clock periods

or WR makes a low-to-high transition, conversion starts.

and WR are low, the start flip-flop is set and the interrupt flip-flop and 8-bit register are reset. The next clock

or WR have gone high, the set signal to the start flip-flop

and WR are still low, the start flip-flop, the 8-bit shift register, and the SAR remain reset.

and WR inputs, with conversion starting from one to eight clock periods after one of

output that is high during conversion and low when the conversion is complete.

and RD, an output is applied to the DB0 through DB7 outputs and the interrupt flip-flop is

or RD return to a high state, the DB0 through DB7 outputs are disabled (returned to the

6

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