TEXAS INSTRUMENTS 74HC 4015 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4015

Dual 4-bit serial-in/parallel-out shift
register

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift
register

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

propagation delay nCP to nQ

n

maximum clock frequency 110 74 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per register notes 1 and 2 35 40 pF

The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q
1Q3 and 2Q0 to 2Q3) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ0 to nQ
to LOW, independent of nCP and nD.

CL= 15 pF; VCC=5 V1618ns

74HC/HCT4015

TYPICAL

HC HCT

UNIT

to

0

3

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

5, 4, 3, 10 1Q
6, 14 1MR, 2MR asynchronous master reset inputs (active HIGH)
7, 15 1D, 2D serial data inputs
8 GND ground (0 V)
9, 1 1CP, 2CP clock inputs (LOW-to-HIGH, edge-triggered)
13, 12, 11, 2 2Q
16 V

0

0

CC

to 1Q

to 2Q

3

3

flip-flop outputs

flip-flop outputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

Fig.5 Logic diagram (one 4-bit

Fig.4 Functional diagram.

serial-in/parallel-out shift register).

FUNCTION TABLE

INPUTS OUTPUTS

n nCP nD nMR nQ

1
2
3
4

↑
↑
↑
↑

D
D
D
D

L

1
2
3
4

D

L

D

L

D

L

D
↓ X L no change
XXHLLLL

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don’t care

↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition

n = number of clock pulse transitions

= either HIGH or LOW

D

n

APPLICATIONS

• Serial-to-parallel converter

• Buffer stores

• General purpose register

nQ1nQ2nQ

0

X

1

D

2

1

D

3

2

D

4

3

3

X
X
D
D

X
X
X

1

D

2

1

December 1990 4

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

SYMBOL

/ t

t

PHL

PLH

t

PHL

t

/ t

THL

TLH

t

W

= 6 ns; CL= 50 pF

r=tf

PARAMETER

propagation delay

nCP to nQ

n

propagation delay

nMR to nQ

n

output transition time 19

clock pulse width

HIGH or LOW

t

W

master reset pulse
width HIGH

t

rem

removal time

nMR to nCP

t

su

set-up time

nD to nCP

t

h

hold time

nD to nCP

f

max

maximum clock pulse

frequency

(°C)

T

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

52

80
16
14

80
16
14

60
12
10

60
12
10

5
5
5

6.0
30
35

19
15

44
16
13

7
6

17
6
5

17
6
5

17
6
5

8
3
2

0
0
0

33
100
119

175
35
30

175
35
30

75
15
13

100
20
17

100
20
17

75
15
13

75
15
13

5
5
5

4.8
24
28

220
44
37

220
44
37

95
19
16

265
53
45

265
53
45

110
22
19

120
24
20

120
24
20

90
18
15

90
18
15

5
5
5

4.0
20
24

.

UNIT

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.7

4.5

6.0
Fig.8

4.5

6.0
Fig.8

4.5

6.0
Fig.6

4.5

6.0

December 1990 5

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

nD
nMR
nCP

0.30

1.50

1.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

T

(°C) TEST CONDITIONS

amb

74HCT

SYMBOL PARAMETER

+25 −40 to +85 −40

to +125

UNIT

V

(V)

CC

WAVEFORMS

t

PHL

t

PHL

t

THL

t

W

t

W

t

rem

t

su

t

h

f

max

min. typ. max. min. max. min. max.

/ t

/ t

propagation delay

PLH

nCP to nQ

n

propagation delay

nMR to nQ

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

n

clock pulse width

21 35 44 53 ns 4.5 Fig.6

18 35 44 53 ns 4.5 Fig.7

16 7 20 24 ns 4.5 Fig.6

HIGH or LOW

master reset pulse width

16 5 20 24 ns 4.5 Fig.7

HIGH

removal time

20 10 25 30 ns 4.5 Fig.7

nMR to nCP

set-up time

12 4 15 18 ns 4.5 Fig.8

nD to nCP

hold time

5 −2 5 5 ns 4.5 Fig.8

nD to nCP

maximum clock pulse

30 67 24 20 MHz 4.5 Fig.6

frequency

December 1990 6

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.6 Waveforms showing the clock (nCP) to output (nQn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the master reset (nMR) pulse width, the master reset to output (nQn) propagation

delay and the master reset to clock (nCP) removal time.

The shaded areas indicate when the input is permitted to
change for predictable output performance.

(1) HC : V

HCT: V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

M

Fig.8 Waveforms showing the data set-up and hold times for nD inputs.

December 1990 7

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 8