Texas Instruments CY74FCT16543TPVCT, CY74FCT16543TPVC, CY74FCT16543ETPVCT, CY74FCT16543ETPVC, CY74FCT16543ETPACT Datasheet
...
16-Bit Latched Transceivers
SCCS059 - August 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
Copyright © 2000, Texas Instruments Incorporated
Features
• FCT-E speed at 3.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
•V
CC
= 5V ± 10%
CY74FCT16543T Features:
• 64 mA sink current, 32 mA source current
• Typical V
OLP
(ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162543T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical V
OLP
(ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
CY74FCT162H543T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
The CY74FCT16543T and CY74FCT162543T are 16-bit,
high-speed,lowpowerlatchedtransceiv ersthatareorganizedastw o
independent 8-bit D-type latched transceivers containing two sets of
eight D-type latches with separate Latch Enable (
LEAB, LEAB) and
Output Enable (
OEAB, OEAB) controls for each set to permit
independent control of inputting and outputting in either direction of
data flow. For data flow from A to B, for example, the A-to-B input
Enable(
CEAB)must be LOW in orderto enter data fromA or totake
data from B as indicated in the truth table. With
CAEB LOW,a LOW
signal on the A-to-B Latch Enable (
LEAB) makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the
LEAB
signal puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With
CEAB and OEAB both LOW ,
thethree-stateBoutputbuffersareactiveand reflect thedatapresent
at the output of the A latches. Control of data from B to A is similar,
but uses
CEAB, LEAB, and OEAB inputs flow-through pinout and
small shrink packaging and in simplifying board design. The output
buffers are designed with a power-off disable feature to allow live
insertion of boards.
The CY74FCT16543T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162543T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162543T is ideal for driving transmission lines.
TheCY74FCT162H543T is a24-mAbalanced output part that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
2
Maximum Ratings
[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .....................Com’l −55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l −55°C to +125°C
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Logic Block Diagrams PinConfiguration
1
OEAB
SSOP/TSSOP
Top View
GND
V
CC
FCT16543T-1
FCT16543T-2
TO 7 OTHER CHANNELS
D
C
1B1
1
OEBA
1A1
1
CEBA
1
LEAB
1
OEAB
1
LEBA
1
CEAB
D
C
D
C
2B1
2
OEBA
2A1
2
CEBA
2
OEAB
2
LEBA
2
CEAB
1
LEAB
1
CEAB
1A1
V
CC
GND
2
LEAB
1A2
1A3
1A5
1A4
1A6
1A7
1A8
GND
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
GND
2
OEAB
2
CEAB
2
LEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
GND
V
CC
1
LEBA
1
CEBA
1B1
V
CC
GND
1B2
1B3
1B5
1B4
1B6
1B7
1B8
GND
2B1
2B2
2B3
2B4
2B6
2B7
2B8
GND
2
OEBA
2
CEBA
2
LEBA
2B5
D
C
FCT16543T-3
TO 7 OTHER CHANNELS
Pin Description
Name Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A A-to-BData Inputs orB-to-A Three-State Outputs
[9]
B B-to-AData Inputs orA-to-B Three-State Outputs
[9]
Function Table
[1]
Inputs
Latch
Status
Output
Buffers
CEAB LEAB OEAB A to B B
H X X Storing High Z
X H X Storing X
X X H X High Z
L L L Transparent Current A
Inputs
L H L Storing Previous A
Inputs
[2]
Operating Range
Range
Ambient
Temperature V
CC
Industrial −40°C to +85°C 5V ± 10%
CY74FCT16543T
CY74FCT162543T
CY74FCT162H543T
3
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Input Hysteresis
[6]
100 mV
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
I
IH
Input HIGH Current VCC=Max., VI=V
CC
±1 µA
I
IL
Input LOW Current VCC=Max., VI=GND ±1 µA
I
OZH
High Impedance Output Current (Three-State Output pins)
VCC=Max., V
OUT
=2.7V ±1 µA
I
OZL
High Impedance Output Current (Three-State Output pins)
VCC=Max., V
OUT
=0.5V ±1 µA
I
OS
Short Circuit Current
[7]
VCC=Max., V
OUT
=GND −80 −140 −200 mA
I
O
Output Drive Current
[7]
VCC=Max., V
OUT
=2.5V −50 −180 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
≤4.5V
[8]
±1 µA
Notes:
1. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA, and OEBA.
2. Data prior to LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level. L = LOW Voltage Level.
X = Don’t Care. Z = High Impedance.
3. Operation beyond the limits set forth may impair the useful lifeof the device.Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at V
CC
= 5.0V, TA= +25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accurately reflect operational values.Otherwiseprolongedshorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
8. Tested at +25˚C.
9. On the 74FCT162H543T, these pins have bus hold.
Loading...