Texas Instruments CY74FCT16652ETPVCT, CY74FCT16652ETPVC, CY74FCT16652ETPACT, CY74FCT16652ETPAC, CY74FCT16652CTPVCT Datasheet

16-Bit Registered Transceivers

CY74FCT16652T

CY74FCT162652T

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

SCCS061 - July 1994 - Revised March 2000

Copyright © 2000, Texas Instruments Incorporated

1CY74FCT162652T

Features

• FCT-E speed at 3.8 ns

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for significantly improved
noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages

• Industrial temperature range of −40˚C to +85˚C

•V

CC

= 5V ± 10%

CY74FCT16652T Features:

• 64 mA sink current, 32 mA source current

• Typical V

OLP

(ground bounce) <1.0V at VCC = 5V,

TA = 25˚C

CY74FCT162652T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

• Typical V

OLP

(ground bounce) <0.6V at VCC = 5V,

TA= 25˚C

Functional Description

These 16-bit, high-speed, low-power, registered transceivers
that are organized as two independent 8-bit bus transceivers
with three-stateD-type registers and control circuitry arranged
formultiplexed transmissionof data directlyfrom the inputbus
orfrom theinternal storageregisters.OEABand

OEBAcontrol
pinsare providedto controlthe transceiver functions.SAB and
SBA control pins are provided to select either real-time or
stored data transfer.

Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode,itis alsopossible tostore datawithout
using the internal D-type flip-flops by simultaneously enabling
OEAB and

OEBA. Inthis configuration,each outputreinforces
its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will
remain at its last state. Theoutput buffers are designed with a
power-off disable feature that allows live insertion of boards.

The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.

The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.

TO7 OTHER CHANNELS

1

OEAB

C

D

1A1

1

OEBA

1

CLKBA

1

CLKAB

1

SBA

B REG

C

D

A

REG

1B1

1

SAB

FCT16652-1

2

OEAB

2

SAB

2

OEBA

2

CLKBA

2

CLKAB

2

SBA

2B1

2A1

C

D

B

REG

C

D

A

REG

TO 7 OTHER CHANNELS

FCT16652-2

Logic Block Diagrams

CY74FCT16652T

CY74FCT162652T

2

Pin Configuration

SSOP/TSSOP

Top View

FCT16652–1

GND

1

OEAB

1

CLKAB

1

SAB

1A1
1A2

1

CLKBA

1

SBA

1B1

1

OEBA

GND

GND

V

CC

1A3

V

CC

GND

1A4
1A5

1A6
1A7
1A8
2A1
2A2

2A3

2A4

GND

2A5
2A6

V

CC
2A7
2A8

2

SAB

2

CLKAB

1
2

3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55

54
53

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

GND

2

OEAB

1B2

1B3
1B4
1B5

1B6
1B7
1B8
2B1
2B2
2B3

GND

2B4
2B5
2B6

V

CC
2B7
2B8

GND

2

SBA

2

CLKBA

2

OEBA

FCT16652-3

Pin Description

Name Description

A Data Register A Inputs

Data Register B Outputs

B Data Register B Inputs

Data Register A Outputs
CLKAB, CLKBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
OEAB, OEBA Output Enable Inputs

CY74FCT16652T

CY74FCT162652T

3

Function Table

[1]

Inputs Data I/O

[2]

Operation or FunctionOEAB OEBA CLKAB CLKBA SAB SBA A B

L
L

H
H

H or L H or L X

X

X
X

Input Input Isolation

Store A and B Data

X
H

H
H

H or L X

X

[3]

X
X

Input
Input

Unspecified

[2]

Output

Store A, Hold B
Store A in Both Registers

L
L

X

L

H or L X

X

X

X

[3]

Unspecified

[2]

Input
Input

Hold A, Store B
Store B in both Registers

L
L

L
L

X
X

X

H or L

X
X

L
H

Output Input Real Time B Data to A Bus

Stored B Data to A Bus

H
H

H
H

X

H or L

X
X

L
H

X
X

Input Output Real Time A Data to B Bus

Stored A Data to B Bus

H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

Notes:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

=LOW-to-HIGH Transition

2. The dataoutput functions maybe enabled ordisabled by various signals at theOEAB or

OEBA inputs. Datainput functions are always enabled, i.e.,data at

the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.

CY74FCT16652T

CY74FCT162652T

4

Maximum Ratings

[4]

(Above which the useful life may be impaired.For user guide­lines, not tested.)

Storage Temperature .....................Com’l −55°C to +125°C

Ambient Temperature with

Power Applied.................................Com’l −55°C to +125°C

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)...........................−60 to +120 mA

Power Dissipation..........................................................1.0W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Note:

4. Stresses greaterthan those listed underMaximum Ratings may cause permanentdamage to thedevice.This is astress rating only and functional operation of
the device at these or any otherconditions above those indicated in the operationalsections of thisspecification is notimplied. Exposure toabsolute maximum
rating conditions for extended periods may affect reliability.

BUS BBUS A

OEAB

L

OEBALCLKAB

X

SAB

X

BUS

BBUS A

OEAB

X
L
L

OEBA

H
X
H

CLKAB

X

SAB

X
X
X

SBA

X
X
X

BUS

BBUS A

OEAB

H

OEBA

L

SAB

L

SBA

X

BUS

ABUS A

OEAB

H

OEBA

L

SABHSBA

H

Real-Time Transfer

BusB to BusA

Real-TimeTransfer

BusA to BusB

Storagefrom

A and/or B

TransferStored Data

to A and/or B

CLKBA

X

CLKABXCLKBA

X

SBA

L

CLKBA

X

CLKAB

HorL

CLKBA

HorL

Operating Range

Range

Ambient

Temperature V

CC

Industrial −40°C to +85°C 5V ± 10%

CY74FCT16652T

CY74FCT162652T

5

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

[5]

Min. Typ.

[6]

Max. Unit

V

IH

Input HIGH Voltage Logic HIGH Level 2.0 V

V

IL

Input LOW Voltage Logic LOW Level 0.8 V

V

H

Input Hysteresis 100 mV

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

I

IH

Input HIGH Current VCC=Max., VI=V

CC

±1 µA

I

IL

Input LOW Current VCC=Max., VI=GND ±1 µA

I

OZH

High Impedance Output
Current
(Three-State Output pins)

VCC=Max., V

OUT

=2.7V ±1 µA

I

OZL

High Impedance Output
Current
(Three-State Output pins)

VCC=Max., V

OUT

=0.5V ±1 µA

I

OS

Short Circuit Current

[8]

VCC=Max., V

OUT

=GND −80 −140 −200 mA

I

O

Output Drive Current

[8]

VCC=Max., V

OUT

=2.5V −50 −180 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

≤4.5V

[7]

±1 µA

Output Drive Characteristics for CY74FCT16652T

Parameter Description Test Conditions

[5]

Min. Typ.

[6]

Max. Unit

V

OH

Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V

VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0

V

OL

Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V

Output Drive Characteristics for CY74FCT162652T

Parameter Description Test Conditions

[5]

Min. Typ.

[6]

Max. Unit

I

ODL

Output LOW Current

[8]

VCC=5V, VIN=VIH or VIL, V

OUT

=1.5V 60 115 150 mA

I

ODH

Output HIGH Current

[8]

VCC=5V, VIN=VIH or VIL, V

OUT

=1.5V −60 −115 −150 mA

V

OH

Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V

V

OL

Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V

Capacitance(T

A

= +25˚C, f = 1.0 MHz)

Parameter Description

[10]

Test Conditions Typ. Max. Unit

C

IN

Input Capacitance VIN = 0V 4.5 6.0 pF

C

OUT

Output Capacitance V

OUT

= 0V 5.5 8.0 pF

Notes:

5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

6. Typical values are at V

CC

=5.0V, +25°C ambient.

7. Tested at T

A

= +25°C.

8. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

9. Duration of the condition cannot exceed one second.

10. This parameter is measured at characterization but not tested.

CY74FCT16652T

CY74FCT162652T

6

Power Supply Characteristics

Param. Description Test Conditions

[11]

Min. Typ.

[12]

Max. Unit

I

CC

Quiescent Power Supply
Current

VCC=Max. VIN<0.2V

V

IN>VCC

−0.2V

— 5 500 µA

∆I

CC

Quiescent Power Supply
Current
TTL Inputs HIGH

VCC = Max. VIN=3.4V

[13]

— 0.5 1.5 mA

I

CCD

Dynamic Power Supply
Current

[14]

VCC=Max.
Outputs Open
OEAB=

OEAB=GND
One Input Toggling
50% Duty Cycle

VIN=VCCor
V

IN

=GND

— 75 120 µA/

MHz

I

C

Total Power Supply Current

[15]

VCC=Max.
Outputs Open
f

o

=10 MHz (CLKBA)
50% Duty Cycle
OEAB=

OEBA=GND
One-Bit Toggling
f

1

=5 MHz

50% Duty Cycle

VIN=VCCor
V

IN

=GND

— 0.8 1.7 mA

VIN=3.4V or
V

IN

=GND

— 1.3 3.2 mA

VCC=Max.
Outputs Open
f

o

=10 MHz (CLKBA)
50% Duty Cycle
OEAB=

OEBA=GND
Sixteen Bits Toggling
f

1

=2.5 MHz

50% Duty Cycle

VIN=VCCor
V

IN

=GND

— 3.8 6.5

[16]

mA

VIN=3.4V or
V

IN

=GND

— 8.3 20.0

[16]

mA

Notes:

11. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

12. Typical values are at V

CC

=5.0V +25° ambient.

13. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

15. I

C

=I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input(VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

16. Values for these conditions are examples of the I

CC

formula. These limits are specified but not tested.

CY74FCT16652T

CY74FCT162652T

7

Switching Characteristics Over the Operating Range

[17]

Parameter Description

CY74FCT16652AT

CY74FCT162652AT

UnitMin. Max. Fig. No.

[18]

t

PLH

t

PHL

Propagation Delay Bus to Bus 1.5 6.3 ns 1, 3

t

PZH

t

PHL

Output Enable Time OEAB or OEBA to Bus 1.5 9.8 ns 1, 7, 8

t

PHZ

t

PLZ

Output Disable Time OEAB or OEBA to Bus 1.5 6.3 ns 1, 7, 8

t

PLH

t

PHL

Propagation Delay Clock to Bus 1.5 6.3 ns 1, 5

t

PLH

t

PHL

Propagation Delay SBA or SAB to Bus 1.5 7.7 ns 1, 5

t

SU

Set-Up time HIGH or LOW Bus to Clock 2.0 — ns 4

t

H

Hold Time HIGH or LOW Bus to Clock 1.5 — ns 4

t

W

Clock Pulse Width HIGH or LOW 5.0 — ns 5

t

SK(O)

Output Skew

[19]

— 0.5 ns

Parameter Description

CY74FCT16652CT

CY74FCT162652CT

CY74FCT16652ET

CY74FCT162652ET

UnitMin. Max. Min. Max. Fig. No.

[18]

t

PLH

t

PHL

Propagation Delay
Bus to Bus

1.5 5.4 1.5 3.8 ns 1, 3

t

PZH

t

PHL

Output Enable Time
OEAB or

OEBA to Bus

1.5 7.8 1.5 4.8 ns 1, 7, 8

t

PHZ

t

PLZ

Output Disable Time
OEAB or

OEBA to Bus

1.5 6.3 1.5 4.0 ns 1, 7, 8

t

PLH

t

PHL

Propagation Delay
Clock to Bus

1.5 5.7 1.5 3.8 ns 1, 5

t

PLH

t

PHL

Propagation Delay
SBA or SAB to Bus

1.5 6.2 1.5 4.2 ns 1, 5

t

SU

Set-Up Time
HIGH or LOW
Bus to Clock

2.0 — 2.0 — ns 4

t

H

Hold Time
HIGH or LOW
Bus to Clock

1.5 — 0.0 — ns 4

t

W

Clock Pulse Width
HIGH or LOW

5.0 — 3.0 — ns 5

t

SK(O)

Output Skew

[19]

— 0.5 — 0.5 ns

Notes:

17. Minimum limits are specified, but not tested, on propagation delays.

18. See “Parameter Measurement Information” in the General Information section.

19. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.

CY74FCT16652T

CY74FCT162652T

8

Ordering Information CY74FCT16652

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

3.8 CY74FCT16652ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16652ETPVC/PVCT O56 56-Lead (300-Mil) SSOP

5.4 CY74FCT16652CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

6.3 CY74FCT16652ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

Ordering Information CY74FCT162652

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

3.8 74FCT162652ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162652ETPVC O56 56-Lead (300-Mil) SSOP
74FCT162652ETPVCT O56 56-Lead (300-Mil) SSOP

5.4 74FCT162652CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162652CTPVC O56 56-Lead (300-Mil) SSOP
74FCT162652CTPVCT O56 56-Lead (300-Mil) SSOP

6.3 CY74FCT162652ATPVC O56 56-Lead (300-Mil) SSOP Industrial
74FCT162652ATPVCT O56 56-Lead (300-Mil) SSOP

CY74FCT16652T

CY74FCT162652T

9

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin ShrunkSmall Outline Package

Z56

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Copyright  2000, Texas Instruments Incorporated