Texas Instruments CY74FCT16652ETPVCT, CY74FCT16652ETPVC, CY74FCT16652ETPACT, CY74FCT16652ETPAC, CY74FCT16652CTPVCT Datasheet
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16-Bit Registered Transceivers
CY74FCT16652T
CY74FCT162652T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
SCCS061 - July 1994 - Revised March 2000
Copyright © 2000, Texas Instruments Incorporated
1CY74FCT162652T
Features
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
•V
CC
= 5V ± 10%
CY74FCT16652T Features:
• 64 mA sink current, 32 mA source current
• Typical V
OLP
(ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162652T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical V
OLP
(ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
Functional Description
These 16-bit, high-speed, low-power, registered transceivers
that are organized as two independent 8-bit bus transceivers
with three-stateD-type registers and control circuitry arranged
formultiplexed transmissionof data directlyfrom the inputbus
orfrom theinternal storageregisters.OEABand
OEBAcontrol
pinsare providedto controlthe transceiver functions.SAB and
SBA control pins are provided to select either real-time or
stored data transfer.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode,itis alsopossible tostore datawithout
using the internal D-type flip-flops by simultaneously enabling
OEAB and
OEBA. Inthis configuration,each outputreinforces
its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will
remain at its last state. Theoutput buffers are designed with a
power-off disable feature that allows live insertion of boards.
The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
TO7 OTHER CHANNELS
1
OEAB
C
D
1A1
1
OEBA
1
CLKBA
1
CLKAB
1
SBA
B REG
C
D
A
REG
1B1
1
SAB
FCT16652-1
2
OEAB
2
SAB
2
OEBA
2
CLKBA
2
CLKAB
2
SBA
2B1
2A1
C
D
B
REG
C
D
A
REG
TO 7 OTHER CHANNELS
FCT16652-2
Logic Block Diagrams
CY74FCT16652T
CY74FCT162652T
2
Pin Configuration
SSOP/TSSOP
Top View
FCT16652–1
GND
1
OEAB
1
CLKAB
1
SAB
1A1
1A2
1
CLKBA
1
SBA
1B1
1
OEBA
GND
GND
V
CC
1A3
V
CC
GND
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
GND
2A5
2A6
V
CC
2A7
2A8
2
SAB
2
CLKAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
2
OEAB
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2
SBA
2
CLKBA
2
OEBA
FCT16652-3
Pin Description
Name Description
A Data Register A Inputs
Data Register B Outputs
B Data Register B Inputs
Data Register A Outputs
CLKAB, CLKBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
OEAB, OEBA Output Enable Inputs
CY74FCT16652T
CY74FCT162652T
3
Function Table
[1]
Inputs Data I/O
[2]
Operation or FunctionOEAB OEBA CLKAB CLKBA SAB SBA A B
L
L
H
H
H or L H or L X
X
X
X
Input Input Isolation
Store A and B Data
X
H
H
H
H or L X
X
[3]
X
X
Input
Input
Unspecified
[2]
Output
Store A, Hold B
Store A in Both Registers
L
L
X
L
H or L X
X
X
X
[3]
Unspecified
[2]
Input
Input
Hold A, Store B
Store B in both Registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output Input Real Time B Data to A Bus
Stored B Data to A Bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input Output Real Time A Data to B Bus
Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
=LOW-to-HIGH Transition
2. The dataoutput functions maybe enabled ordisabled by various signals at theOEAB or
OEBA inputs. Datainput functions are always enabled, i.e.,data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.
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