TEXAS INSTRUMENTS 54ACT16861, 74ACT16861 Technical data

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54ACT16861, 74ACT16861
20-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996
D
Widebus
D
Inputs Are TTL-Voltage Compatible
D
3-State Outputs Drive Bus Lines Directly
D
Flow-Through Architecture Optimizes
Family
PCB Layout
D
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at 125°C
D
Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
description
The ’ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
The ’ACT16861 can be used as two 10-bit transceivers or one 20-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (OEAB inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.
or OEBA)
54ACT16861 . . . WD PACKAGE
74ACT16861 . . . DL PACKAGE
1OEAB
2OEAB
1B1 1B2
GND
1B3 1B4
V
CC
1B5 1B6 1B7
GND
1B8 1B9
1B10
2B1 2B2 2B3
GND
2B4 2B5 2B6
V
CC
2B7 2B8
GND
2B9
2B10
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA 1A1 1A2 GND 1A3 1A4 V
CC
1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 V
CC
2A7 2A8 GND 2A9 2A10 2OEBA
The 74ACT16861 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16861 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16861 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
54ACT16861, 74ACT16861
OPERATION
20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996
FUNCTION TABLE
(each 10-bit section)
INPUTS
OEAB
OEBA
L L
L H A to B H L B to A H H Isolation
Latch A and B
(A = B)
logic symbol
1OEBA 1OEAB 2OEBA 2OEAB
1A1
1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9
1A10
2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9
2A10
56 1 29 28
55
54 52 51 49 48 47 45 44 43 42
41 40 38 37 36 34 33 31 30
EN1 EN2 EN3 EN4
11
31
1 2
14
10 12 13 14 15
16 17 19 20 21 23 24 26 27
2
1B1
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6 1B7 1B8 1B9 1B10 2B1
2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
logic diagram (positive logic)
54ACT16861, 74ACT16861
20-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996
1OEBA
1OEAB
1A1
56
1
To Nine Other Channels
2OEBA
2OEAB
255
1B1
2A1
29
28
To Nine Other Channels
1542
2B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
54ACT16861 74ACT16861
MIN NOM MAX MIN NOM MAX
V V V V V I
OH
I
OL
t/v Input transition rise or fall rate 0 10 0 10 ns/V T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
CC CC
0 V 0 V
CC CC
V V
3
54ACT16861, 74ACT16861
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
PARAMETER
UNIT
A or B
B or A
ns
OEBA
OEAB
A or B
ns
OEBA
OEAB
A or B
ns
CpdPower dissipation capacitance per transceiver
C
50 pF
f
pF
20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
= –50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC I C
C
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
A or B ports VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
§
CC
Control inputs VI = VCC or GND 5 V 4.5 pF
i
A or B ports VO = VCC or GND 5 V 17 pF
io
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA One input at 3.4 V ,
Other inputs at VCC or GND
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16861 74ACT16861
MIN TYP MAX MIN MAX MIN MAX
V
V
switching characteristics over recommended operating free-air temperature range, V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT16861 74ACT16861
MIN TYP MAX MIN MAX MIN MAX
3.1 6.5 9.2 3.1 10.4 3.1 10.4
2.9 7.5 10 2.9 11.1 2.9 11.1
2.4 6.6 9 2.4 10 2.4 10
3.7 8.5 11.5 3.7 12.7 3.7 12.7
4.9 7.4 9.8 4.9 10.7 4.9 10.7
4.5 6.9 9.3 4.5 10 4.5 10
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
or
or
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled Outputs disabled
p
,
=
L
= 1 MHz
64 14
p
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
Input
CL = 50 pF
(see Note A)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
500
LOAD CIRCUIT
t
w
54ACT16861, 74ACT16861
20-BIT BUS TRANSCEIVERS
SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
500
S1
CC
Open
GND
Timing Input
3 V
Data Input
0 V
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V
VOLTAGE WAVEFORMS
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
1.5 V
t
h
1.5 V
3 V
0 V
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control (low-level enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
CC
CC
1.5 V
20% V
80% V
1.5 V
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
74ACT16861DL ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br)
74ACT16861DLR ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
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Addendum-Page 1
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