54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B – JANUARY 1991 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Provide Extra Data Width Necessary for
Family
Wider Address/Data Paths or Buses With
Parity
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The ’ACT16825 18-bit buffers/drivers are
designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.
The ’ACT16825 can be used as two 9-bit buffers
or one 18-bit buffer. They provide true data from
A to Y.
The 3-state control gate is a 2-input NOR gate;
therefore, if either output-enable (OE1 or OE2)
input is high, all nine affected outputs are in the
high-impedance state.
54ACT16825 . . . DW PACKAGE
74ACT16825 . . . DL PACKAGE
1OE1
2OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
V
CC
2Y6
2Y7
GND
2Y8
2Y9
(TOP VIEW)
56
1
55
2
54
3
53
4
52
5
51
6
50
7
49
8
48
9
47
10
46
11
45
12
44
13
43
14
42
15
41
16
40
17
39
18
38
19
37
20
36
21
35
22
34
23
33
24
32
25
31
26
30
27
29
28
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OE2
The 74ACT16825 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16825 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16825 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OE2 A
OE1
L L L L
L LH H
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
Y
Copyright 1996, Texas Instruments Incorporated
1
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B – JANUARY 1991 – REVISED APRIL 1996
logic symbol
†
1OE1
1OE2
2OE1
2OE2
1
56
28
29
55
1A1 1Y1
54
1A2 1Y2
52
1A3 1Y3
51
1A4
49
1A5
48
1A6
47
1A7
45
1A8
44
1A9 1Y9
41
2A1 2Y1
40
2A2
38
2A2 2Y3
37
2A3 2Y4
36
2A4 2Y5
34
2A5 2Y6
33
2A6 2Y7
31
2A7
30
2A8 2Y9
&
EN1
&
EN2
10
12
13
16
17
19
20
21
23
24
26
27
2
3
5
6
1Y4
8
1Y5
9
1Y6
1Y7
1Y8
2Y2
2Y8
1
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE1
1OE2
1A1
1
56
55
To Eight Other Channels
2
1Y1
2OE1
2OE2
2A1
28
29
41
To Eight Other Channels
16
2Y1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B – JANUARY 1991 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±450 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
54ACT16825 74ACT16825
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
CC
0 V
0 V
CC
CC
V
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54ACT16825, 74ACT16825
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
PARAMETER
UNIT
A
Y
ns
OE
Y
ns
OE
Y
ns
CpdPower dissipation capacitance
C
f
pF
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B – JANUARY 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC
‡
∆I
CC
C
i
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
o
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
One input at 3.4 V ,
Other inputs at VCC or GND
VI = VCC or GND 5 V 4 pF
VO = VCC or GND 5 V 16 pF
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16825 74ACT16825
MIN TYP MAX MIN MAX MIN MAX
V
V
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT16825 74ACT16825
MIN TYP MAX MIN MAX MIN MAX
4.1 7.5 9.3 4.1 10.5 4.1 10.5
3.1 7.5 9.6 3.1 10.3 3.1 10.3
3.3 7.9 9.9 3.3 11 3.3 11
4.1 9.5 12.1 4.1 13.2 4.1 13.2
5.7 9 10.8 5.7 11.5 5.7 11.5
5.5 8.5 10 5.5 10.6 5.5 10.6
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
Outputs enabled
Outputs disabled
= 50 pF,
L
p
= 1 MHz
42
12
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
500 Ω
500 Ω
LOAD CIRCUIT
S1
Open
GND
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B – JANUARY 1991 – REVISED APRIL 1996
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
1.5 V
50% V
PZH
50% V
VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
CC
CC
1.5 V
20% V
80% V
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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Copyright 1998, Texas Instruments Incorporated
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