Texas Instruments 74ACT16657DLR, 74ACT16657DL Datasheet

54ACT16657, 74ACT16657

16-BIT TRANSCEIVERS

WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SCAS164A – JANUARY 1991 – REVISED APRIL 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

Inputs Are TTL-Voltage Compatible

D

Flow-Through Architecture Optimizes
PCB Layout

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

500-mA Typical Latch-Up Immunity at
125°C

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings

description

The ’ACT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R

or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE

or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.

Odd or even parity is selected by a logic high or
low level, respectively, on the 1ODD/EVEN (or
2ODD/EVEN) input. 1PARITY (or 2PARITY)
carries the parity bit value; it is an output from the
parity generator/checker in the transmit mode and
an input to the parity generator/checker in the
receive mode.

In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2P ARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN

(or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1P ARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.

Copyright  1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

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23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE

NC

1ERR

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

2ERR

NC

2OE

1T/R
1ODD/EVEN
1PARITY
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2PARITY
2ODD/EVEN
2T/R

54ACT16657 . . . WD PACKAGE

74ACT16657 . . . DL PACKAGE

(TOP VIEW)

NC – No internal connection

54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SCAS164A – JANUARY 1991 – REVISED APRIL 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR)
output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example,
if 1ODD/EVEN

is high (odd parity selected), 1P ARITY is high, and there are three high bits on the 1B bus, then

1ERR is low, indicating a parity error.
The 74ACT16657 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and

functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16657 is characterized for operation over the full military temperature range of –55°C to 125°C. The

74ACT16657 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

NUMBER OF A OR B

INPUTS

INPUT/OUTPUT

OUTPUTS

NUMBER OF A OR B

INPUTS THAT ARE HIGH

OE

T/R

ODD/EVEN

INPUT/OUTPUT

PARITY

ERR

OUTPUT MODE

L H H H Z Transmit
L HL L Z Transmit
L LH H H Receive

0, 2, 4, 6, 8

L LH L L Receive
L LL H L Receive
L LL L H Receive
L H H L Z Transmit
L HL H Z Transmit
L LH H L Receive

1, 3, 5, 7

L LH L H Receive
L LL H H Receive
L LL L L Receive

Don’t care H X X Z Z Z

54ACT16657, 74ACT16657

16-BIT TRANSCEIVERS

WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SCAS164A – JANUARY 1991 – REVISED APRIL 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

1A2

6

1A3

8

1A4

9

1A5

10

1A6

12

1A7

13

1A8

14

2A2

16

2A3

17

2A4

19

2A5

20

2A6

21

2A7

23

2A8

24

1OE

1A1

5

Z11

G3

1

3 EN1/3G5 [REC]

56

3 EN2 [XMIT]
N4

55

G8

28

8 EN6/8G10 [REC]

29

8 EN7 [XMIT]
N9

30

1B1

52

1B2

51

1B3

49

1B4

48

1B5

47

1B6

45

1B7

44

1B8

43

1PARITY

54

5

3

1T/R

1ODD/EVEN

2OE

2T/R

2ODD/EVEN

1ERR

1

2

11

18

2k

4

, 2

4

, 1

2A1

15

Z21

2B1

42

2B2

41

2B3

40

2B4

38

2B5

37

2B6

36

2B7

34

2B8

33

2PARITY

31

10

26

21

•

•

•

28

2ERR

6

7

2k

9

, 7

9, 6

1

1

1

1

•

•

•

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.