Texas Instruments 74ACT16652DLR, 74ACT16652DL Datasheet
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Independent Registers and Enables for A
Family
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The ’ACT16652 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and
OEBA
) inputs are provided to control the
transceiver functions. Select-control (SAB and
SBA) inputs are provided to select whether
real-time or stored data is transferred. A low input
level selects real-time data, and a high input level
selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
’ACT16652.
54ACT16652 . . . WD PACAGE
74ACT16652 . . . DL PACKAGE
1OEAB
1CLKAB
1SAB
2SAB
2CLKAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
54ACT16652, 74ACT16652
OPERATION OR FUNCTION
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
The 74ACT16652 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB
†
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
OEBA
L H L L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ L X X Input Unspecified
H H ↑↑X
L X L ↑ X X Unspecified
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H L X H X Input Output Stored A data to B bus
H L L L H H Output Output
CLKAB CLKBA SAB SBA A1–A8 B1–B8
‡
X Input Output Store A in both registers
DATA I/O
‡
†
. In this configuration, each output
‡
Input Hold A, store B
Store A, hold B
Stored A data to B bus and
stored B data to A bus
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
BUS A
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS A
OEAB OEBA
HH
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
OEAB
X
L
L
BUS A
CLKAB CLKBAXSABXSBA
OEBA
H
X
H
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
OEAB OEBA
X
X
X
X
HL L HH
BUS A
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
BUS B
CLKAB CLKBA SAB SBA
L
TO A AND/OR B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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