Texas Instruments 74ACT16652DLR, 74ACT16652DL Datasheet

54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
D
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Independent Registers and Enables for A
Family
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes PCB Layout
D
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at 125°C
D
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Spacings
description
The ’ACT16652 are 16-bit bus transceivers consisting of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The devices can be used as two 8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and OEBA
) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’ACT16652.
54ACT16652 . . . WD PACAGE
74ACT16652 . . . DL PACKAGE
1OEAB
1CLKAB
1SAB
2SAB
2CLKAB
2OEAB
GND
1A1 1A2
V
CC
1A3 1A4 1A5
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
2A4 2A5 2A6
V
CC
2A7 2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA 1CLKBA 1SBA GND 1B1 1B2 V
CC
1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 V
CC
2B7 2B8 GND 2SBA 2CLKBA 2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  1996, Texas Instruments Incorporated
1
54ACT16652, 74ACT16652
OPERATION OR FUNCTION
16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The 74ACT16652 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers.
OEBA
L H L L X X Input Input Isolation L H ↑↑X X Input Input Store A and B data X H L X X Input Unspecified
H H ↑↑X
L X L X X Unspecified L L ↑↑XX‡Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus
L L X L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H L X H X Input Output Stored A data to B bus
H L L L H H Output Output
CLKAB CLKBA SAB SBA A1–A8 B1–B8
X Input Output Store A in both registers
DATA I/O
. In this configuration, each output
Input Hold A, store B
Store A, hold B
Stored A data to B bus and
stored B data to A bus
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54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
BUS A
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS A
OEAB OEBA
HH
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
OEAB
X L L
BUS A
CLKAB CLKBAXSABXSBA
OEBA
H
X
H
XX
STORAGE FROM
A, B, OR A AND B
↑ ↑
BUS B
OEAB OEBA X X
X
X
HL L HH
BUS A
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
BUS B
CLKAB CLKBA SAB SBA
L
TO A AND/OR B
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3
54ACT16652, 74ACT16652 16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
logic symbol
1OEBA 1OEAB
1CLKBA
1SBA
1CLKAB
1SAB 2OEBA 2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
1A1
1A2 1A3 1A4 1A5 1A6 1A7 1A8
2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
56 1 55 54 2 3 29 28 30 31 27 26
5
6 8 9 10 12 13 14
15
16 17 19 20 21 23 24
EN1 [BA] EN2 [AB]
C3
G4
C5 G6 EN7 [BA] EN8 [AB]
C9 G10
C11 G12
1
1
5D
16
1
7
11D
12
112
52
51 49 48 47 45 44 43 42
41 40 38 37 36 34 33
1B1
1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1
2B2 2B3 2B4 2B5 2B6 2B7 2B8
3D
441
1
6
2
10
9D
1
10
1
8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
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logic diagram (positive logic)
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
2OEBA
56
1 55
54 2 3
5
29
1D
C1
TG
TG
TG
TG
To Seven Other Channels
C1
1D
52
1B1
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
28 30 31 27 26
15
1D
C1
TG
TG
TG
TG
To Seven Other Channels
C1
1D
42
2B1
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5
54ACT16652, 74ACT16652
UNIT
16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
54ACT16652 74ACT16652
MIN NOM MAX MIN NOM MAX
V V V V V I
OH
I
OL
t/v Input transition rise or fall rate 0 10 0 10 ns/V T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC CC
0 V 0 V
CC CC
V V
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
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PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
UNIT
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
= –50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC I C
C
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
A or B ports VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
§
CC
Control inputs VI = VCC or GND 5 V 4 pF
i
A or B ports VO = VCC or GND 5 V 12 pF
io
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA One input at 3.4 V ,
Other inputs at VCC or GND
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16652 74ACT16652
MIN TYP MAX MIN MAX MIN MAX
V
V
timing requirements over recommended operating free-air temperature range, V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT16652 74ACT16652 MIN MAX MIN MAX MIN MAX
f
clock t
w t
su t
h
Clock frequency 0 90 0 90 0 90 MHz Pulse duration, CLKAB or CLKBA high or low 5.5 5.5 5.5 ns Setup time, A before CLKAB or B before CLKBA 4.5 4.5 4.5 ns Hold time, A after CLKAB or B after CLKBA 1 1 1 ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
54ACT16652, 74ACT16652
PARAMETER
UNIT
A or B
B or A
ns
CLKBA or CLKAB
A or B
ns
A or B
ns
A or B
ns
OEBA
A
ns
OEBA
A
ns
OEAB
B
ns
OEAB
B
ns
CpdPower dissipation capacitance per transceiver
C
50 pF
f
pF
16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
TA = 25°C 54ACT16652 74ACT16652
MIN TYP MAX MIN MAX MIN MAX
90 90 90 MHz
3.7 7.2 9.4 3.7 10.5 3.7 10.5 3 8.1 10.5 3 11.6 3 11.6
4.5 8.7 11.2 4.5 12.3 4.5 12.3
4.9 8.9 11.3 4.9 12.3 4.9 12.3
4.9 10.4 14.1 4.9 16 4.9 16
4.6 8.4 10.6 4.6 11.7 4.6 11.7
3.9 7.8 10 3.9 11.2 3.9 11.2
5.6 12.3 14.9 5.6 16.9 5.6 16.9 3 8.1 10.5 3 11.7 3 11.7
3.9 9.4 12 3.9 13.4 3.9 13.4
5.3 7.4 8.9 5.3 9.5 5.3 9.5
4.8 6.8 8.6 4.8 9.2 4.8 9.2
4.1 7.7 9.8 4.1 10.8 4.1 10.8 5 9 11 5 12.4 5 12.4
4.4 8.1 10.1 4.4 10.5 4.4 10.5
4.3 7.7 9.7 4.3 9.9 4.3 9.9
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
SBA or SAB
(with A or B high)
SBA or SAB
(with A or B low)
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled Outputs disabled
p
,
=
L
= 1 MHz
57 13
p
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Input
Under Test
CL = 50 pF
(see Note A)
1.5 V 1.5 V
PARAMETER MEASUREMENT INFORMATION
500
500
LOAD CIRCUIT
t
w
VOLTAGE WAVEFORMS
S1
3 V
0 V
2 × V
Open
GND
CC
Timing Input
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
TEST S1
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
Open
2 × V
GND
t
1.5 V
CC
3 V
0 V
h
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control (low-level enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
1.5 V
50% V
PZH
50% V
VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
CC
CC
1.5 V
20% V
80% V
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
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9
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Copyright 1998, Texas Instruments Incorporated
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