Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The ’ACT16652 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and
OEBA
) inputs are provided to control the
transceiver functions. Select-control (SAB and
SBA) inputs are provided to select whether
real-time or stored data is transferred. A low input
level selects real-time data, and a high input level
selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
’ACT16652.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
54ACT16652, 74ACT16652
OPERATION OR FUNCTION
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
The 74ACT16652 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB
†
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
OEBA
LHLLXXInputInputIsolation
LH↑↑XXInputInputStore A and B data
XH↑LXXInputUnspecified
HH↑↑X
LXL↑XXUnspecified
LL↑↑XX‡OutputInputStore B in both registers
LLXXXLOutputInputReal-time B data to A bus
LLXLXHOutputInputStored B data to A bus
HHXXLXInputOutputReal-time A data to B bus
HHLXHXInputOutputStored A data to B bus
HLLLHHOutputOutput
CLKABCLKBASABSBAA1–A8B1–B8
‡
XInputOutputStore A in both registers
DATA I/O
‡
†
. In this configuration, each output
‡
InputHold A, store B
Store A, hold B
Stored A data to B bus and
stored B data to A bus
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
BUS A
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS A
OEAB OEBA
HH
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
OEAB
X
L
L
BUS A
CLKAB CLKBAXSABXSBA
OEBA
H
X
H
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
OEAB OEBA
X
X
X
X
HL LHH
BUS A
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
BUS B
CLKAB CLKBA SABSBA
L
TO A AND/OR B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
logic symbol
†
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN1 [BA]
EN2 [AB]
C3
G4
C5
G6
EN7 [BA]
EN8 [AB]
C9
G10
C11
G12
≥ 1
1
5D
16
≥ 1
7
11D
12
112
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
3D
441
≥ 1
6
2
10
9D
1
10
≥ 1
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
2OEBA
56
1
55
54
2
3
5
29
1D
C1
TG
TG
TG
TG
To Seven Other Channels
C1
1D
52
1B1
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
28
30
31
27
26
15
1D
C1
TG
TG
TG
TG
To Seven Other Channels
C1
1D
42
2B1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
54ACT16652, 74ACT16652
UNIT
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
UNIT
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC
∆I
C
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputsVI = VCC or GND5.5 V±0.1±1±1µA
‡
A or B portsVO = VCC or GND5.5 V±0.5±5±5µA
§
CC
Control inputsVI = VCC or GND5 V4pF
i
A or B portsVO = VCC or GND5 V12pF
io
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND,IO = 05.5 V88080µA
One input at 3.4 V ,
Other inputs at VCC or GND
†
†
4.5 V4.44.44.4
5.5 V5.45.45.4
4.5 V3.943.83.8
5.5 V4.944.84.8
5.5 V3.853.85
4.5 V0.10.10.1
5.5 V0.10.10.1
4.5 V0.360.440.44
5.5 V0.360.440.44
5.5 V1.651.65
5.5 V0.911mA
TA = 25°C54ACT1665274ACT16652
MINTYPMAXMINMAXMINMAX
V
V
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C54ACT1665274ACT16652
MINMAXMINMAXMINMAX
f
clock
t
w
t
su
t
h
Clock frequency090090090MHz
Pulse duration, CLKAB or CLKBA high or low5.55.55.5ns
Setup time, A before CLKAB↑ or B before CLKBA↑4.54.54.5ns
Hold time, A after CLKAB↑ or B after CLKBA↑111ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
54ACT16652, 74ACT16652
PARAMETER
UNIT
A or B
B or A
ns
CLKBA or CLKAB
A or B
ns
A or B
ns
A or B
ns
OEBA
A
ns
OEBA
A
ns
OEAB
B
ns
OEAB
B
ns
CpdPower dissipation capacitance per transceiver
C
50 pF
f
pF
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
TA = 25°C54ACT1665274ACT16652
MINTYPMAXMINMAXMINMAX
909090MHz
3.77.29.43.710.53.710.5
38.110.5311.6311.6
4.58.711.24.512.34.512.3
4.98.911.34.912.34.912.3
4.910.414.14.9164.916
4.68.410.64.611.74.611.7
3.97.8103.911.23.911.2
5.612.314.95.616.95.616.9
38.110.5311.7311.7
3.99.4123.913.43.913.4
5.37.48.95.39.55.39.5
4.86.88.64.89.24.89.2
4.17.79.84.110.84.110.8
5911512.4512.4
4.48.110.14.410.54.410.5
4.37.79.74.39.94.39.9
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
FROMTO
(INPUT)(OUTPUT)
SBA or SAB
(with A or B high)
SBA or SAB
(with A or B low)
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETERTEST CONDITIONSTYPUNIT
p
p
p
Outputs enabled
Outputs disabled
p
,
=
L
= 1 MHz
57
13
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Input
Under Test
CL = 50 pF
(see Note A)
1.5 V1.5 V
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
LOAD CIRCUIT
t
w
VOLTAGE WAVEFORMS
S1
3 V
0 V
2 × V
Open
GND
CC
Timing Input
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
TESTS1
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
Open
2 × V
GND
t
1.5 V
CC
3 V
0 V
h
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
1.5 V
50% V
PZH
50% V
VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
CC
CC
1.5 V
20% V
80% V
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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