54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
3-State True Outputs
D
Flow-Through Architecture Optimizes
Family
PCB Layout
D
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings, and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16543 are 16-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction. The ’ACT16543 can be used as two
8-bit transceivers or one 16-bit transceiver.
Separate latch enable (LEAB
output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
or LEBA) and
54ACT16543 . . . WD PACKAGE
74ACT16543 . . . DGG OR DL PACKAGE
1OEAB
1LEAB
1CEAB
2CEAB
2LEAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB) and OEAB inputs must
be low to enter data from A or to output data to B.
Having CEAB low and LEAB low makes the
A-to-B latches transparent; a subsequent low-tohigh transition at LEAB
puts the A latches in the
storage mode. Data flow from B to A is similar, but
requires using the CEBA, LEBA, and OEBA
inputs.
The 74ACT16543 is packaged in TI’s shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16543 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
54ACT16543, 74ACT16543
STATUS
BUFFERS
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
INPUTS
CEAB LEAB OEAB
H X X Storing Z
X H X Storing
X XH Z
L L L Transparent Current A data
L H L Storing Previous A data
†
A-to-B data flow is shown: B-to-A flow control is the same except that
it uses CEBA
‡
Data present before low-to-high transition of LEAB
CEAB
, LEBA, and OEBA.
is low
FUNCTION TABLE
(each octal register)
LATCH
†
A TO B
OUTPUT
B1–B8
}
occurring while
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
logic symbol
†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
3
6D
9
12D
5D
4
11D
10
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
2OEBA
56
54
55
1
3
2
5
29
C1
1D
To Seven Other Channels
C1
1D
52
1B1
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
31
30
28
26
27
15
C1
1D
To Seven Other Channels
C1
1D
42
2B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, VI (see Note 1) –0.5 V to VCC+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
(V
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DGG package 1 W. . . . . . . . . . . . . . . . . .
DL package 1.4 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions (see Note 3)
54ACT16543 74ACT16543
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
Dt/D
T
NOTES: 3. Unused pins (inputs and I/O) must be held high or low to prevent them from floating.
Supply voltage (see Note 4) 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
v Input transition rise or fall rate 0 10 0 10 ns/V
Operating free-air temperature –55 125 –40 85 °C
A
4. All VCC and GND pins must be connected to the proper voltage power supply.
CC
CC
0 V
0 V
CC
CC
V
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
54ACT16543, 74ACT16543
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
OH
I
mA
I
A
OL
I
24 mA
pF
UNIT
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50
= –24
= 50
=
m
{
m
{
CC
OH
V
OH
V
OL
I
I
I
OZ
I
CC
D
C
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1
A or B ports
w
I
CC
Control inputs VI = VCC or GND 5 V 4.5
i
A or B ports VO = VCC or GND 5 V 12
io
OH
IOH = –75 mA
OL
OL
IOL = 75 mA
}
VO = VCC or GND 5.5 V ±0.5 ±5 ±5
VI = VCC or GND, IO = 0 5.5 V 8 80 80
One input at 3.4 V ,
Other inputs at GND or V
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16543 74ACT16543
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
m
A
p
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
TA = 25°C 54ACT16543 74ACT16543
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration, LEAB or LEBA low 7.5 7.5 7.5 ns
Setup time, data before LEAB or LEBA↑ 2.5 2.5 2.5 ns
Hold time, data after LEAB or LEBA↑ 4 4 4 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
A or B
B or A
ns
LEBA
LEAB
A or B
ns
OEBA
OEAB
A or B
ns
OEBA
OEAB
A or B
ns
CEBA
CEAB
A or B
ns
CEBA
CEAB
A or B
ns
CpdPower dissipation capacitance per transceiver
C
f
pF
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (see Figure 1)
TA = 25°C 54ACT16543 74ACT16543
MIN TYP MAX MIN MAX MIN MAX
3.5 6.9 9.5 3.5 10.5 3.5 10.5
3.1 7.3 10.7 3.1 11.6 3.1 11.6
3.9 8.6 12.3 3.9 13.8 3.9 13.8
3.9 8.7 12.2 3.9 13.5 3.9 13.5
2.6 7.1 10.3 2.6 11.4 2.6 11.4
3.5 8.3 11.9 3.5 13.2 3.5 13.2
4.1 8.2 10.5 4.1 11.1 4.1 11.1
5 7.3 9.3 5 9.6 5 9.6
3.1 7.3 10.7 3.1 11.7 3.1 11.7
3.9 8.5 12.2 3.9 13.5 3.9 13.5
4.6 8.5 11 4.6 11.6 4.6 11.6
5.2 7.4 9.7 5.2 10.5 5.2 10.5
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
or
or
or
or
or
operating characteristics, V
p
p
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
p
= 25°C
A
Outputs enabled
Outputs disabled
= 50 pF,
L
p
= 1 MHz
45
12
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
S1
3 V
0 V
2 × V
Open
GND
CC
Timing Input
(see Note B)
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
Open
2 × V
GND
t
1.5 V
CC
3 V
0 V
h
3 V
0 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
1.5 V
50% V
PZH
50% V
VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
CC
CC
1.5 V
20% V
80% V
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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