54ACT16541, 74ACT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUPUTS
SCAS208A – JUNE 1992 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Flow-Through Architecture Optimizes
Family
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16541 are noninverting 16-bit buffers
composed of two 8-bit sections with separate
output-enable signals. For either 8-bit buffer
section, the two output-enable (1OE1
or 2OE1 and 2OE2) inputs must both be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
8-bit buffer section are in the high-impedance
state.
and 1OE2
54ACT16541 . . . WD PACKAGE
74ACT16541 . . . DL PACKAGE
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
V
CC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE2
The 74ACT16541 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16541 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE2 A
OE1
L L L L
L LH H
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
OUTPUT
Y
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
54ACT16541, 74ACT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUPUTS
SCAS208A – JUNE 1992 – REVISED APRIL 1996
logic symbol
†
1OE1
1OE2
2OE1
2OE2
1
48
24
25
47
1A1
46
1A2
44
1A3 1Y3
43
1A4 1Y4
41
1A5 1Y5
40
1A6 1Y6
38
1A7 1Y7
37
1A8 1Y8
36
2A1 2Y1
35
2A2
33
2A3 2Y3
32
2A4 2Y4
30
2A5 2Y5
29
2A6 2Y6
27
2A7
26
2A8
&
&
EN1
EN2
111
2
1Y1
3
1Y2
5
6
8
9
11
12
2
13
14
16
17
19
20
22
23
2Y2
2Y7
2Y8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
1OE1
48
1OE2
47
1A1 1Y1
To Seven Other Channels
2
2OE1
2OE2
2A1
24
25
36
13
2Y1
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
54ACT16541, 74ACT16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUPUTS
SCAS208A – JUNE 1992 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
54ACT16541 74ACT16541
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
CC
0 V
0 V
CC
CC
V
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54ACT16541, 74ACT16541
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
I
mA
I
50 µA
I
24 mA
PARAMETER
UNIT
A
Y
ns
OE
Y
ns
OE
Y
ns
CpdPower dissipation capacitance per buffer/driver
C
f
pF
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUPUTS
SCAS208A – JUNE 1992 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50 µ
OH
V
OH
V
OL
I
I
I
OZ
I
CC
‡
∆I
CC
C
i
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
o
= –24
OH
IOH = –75 mA
=
OL
=
OL
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
One input at 3.4 V ,
Other inputs at VCC or GND
VI = VCC or GND 5.5 V 4 pF
VO = VCC or GND 5 V 13 pF
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
5.5 V 3.9 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16541 74ACT16541
MIN TYP MAX MIN MAX MIN MAX
V
V
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT16541 74ACT16541
MIN TYP MAX MIN MAX MIN MAX
3.1 5.9 7.9 3.1 9 3.1 9
2.7 6.3 8.3 2.7 9.2 2.7 9.2
2.8 6.5 8.9 2.8 9.7 2.8 9.7
3.5 7.5 9.9 3.5 11 3.5 11
4.5 8.5 10.3 4.5 11.3 4.5 11.3
4.9 8 9.9 4.9 10.7 4.9 10.7
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
Outputs disabled
= 50 pF,
L
p
= 1 MHz
40
9.5
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
54ACT16541, 74ACT16541
16-BIT BUFFERS/DRIVERS
SCAS208A – JUNE 1992 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
500 Ω
500 Ω
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
WITH 3-STATE OUPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
V
CC
V
3 V
0 V
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
1.5 V
t
PLZ
50% V
t
PHZ
50% V
CC
CC
1.5 V
20% V
80% V
CC
CC
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
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5
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