Texas Instruments 74ACT11652DWR, 74ACT11652DW Datasheet

74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes PCB Layout
D
Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at 125°C
description
This device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Enable GAB and G
BA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and G
BA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The 74ACT11652 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GAB
A1 A2 A3
A4 GND GND GND GND
A5
A6
A7
A8
G
BA
CAB SAB B1 B2 B3 B4 V
CC
V
CC
B5 B6 B7 B8 CBA SBA
DW PACKAGE
(TOP VIEW)
74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
BUS A
BUS B
BUS A
BUS B
GAB GBA CAB CBA SAB SBA GAB GBA CAB CBA SAB SBA
LLXXXL HHXXLX
REAL-TIME TRANSFER BUS B TO BUS A REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
BUS B
GAB GBA CAB CBA SAB SBA GAB GBA CAB CBA SAB SBA
XH X X X L L H or L H or L X H LXX XX LH↑↑XX
STORAGE FROM A AND/OR B TRANSFER STORED DATA TO A AND/OR B
Figure 1. Bus Transfer Diagram
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
GAB GBA CAB CBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
L H H or L H or L X X
p
p
Isolation
L H X X
Input
Input
Store A and B data
X H H or L X X Input Unspecified
Store A, hold B
H H X
X Input Output Store A in both registers
L X H or L X X Unspecified
Input Hold A, store B
L L X X
Output Input Store B in both registers
L L X X X L
p
p
Real-time B data to A bus
L LXH or L X H
Output
Input
Stored B data to A bus
H H X X L X
p
p
Real-time A data to B bus
H H H or L XHX
Input
Output
Stored A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus and
stored B data to A bus
The data-output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data-input functions are always enabled, i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.
logic symbol
§
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
5
5
B8
B7
B6
B5
B4
B3
B2
B1
17
18
19
20
23
24
25
26
A8
A7
A6
A5
A4
A3
A2
A1
SAB
CAB
SBA
CBA
G
BA
2
27
28
15
16
14
16D7
7
4D
G7
C6
G5
C4
EN2 [AB]
EN1 [BA]
2
1
1
1
1
1
GBA
3
4
5
10
11
12
13
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