74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Registers and Enables for A
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes
PCB Layout
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
description
This device consists of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Enable GAB and G
BA are provided to control the
transceiver functions. SAB and SBA control pins
are provided to select whether real-time or stored
data is transferred. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. A low input
level selects real-time data, and a high selects
stored data. Figure 1 illustrates the four
fundamental bus-management functions that can
be performed with the octal bus transceivers and
registers.
Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock pins (CAB or CBA), regardless of the select or enable control pins. When SAB and SBA are
in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by
simultaneously enabling GAB and G
BA. In this configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
The 74ACT11652 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
G
BA
CAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CBA
SBA
DW PACKAGE
(TOP VIEW)
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BUS A
BUS B
BUS A
BUS B
GAB GBA CAB CBA SAB SBA GAB GBA CAB CBA SAB SBA
LLXXXL HHXXLX
REAL-TIME TRANSFER BUS B TO BUS A REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
BUS B
GAB GBA CAB CBA SAB SBA GAB GBA CAB CBA SAB SBA
XH↑ X X X L L H or L H or L X H
LXX↑ XX
LH↑↑XX
STORAGE FROM A AND/OR B TRANSFER STORED DATA TO A AND/OR B
Figure 1. Bus Transfer Diagram
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
†
GAB GBA CAB CBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
L H H or L H or L X X
p
p
Isolation
L H ↑ ↑ X X
Input
Input
Store A and B data
X H ↑ H or L X X Input Unspecified
†
Store A, hold B
H H ↑ ↑ X
‡
X Input Output Store A in both registers
L X H or L ↑ X X Unspecified
†
Input Hold A, store B
L L ↑ ↑ X X
‡
Output Input Store B in both registers
L L X X X L
p
p
Real-time B data to A bus
L LXH or L X H
Output
Input
Stored B data to A bus
H H X X L X
p
p
Real-time A data to B bus
H H H or L XHX
Input
Output
Stored A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus and
stored B data to A bus
†
The data-output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data-input functions are always enabled,
i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.
logic symbol
§
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
5
5
B8
B7
B6
B5
B4
B3
B2
B1
17
18
19
20
23
24
25
26
A8
A7
A6
A5
A4
A3
A2
A1
SAB
CAB
SBA
CBA
G
BA
2
27
28
15
16
14
16D7
7
4D
G7
C6
G5
C4
EN2 [AB]
EN1 [BA]
2
1
≥1
≥1
1
1
GBA
3
4
5
10
11
12
13
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
To Seven Other Channels
B1
26
A1
2
SAB
CAB
SBA
CBA
GAB
G
BA
27
28
15
16
14
1
Channels
One of Eight
1D
C1
C1
1D
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 1.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 24 mA
∆t/∆V Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
4.5 V 4.4 4.4
I
OH
= –50
m
A
5.5 V 5.4 5.4
V
OH
4.5 V 3.94 3.8
V
I
OH
= –24
mA
5.5 V 4.94 4.8
IOH = – 75 mA
{
5.5 V 3.85
4.5 V 0.1 0.1
I
OL
=
50
m
A
5.5 V 0.1 0.1
V
OL
4.5 V 0.36 0.44
V
I
OL
=
24 mA
5.5 V 0.36 0.44
IOL = 75 mA
{
5.5 V 1.65
I
OZ
A or B ports‡VO = VCC or GND 5.5 V ±0.5 ±5
m
A
I
I
GAB or GBA VI = VCC or GND 5.5 V ±0.1 ±1
m
A
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 80
m
A
D
I
CC
§
One input at 3.4 V , Other inputs at GND or V
CC
5.5 V 0.9 1 mA
C
i
GAB or GBA VI = VCC or GND 5 V 4.5 pF
C
o
A or B ports VO = VCC or GND 5 V 12 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25°C
PARAMETER
MIN MAX
MIN
MAX
UNIT
f
clock
Clock frequency 0 105 0 105 MHz
t
w
Pulse duration, CAB or CBA high or low 4.8 4.8 ns
t
su
Setup time, A before CLK↑ or B before CBA↑ 4 4 ns
t
h
Hold time, A after CAB↑ or B after CBA↑ 2.5 2.5 ns
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
FROM TO
TA = 25°C
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
f
max
105 105 MHz
t
PLH
3.8 7 9.9 3.8 11.1
t
PHL
A or B
B or A
3.4 6.7 10.7 3.4 11.6
ns
t
PLH
5.4 8.4 11.8 5.4 13.1
t
PHL
CBA or CAB
A or B
6.1 9.4 13.1 6.1 14.4
ns
t
PLH
SBA or SAB
†
2.8 6.2 10.1 2.8 11
t
PHL
with A or B high
A or B
5.5 8.7 12.1 5.5 13.3
ns
t
PLH
SBA or SAB
†
4.9 7.8 11 4.9 12.2
t
PHL
with A or B low
A or B
3.9 7.5 11.6 3.9 12.6
ns
t
PZH
3.3 7.2 11.4 3.3 12.6
t
PZL
GBA
A
4.1 7.8 12.6 4.1 13.8
ns
t
PHZ
5.2 7.2 9.3 5.2 9.9
t
PLZ
GBA
A
4.8 6.7 8.6 4.8 9.3
ns
t
PZH
5.1 9.1 13.4 5.1 15.2
t
PZL
GAB
B
5.8 9.7 14.2 5.8 16.1
ns
t
PHZ
3.4 6.8 9.7 3.4 10.3
t
PLZ
GAB
B
3.1 6 8.8 3.1 9.3
ns
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, V
CC
= 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
59
p
CpdPower dissipation capacitance per transceiver
Outputs disabled
C
L
= 50 pF,
f
= 1 MHz
14
pF
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
Data Input
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
50% V
CC
50% V
CC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% V
CC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
[
V
CC
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
3 V
0 V
1.5 V 1.5 V
t
w
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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