74ACT11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS069B – AUGUST 1988 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Generates Either Odd or Even Parity for
Nine Data Lines
D
Cascadable for n-Bits Parity
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic 300-mil DIPs (N)
description
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a
bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by
cascading.
The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity
tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels.
When XMIT
is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even
number of inputs (A through I) are high and P ARITY I/O is forced to a low logic level, or when an odd number
of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up
or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
NUMBER OF INPUTS
(A–I ) THAT
ARE HIGH
XMIT
INPUT
PARITY
I/O
PARITY
ERROR
OUTPUT
0, 2, 4, 6, 8 l H H
1, 3, 5, 7, 9 l L H
h h H
0, 2, 4, 6, 8
h l L
h h L
1, 3, 5, 7, 9
h l H
h = high input level, H = high output level, I = low input level,
L = low output level
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
B
A
PARITY I/O
GND
PARITY ERROR
XMIT
I
C
D
E
V
CC
F
G
H
D OR N PACKAGE
(TOP VIEW)
74ACT11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS069B – AUGUST 1988 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
2k
2, 1
N2
1
EN 1XMIT
I
H
G
F
E
D
C
B
A
6
7
8
9
10
12
13
14
1
2
PARITY ERROR
PARITY I/O
5
3
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
XMIT
PARITY I/O
I
H
G
F
E
D
C
B
A
6
3
7
8
9
10
12
13
14
1
2
PARITY
ERROR
5
74ACT11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS069B – AUGUST 1988 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.25 W. . . . . . . . . . . . . . . . . . .
N package 1.1 W. . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 24 mA
Dt/D
v Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
74ACT11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS069B – AUGUST 1988 – REVISED APRIL 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
4.5 V 4.4 4.4
I
OH
= –50
m
A
5.5 V 5.4 5.4
V
OH
4.5 V 3.94 3.8
V
OH
I
OH
= –24
mA
5.5 V 4.94 4.8
IOH = –75 mA
†
5.5 V 3.85
4.5 V 0.1 0.1
I
L
= 50
m
A
5.5 V 0.1 0.1
V
OL
4.5 V 0.36 0.44
V
OL
I
OL
=
24 mA
5.5 V 0.36 0.44
IOL = 75 mA
†
5.5 V 1.65
I
OZ
PARITY I/O VO = VCC or GND 5.5 V ±0.5 ±5
m
A
I
I
Except PARITY I/O VI = VCC or GND 5.5 V ±0.1 ±1
m
A
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 80
m
A
One input at 3.4 V ,
D
I
CC
‡
,
Other inputs at GND or V
CC
5.5 V
0.91mA
C
i
VI = VCC or GND 5 V 3.5 pF
C
o
PARITY I/O VO = VCC or GND 5 V 8 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
switching characteristics over recomended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
t
PLH
2.7 6.1 9 2.7 10.4
t
PHL
Any A–I
PARITY I/O
3.6 7.3 10.8 3.6 12
ns
t
PLH
3 6.9 9.7 3 11.3
t
PHL
Any A–I
PARITY ERROR
3.9 7.7 11.4 3.9 12.9
ns
t
PLH
2.2 4.6 6.8 2.2 7.7
t
PHL
PARITY I/O
PARITY ERROR
3.1 5.6 8.3 3.1 9.1
ns
t
PZH
1.8 4.2 6.3 1.8 7.3
t
PZL
XMIT
PARITY I/O
3 6.3 9.4 3 11.4
ns
t
PHZ
4.7 6.5 7.9 4.7 8.5
t
PLZ
XMIT
PARITY I/O
4.1 6 7.3 4.1 7.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
Outputs enabled
p
56
p
CpdPower dissipation capacitance
Outputs disabled
C
L
=
50 pF
,
f
= 1 MHz
50
pF
74ACT11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS069B – AUGUST 1988 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
GND
Open
TEST S1
t
PHL
t
PLH
1.5 V 1.5 V
3 V
0 V
50% V
CC
50% V
CC
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
[
V
CC
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
3 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf= 3 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...