Texas Instruments 74ACT11139PWR, 74ACT11139PWLE, 74ACT11139N, 74ACT11139DR, 74ACT11139D Datasheet
74ACT11139
DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
SCAS175A – SEPTEMBER 1991 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporates Two Enable Inputs to Simplify
Cascading and/or Data Reception
D
Fully Synchronous Operation for Counting
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
The 74ACT1 1139 is designed for use in high-performance memory-decoding or data-routing applications that
require very short propagation delay times. In high-performance memory systems, this decoder is used to
minimize the effects of system decoding.
The 74ACT11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low
enables (1G
or 2G) can be used as data lines in demultiplexing applications. This decoder/demultiplexer
features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74ACT11139 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
G B A Y0 Y1 Y2 Y3
H X X H H H H
L LLLHHH
L LHHLHH
L HLHHLH
L H H H H H L
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
1Y0
1A
1B
1G
V
CC
2G
2A
2B
D, N, OR PW PACKAGE
(TOP VIEW)
74ACT11139
DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
SCAS175A – SEPTEMBER 1991 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1G
DMUX
1
15
1A
13
1Y0
16
0
1Y1
1
1
1Y2
2
2
1Y3
3
3
2
14
1B
10
2A
11
2Y0
5
2Y1
6
2Y2
7
2Y3
8
9
2B
2G
G
0
3
logic diagram (positive logic)
1A
1Y3
1Y2
1Y1
1Y0
15
16
1
2
3
1B
14
13
2A
2Y3
2Y2
2Y1
2Y0
10
6
7
8
2B
9
11
5
2G
1G
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