Datasheet 74ACT11004PWR, 74ACT11004N, 74ACT11004DWR, 74ACT11004DW, 74ACT11004DBR Datasheet (Texas Instruments)

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74ACT11004
HEX INVERTER
SCAS215B – JANAURY 1988 – REVISED JUNE 1997
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
D
Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at 125°C
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages and Standard Plastic (N) 300-mil DIPs
description
This device contains six independent inverters. It performs the Boolean function Y = A. The 74ACT11004 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each inverter)
INPUTAOUTPUT
Y
H L L H
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
20
1A
19
2A
1Y
1
18
3A
13
4A
2Y
2
12
5A
11
6A
3Y
3
4Y
8
5Y
9
6Y
10
1
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
1Y 2Y
3Y GND GND GND GND
4Y
5Y
6Y
1A 2A 3A NC V
CC
V
CC
NC 4A 5A 6A
DB, DW, N, OR PW PACKAGE
(TOP VIEW)
NC – No internal connection
74ACT11004 HEX INVERTER
SCAS215B – JANAURY 1988 – REVISED JUNE 1997
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1Y1A
2Y2A
3Y3A
4Y4A
5Y5A
6Y6A
20
19
18
13
12
11
1
2
3
8
9
10
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
recommended operating conditions
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 24 mA t/v Input transition rise or fall rate 0 10 ns/V T
A
Operating free-air temperature –40 85 °C
74ACT11004
HEX INVERTER
SCAS215B – JANAURY 1988 – REVISED JUNE 1997
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
4.5 V 4.4 4.4
I
OH
= –50
m
A
5.5 V 5.4 5.4
V
OH
4.5 V 3.94 3.8
V
I
OH
= –24
mA
5.5 V 4.94 4.8
IOH = –75 mA
5.5 V 3.85
4.5 V 0.1 0.1
I
OL
=
50
m
A
5.5 V 0.1 0.1
V
OL
4.5 V 0.36 0.44
V
I
OL
=
24 mA
5.5 V 0.36 0.44
IOL = 75 mA
5.5 V 1.65
I
I
VI = VCC or GND 5.5 V ±0.1 ±1
m
A
I
CC
VI = VCC or GND, IO = 0 5.5 V 4 40
m
A
I
CC
One input at 3.4 V , Other inputs at GND or V
CC
5.5 V 0.9 1 mA
C
i
VI = VCC or GND 5 V 3.5 pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ns.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
t
PLH
1.5 5.3 9 1.5 9.7
t
PHL
A
Y
1.5 6.4 8.7 1.5 9.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per inverter CL = 50 pF, f = 1 MHz 32 pF
74ACT11004 HEX INVERTER
SCAS215B – JANAURY 1988 – REVISED JUNE 1997
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WA VEFORMSLOAD CIRCUIT
Input
(see Note B)
50% V
CC
50% V
CC
t
PHL
t
PLH
3 V
Output
V
OL
V
OH
0 V
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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