Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16374 are 16-bit edge-triggered D-type
flip-flops with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
54AC16374 . . . WD PACKAGE
74AC16374 . . . DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
Maximum power package dissipation at TA = 55°C (in still air)(see Note 2): DL package 1.2 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
3 V2.92.92.9
IOH = –50 µA
V
OH
V
OL
I
I
I
OZ
I
CC
C
i
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
o
IOH = –4 mA3 V2.582.482.48
IOL = –24 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA3 V0.360.440.44
= 24
OL
IOL = 75 mA
VI = VCC or GND5.5 V±0.1±1±1µA
VO = VCC or GND5.5 V±0.5±5±5µA
VI = VCC or GND,IO = 05.5 V88080µA
VI = VCC or GND5 V3pF
VO = VCC or GND5 V11pF
†
†
4.5 V4.44.44.4
5.5 V5.45.45.4
4.5 V3.943.83.8
5.5 V4.944.84.8
5.5 V3.853.85
3 V0.10.10.1
4.5 V0.10.10.1
5.5 V0.10.10.1
4.5 V0.360.440.44
5.5 V0.360.440.44
5.5 V1.651.65
TA = 25°C54AC1637474AC16374
MINTYPMAXMINMAXMINMAX
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
UNIT
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
CpdPower dissipation capacitance per flip-flop
C
50 pF
f
pF
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C54AC1637474AC16374
MINMAXMINMAXMINMAX
f
clock
t
w
t
su
t
h
timing requirements over recommended operating free-air temperature range
V
CC
f
clock
t
w
t
su
t
h
Clock frequency060060060MHz
Pulse durationCLK high or low8.38.38.3ns
Setup time, data before CLK↑7.57.57.5ns
Hold time, data after CLK↑000ns
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C54AC1637474AC16374
MINMAXMINMAXMINMAX
Clock frequency010001000100MHz
Pulse durationCLK high or low555ns
Setup time, data before CLK↑555ns
Hold time, data after CLK↑000ns
switching characteristics over recommended operating free-air temperature range
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C54AC1637474AC16374
MINTYPMAXMINMAXMINMAX
606060MHz
4.912.2154.9174.917
4.811.914.34.815.74.815.7
4.311.914.74.316.84.316.8
5.315.518.75.321.25.321.2
47.3949.849.8
3.87.18.83.89.43.89.4
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROMTO
(INPUT)(OUTPUT)
switching characteristics over recommended operating free-air temperature range
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C54AC1637474AC16374
MINTYPMAXMINMAXMINMAX
100100100MHz
3.87.69.53.810.83.810.8
3.87.69.53.810.63.810.6
3.27.293.210.23.210.2
3.88.710.73.812.13.812.1
3.767.53.78.23.78.2
3.55.87.33.57.93.57.9
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROMTO
(INPUT)(OUTPUT)
operating characteristics, VCC = 5 V, TA = 25°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PARAMETERTEST CONDITIONSTYPUNIT
p
p
p
p
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Outputs enabled
Outputs disabled
p
,
=
L
= 1 MHz
49
32
p
5
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
50%50%
VOLTAGE WAVEFORMS
S1
GND
V
CC
0 V
Open
Timing Input
Data Input
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
50%
VOLTAGE WAVEFORMS
50%
2 × V
t
h
50%
Open
GND
CC
V
0 V
V
0 V
CC
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50%50%
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
CC
CC
50%
20% V
80% V
50%
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
CC
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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