54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
3-State True Outputs
D
Full Parallel Access for Loading
D
Flow-Through Architecture Optimizes
Family
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16374 are 16-bit edge-triggered D-type
flip-flops with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
54AC16374 . . . WD PACKAGE
74AC16374 . . . DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L XX Q
L ↓ XQ
H X X Z
OUTPUT
Q
0
0
logic symbol
†
1
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
2EN
1D
2D
C1
C2
2
11
12
13
14
16
17
19
20
22
23
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
1OE
1CLK
1D1
1
48
47
C1
1D
To Seven Other Channels
2CLK
1Q1
2OE
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Maximum power package dissipation at TA = 55°C (in still air)(see Note 2): DL package 1.2 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54AC16374, 74AC16374
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
mA
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
recommended operating conditions (see Note 3)
54AC16374 74AC16374
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 3 5 5.5 3 5 5.5 V
CC
VCC = 3 V 2.1 2.1
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5 V
VCC = 5.5 V 1.65 1.65
VCC = 3 V –4 –4
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24
3.15 3.15
1.35 1.35
CC
CC
–24 –24
24 24
0 V
0 V
CC
CC
V
V
V
V
mA
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
3 V 2.9 2.9 2.9
IOH = –50 µA
V
OH
V
OL
I
I
I
OZ
I
CC
C
i
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
o
IOH = –4 mA 3 V 2.58 2.48 2.48
IOL = –24 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.44 0.44
= 24
OL
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
VI = VCC or GND 5 V 3 pF
VO = VCC or GND 5 V 11 pF
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
TA = 25°C 54AC16374 74AC16374
MIN TYP MAX MIN MAX MIN MAX
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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UNIT
UNIT
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
CpdPower dissipation capacitance per flip-flop
C
50 pF
f
pF
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C 54AC16374 74AC16374
MIN MAX MIN MAX MIN MAX
f
clock
t
w
t
su
t
h
timing requirements over recommended operating free-air temperature range
V
CC
f
clock
t
w
t
su
t
h
Clock frequency 0 60 0 60 0 60 MHz
Pulse duration CLK high or low 8.3 8.3 8.3 ns
Setup time, data before CLK↑ 7.5 7.5 7.5 ns
Hold time, data after CLK↑ 0 0 0 ns
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C 54AC16374 74AC16374
MIN MAX MIN MAX MIN MAX
Clock frequency 0 100 0 100 0 100 MHz
Pulse duration CLK high or low 5 5 5 ns
Setup time, data before CLK↑ 5 5 5 ns
Hold time, data after CLK↑ 0 0 0 ns
switching characteristics over recommended operating free-air temperature range
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54AC16374 74AC16374
MIN TYP MAX MIN MAX MIN MAX
60 60 60 MHz
4.9 12.2 15 4.9 17 4.9 17
4.8 11.9 14.3 4.8 15.7 4.8 15.7
4.3 11.9 14.7 4.3 16.8 4.3 16.8
5.3 15.5 18.7 5.3 21.2 5.3 21.2
4 7.3 9 4 9.8 4 9.8
3.8 7.1 8.8 3.8 9.4 3.8 9.4
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
switching characteristics over recommended operating free-air temperature range
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54AC16374 74AC16374
MIN TYP MAX MIN MAX MIN MAX
100 100 100 MHz
3.8 7.6 9.5 3.8 10.8 3.8 10.8
3.8 7.6 9.5 3.8 10.6 3.8 10.6
3.2 7.2 9 3.2 10.2 3.2 10.2
3.8 8.7 10.7 3.8 12.1 3.8 12.1
3.7 6 7.5 3.7 8.2 3.7 8.2
3.5 5.8 7.3 3.5 7.9 3.5 7.9
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
operating characteristics, VCC = 5 V, TA = 25°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
p
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Outputs enabled
Outputs disabled
p
,
=
L
= 1 MHz
49
32
p
5
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
50% 50%
VOLTAGE WAVEFORMS
S1
GND
V
CC
0 V
Open
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
50%
VOLTAGE WAVEFORMS
50%
2 × V
t
h
50%
Open
GND
CC
V
0 V
V
0 V
CC
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% 50%
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
CC
CC
50%
20% V
80% V
50%
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
CC
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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