54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
3-State True Outputs
D
Full Parallel Access for Loading
D
Flow-Through Architecture Optimizes
Family
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16373 are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers. The device can be used as two 8-bit
latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are
latched at the levels set up at the D inputs.
54AC16373 . . . WD PACKAGE
74AC16373 . . . DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74AC16373 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C1
2EN
C2
1D
2D
2
11
12
13
14
16
17
19
20
22
23
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
1OE
1LE
1D1
1
48
47
C1
1D
To Seven Other Channels
2
1Q1
2OE
2LE
2D1
24
25
36
C1
1D
To Seven Other Channels
13
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54AC16373, 74AC16373
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
mA
I
mA
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
recommended operating conditions (see Note 3)
54AC16373 74AC16373
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 3 5 5.5 3 5 5.5 V
CC
VCC = 3 V 2.1 2.1
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5 V
VCC = 5.5 V 1.65 1.65
VCC = 3 V –4 –4
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24
3.15 3.15
1.35 1.35
CC
CC
–24 –24
24 24
0 V
0 V
CC
CC
V
V
V
V
mA
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
3 V 2.9 2.9 2.9
IOH = –50 µA
V
OH
V
OL
I
I
I
OZ
I
CC
C
i
C
†
o
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
IOH = –4 mA 3 V 2.58 2.48 2.48
= –24
OL
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.44 0.44
= 24
OL
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
VI = VCC or GND 5 V 4.5 pF
VO = VCC or GND 5 V 12 pF
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V 3.85 3.85
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65 1.65
TA = 25°C 54AC16373 74AC16373
MIN TYP MAX MIN MAX MIN MAX
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
UNIT
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
CpdPower dissipation capacitance per latch
C
50 pF
f
pF
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C 54AC16373 74AC16373
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
timing requirements over recommended operating free-air temperature range,
V
CC
t
w
t
su
t
h
switching characteristics over recommended operating free-air temperature range,
V
CC
Pulse duration, LE high 5 5 5 ns
Setup time, data before LE↓ 1.5 1.5 1.5 ns
Hold time, data after LE↓ 3 3 3 ns
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C 54AC16373 74AC16373
MIN MAX MIN MAX MIN MAX
Pulse duration, LE high 4 4 4 ns
Setup time, data before LE↓ 1.5 1.5 1.5 ns
Hold time, data after LE↓ 2.5 2.5 2.5 ns
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C 54AC16373 74AC16373
MIN TYP MAX MIN MAX MIN MAX
3.7 10.6 13.4 3.7 15.1 3.7 15.1
4.3 11.3 14 4.3 14.8 4.3 14.8
4.6 12.9 15.8 4.6 18.6 4.6 18.6
4.5 12.1 14.6 4.5 16.4 4.5 16.4
4.2 11.8 14.8 4.2 17.5 4.2 17.5
5.4 16.3 19.8 5.4 22.3 5.4 22.3
4.2 7.9 9.5 4.2 10.2 4.2 10.2
3.8 7.1 8.9 3.8 9.8 3.8 9.8
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
operating characteristics, VCC = 5 V, TA = 25°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
FROM TO
(INPUT) (OUTPUT)
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA = 25°C 54AC16373 74AC16373
MIN TYP MAX MIN MAX MIN MAX
3.1 6.7 8.5 3.1 9.7 3.1 9.7
3.5 7.3 9.1 3.5 10.1 3.5 10.1
3.8 8.2 10.2 3.8 11.9 3.8 11.9
3.6 7.8 9.7 3.6 10.9 3.6 10.9
3.5 7.4 9.4 3.5 10.8 3.5 10.8
4.3 9.1 11.3 4.3 12.8 4.3 12.8
3.9 6.6 8 3.9 8.8 3.9 8.8
3.7 5.9 7.4 3.7 8.1 3.7 8.1
Outputs enabled
Outputs disabled
p
,
=
L
= 1 MHz
43
p
5
5
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
50% 50%
VOLTAGE WAVEFORMS
S1
GND
V
CC
0 V
CC
Open
Timing Input
(see Note B)
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
50%
VOLTAGE WAVEFORMS
50%
2 × V
t
h
50%
Open
GND
CC
V
0 V
V
0 V
CC
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
50% 50%
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
t
PLH
50% V
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
PZL
t
PZH
CC
CC
50%
20% V
80% V
50%
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
CC
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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