54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
t
Family
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
Flow-Through Architecture Optimizes PCB
Layout
D
Distributed VCC and GND Configuration
Minimizes High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA T ypical Latch-Up Immunity at 125°C
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Package,
300-mil Shrink Small-Outline (DL) Package
Using 25-mil Center-to-Center Pin Spacings
and 380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
description
The ’AC16245 are 16-bit bus transceivers
organized as dual-octal noninverting 3-state
transceivers designed for asynchronous two-way
communication between data buses. The control
function implementation minimizes external timing requirements
These devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus,
depending upon the logic level at the direction
control (DIR) input. The output-enable input (OE
)
can be used to disable the devices so that the
buses are effectively isolated.
The 74AC16245 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16245 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
CONTROL
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to bus
H X Isolation
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
54AC16245 . . . WD PACKAGE
74AC16245 . . . DGG OR DL PACKAGE
(TOP VIEW)
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
5
4
1
1
2
1
2OE
1OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
G3
48
3 EN1 [BA]
1
1DIR
G6
25
6 EN4 [BA]
24
2DIR
47
1A1
46
1A2
44
1A3
43
1A4
41
1A5
40
1A6
38
1A7
37
1A8
36
2A1
35
2A2
33
2A3
32
2A4
30
2A5
29
2A6
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
3 EN2 [AB]
6 EN5 [AB]
27
2A7
26
2A8
2B7
22
2B8
23
1
1
logic diagram (positive logic)
To Seven Other Transceivers
1B1
2
1A1
1DIR
47
1
48
1OE
2B1
13
2A1
2DIR
36
24
25
To Seven Other Transceivers
2OE
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package 0.85 W. . . . . . . . . . . . . . . .
DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16245 74AC16245
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage (see Note 4) 3 5 5.5 3 5 5.5 V
VCC = 3 V 2.1 2.1
V
IH
High-level input voltage
VCC = 4.5 V
3.15 3.15
V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
V
IL
Low-level input voltage
VCC = 4.5 V
1.35 1.35
V
VCC = 5.5 V 1.65 1.65
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 3 V –4 –4
I
OH
High-level output current
VCC = 4.5 V
–24 –24
mA
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
I
OL
Low-level output current
VCC = 4.5 V
24 24
mA
VCC = 5.5 V 24 24
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTES: 3. All unused pins (input and I/O) must be held high or low to prevent them from floating.
4. All VCC and GND pins must be connected to the proper voltage power supply.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C 54AC16245 74AC16245
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
3 V 2.9 2.9 2.9
IOH = –50 µA
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
V
OH
IOH = –4 mA 3 V 2.58 2.48 2.48
V
4.5 V 3.94 3.8 3.8
I
OH
= –24
mA
5.5 V 4.94 4.8 4.8
IOH = –75 mA
†
5.5 V 3.85 3.85
3 V 0.1 0.1 0.1
IOL = 50 µA
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
V
OL
IOL = 12 mA 3 V 0.36 0.44 0.44
V
4.5 V 0.36 0.44 0.44
I
OL
=
24 mA
5.5 V 0.36 0.44 0.44
IOL = 75 mA
†
5.5 V 1.65 1.65
I
I
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
OZ
VI = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
C
i
VI = VCC or GND 5 V 4.5
p
C
o
VI = VCC or GND 5 V 16
pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (see Figure 1)
FROM TO
TA = 25°C 54AC16245 74AC16245
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
2.5 7.6 10.4 2.5 11.9 2.5 11.9
t
PHL
A or B
B or A
3.1 9 12.3 3.1 13.5 3.1 13.5
ns
t
PZH
2.8 8.6 11.8 2.8 13.2 2.8 13.2
t
PZL
OE
A or B
3.9 12 16.2 3.9 18 3.9 18
ns
t
PHZ
5.3 8.4 10.4 5.3 11.2 5.3 11.2
t
PLZ
OE
A or B
4.4 7.7 9.7 4.4 10.3 4.4 10.3
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (see Figure 1)
FROM TO
TA = 25°C 54AC16245 74AC16245
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
2 4.6 6.9 2 7.9 2 7.9
t
PHL
A or B
B or A
2.5 5.2 7.9 2.5 8.9 2.5 8.9
ns
t
PZH
2.3 4.9 7.5 2.3 8.6 2.3 8.6
t
PZL
OE
A or B
3 6.2 9.5 3 10.7 3 10.7
ns
t
PHZ
5 7.2 9.1 5 9.8 5 9.8
t
PLZ
OE
A or B
4.2 6.2 8.1 4.2 8.7 4.2 8.7
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
43
p
CpdPower dissipation capacitance per latch
Outputs disabled
C
L
= 50 pF, f = 1 MHz
8
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
50%
50%
50% 50%
[
V
CC
V
CC
0 V
50% V
CC
50% V
CC
V
OH
V
OL
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
V
CC
GND
Open
Input
Output
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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