Texas Instruments 74AC16245DLR, 74AC16245DL, 74AC16245DGGR Datasheet
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
t
Family
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
Flow-Through Architecture Optimizes PCB
Layout
D
Distributed VCC and GND Configuration
Minimizes High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA T ypical Latch-Up Immunity at 125°C
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Package,
300-mil Shrink Small-Outline (DL) Package
Using 25-mil Center-to-Center Pin Spacings
and 380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
description
The ’AC16245 are 16-bit bus transceivers
organized as dual-octal noninverting 3-state
transceivers designed for asynchronous two-way
communication between data buses. The control
function implementation minimizes external timing requirements
These devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus,
depending upon the logic level at the direction
control (DIR) input. The output-enable input (OE
)
can be used to disable the devices so that the
buses are effectively isolated.
The 74AC16245 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16245 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
CONTROL
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to bus
H X Isolation
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
54AC16245 . . . WD PACKAGE
74AC16245 . . . DGG OR DL PACKAGE
(TOP VIEW)
54AC16245, 74AC16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
5
4
1
1
2
1
2OE
1OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
G3
48
3 EN1 [BA]
1
1DIR
G6
25
6 EN4 [BA]
24
2DIR
47
1A1
46
1A2
44
1A3
43
1A4
41
1A5
40
1A6
38
1A7
37
1A8
36
2A1
35
2A2
33
2A3
32
2A4
30
2A5
29
2A6
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
3 EN2 [AB]
6 EN5 [AB]
27
2A7
26
2A8
2B7
22
2B8
23
1
1
logic diagram (positive logic)
To Seven Other Transceivers
1B1
2
1A1
1DIR
47
1
48
1OE
2B1
13
2A1
2DIR
36
24
25
To Seven Other Transceivers
2OE
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